-------------------------------------------------------------------------------
-- Title      :  CRC generator test bench
-- Project    :  Bluetooth baseband core
-------------------------------------------------------------------------------
-- File        : crc_gen_tb.vhd
-- Author      : Jamil Khatib  ([email protected])
-- Organization: OpenIPCore Project
-- Created     : 2000/12/07
-- Last update : 2000/12/09
-- Platform    : 
-- Simulators  : Modelsim 5.3XE/Windows98
-- Synthesizers: 
-- Target      : 
-- Dependency  : ieee.std_logic_1164
--               bluetooth.components_pkg
--               pck_crc16_d1 Package
-------------------------------------------------------------------------------
-- Description: CRC generator core test bench
-------------------------------------------------------------------------------
-- Copyright (c) 2000 Jamil Khatib
-- 
-- This VHDL design file is an open design; you can redistribute it and/or
-- modify it and/or implement it after contacting the author
-- You can check the draft license at
-- http://www.opencores.org/OIPC/license.shtml

-------------------------------------------------------------------------------
-- Revisions  :
-- Revision Number :   1
-- Version         :   0.1
-- Date            :   7 Dec 2000
-- Modifier        :   Jamil Khatib ([email protected])
-- Desccription    :   Created
-- Known bugs      :   
-- To Optimze      :   
-------------------------------------------------------------------------------


library ieee;
use ieee.std_logic_1164.all;

use work.pck_crc16_d1.all;

library bluetooth;
use bluetooth.components_pkg.all;

entity crc_gen_tb is

end crc_gen_tb;

architecture crc_gen_beh_tb of crc_gen_tb is

  signal reset : std_logic := '0';      -- Reset signal
  signal clk   : std_logic := '0';      -- clock signal

  constant init_value : std_logic_vector(15 downto 0) := "1100100100000000";
                                        -- lfst init value

  signal initsignal : std_logic_vector(15 downto 0) := init_value;

  constant bitstream : std_logic_vector(19 downto 0) := "01110110010101100101";

  signal enable : std_logic;            -- crc enable
  signal dout   : std_logic;            -- Dataout
  signal din    : std_logic;            -- DataIn

  signal reg_value : std_logic_vector(15 downto 0) := (others => '0');
                                        -- Regsiter

begin  -- crc_gen_beh_tb


--reset <= '1' after 5 ns;
  clk <= not clk after 10 ns;

  uut : crc_gen_ent
    port map (
      clk     => clk,
      rst     => reset,
      en      => enable,
      DataIn  => din,
      DataOut => dout,
      Init    => initsignal
      );

  process
  begin  -- process
    if reset = '0' then
      wait for 5 ns;

      reset  <= '1';
      enable <= '0';
      din    <= '0';


    else
      wait until clk = '0';
      enable <= '1';

      wait until clk = '1';

      reg_value <= init_value;
--      reg_value <=  nextCRC16_D1( bitstream(i), init_value );


      for i in 0 to bitstream'length-1 loop


        din <= bitstream(i);

        wait until clk = '1';

        assert reg_value(0) = Dout report "Incorrect output, en = 1" severity error;

        reg_value <= nextCRC16_D1( bitstream(i), reg_value );


      end loop;  -- i

      enable <= '0';

      for i in 0 to 15 loop
        din <= '0';

        wait until clk = '1';

        assert reg_value(0) = Dout report "Incorrect output, en = 0" severity error;

        reg_value <= nextCRC16_D1( '0', reg_value );


      end loop;  -- i


    end if;
  end process;


end crc_gen_beh_tb;