This is a VHDL description of the 74xx297, a full digital PLL.
It is fully synthesisable. A few things were modified from the original
design to comply to FPGA design rules.
- fully synchonous design
- K counter and ID counter use the same clock
- minor changes to match FPGA design style
It was tested on a Spartan-II FPGA from Xilinx with system clock frequencies up to 150 MHz.
VHDL for standard version.
VHDL for jitter reduced version.
Application note from Texas Instruments
Datasheet from Texas Instruments