library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity power is
    Port ( clk_in  : in std_logic;                      -- clock input
           sel     : in std_logic_vector(1 downto 0);   -- select modulation ON/OFF
           gnd     : out std_logic_vector(5 downto 0);  -- artificial gnd
           mod_out : out std_logic;                     -- modulation signal
           reset   : in std_logic;                      -- reset for DLL
           dummy   : out std_logic);                    -- dummy out, to fool the synthesizer
           
end power;

architecture Behavioral of power is

COMPONENT row
    PORT(
        clk  : IN std_logic;
        data : IN std_logic;    
        dout : OUT std_logic
        );
END COMPONENT;

-- DLL (Delay Locked Loop), a Virtex primiitive

component CLKDLL
    port (  
        CLKIN   : in    std_logic;
        CLKFB   : in    std_logic;
        RST     : in    std_logic;
        CLK0    : out   std_logic;
        CLK90   : out   std_logic;
        CLK180  : out   std_logic;
        CLK270  : out   std_logic;
        CLK2X   : out   std_logic;
        CLKDV   : out   std_logic;
        LOCKED  : out   std_logic);
end component;

-- BUFG (Global Clock buffer), a Virtex  pprimitive

component BUFG
    port (  I   : in    std_logic;
            O   : out   std_logic);
end component;

-- IBUFG (Global Clock input buffer ), aa  Virtex primitive

component IBUFG
    port (  I   : in    std_logic;
            O   : out   std_logic);
end component;

component SRL16     -- virtex primitive
  port (
        D    : in std_logic;        
        CLK  : in std_logic;
        A0   : in std_logic;
        A1   : in std_logic;
        A2   : in std_logic;
        A3   : in std_logic;        
        Q    : out std_logic
       ); 
end component;

constant rows: integer:=30;

type flop_array is array (rows-1 downto 0) of std_logic_vector(49 downto 0);

signal toggle   : std_logic;                            -- a toggle flipflop
signal ff_ar    : flop_array;
signal drive_ar : std_logic_vector (rows-1 downto 0);   -- driver array for toggeling rows
signal dout_ar  : std_logic_vector (rows-1 downto 0);   -- driver array for toggeling rows
signal or_ar    : std_logic_vector (rows-1 downto 0);   -- driver array for toggeling rows
signal cnt      : std_logic_vector (15 downto 0);       -- modulation divider

signal CLKIN_w, RESET_w, CLK2X_dll, CLK2X_g, CLK4X_dll, CLK4X_g, CLK8X_dll, CLK8X_g: std_logic;
signal LOCKED2X, LOCKED2X_delay, RESET4X, RESET8X, LOCKED4X, LOCKED4X_delay, LOCKED8X : std_logic;

signal logic1,clk : std_logic;

signal clk2x,clk4x,clk8x, clkmux: std_logic;

begin

-- use two DLL to get 147 MHz

logic1<='1';

clkpad : IBUFG  port map (I=>CLK_IN, O=>CLKIN_w);


dll2x  : CLKDLL port map (CLKIN=>CLKIN_w,   CLKFB=>CLK2X_g, RST=>RESET,
                          CLK0=>open,   CLK90=>open, CLK180=>open, CLK270=>open,
                          CLK2X=>CLK2X_dll, CLKDV=>open, LOCKED=>LOCKED2X);

clk2xg : BUFG   port map (I=>CLK2X_dll,   O=>CLK2X_g);

rstsrl : SRL16  port map (D=>LOCKED2X, CLK=>CLK2X_g, Q=>LOCKED2X_delay,
                          A3=>logic1, A2=>logic1, A1=>logic1, A0=>logic1);

RESET4X <= not LOCKED2X_delay;

dll4x  : CLKDLL port map (CLKIN=>CLK2X_g,  CLKFB=>CLK4X_g, RST=>RESET4X,
                          CLK0=>open,   CLK90=>open, CLK180=>open, CLK270=>open,
                          CLK2X=>CLK4X_dll, CLKDV=>open, LOCKED=>LOCKED4X);


clk4xg : BUFG   port map (I=>CLK4X_dll,  O=>CLK4X_g);

clk<=clk4x_g;

-- the toggeling array

l_rows: for i in 0 to rows-1 generate
    Inst_row: row PORT MAP(
        clk  => clk,
        data => drive_ar(i),
        dout => dout_ar(i)
    );
  end generate;

-- combine all douts via a BIG or-gate

  process(dout_ar)
  variable tmp: std_logic;
  begin
    tmp:='0';
    l_or: for i in 0 to rows-1 loop
      tmp:=tmp or dout_ar(i);
    end loop;
    dummy<=tmp;
  end process;

-- prescaler

  process(clk)
  begin
    if clk='1' and clk'event then
      cnt<=cnt+1;
    end if;
  end process;

-- toggle fliplop and distribution

  process(clk)
  begin
    if clk='1' and clk'event then
      case sel is
        when "00"       => toggle <= '0';
        when "01"       => toggle <= '1';
        when "10"       => toggle <= not toggle;
        when "11"       => if cnt(15)='1' then toggle <= not toggle; else toggle<='0'; end if;
        when others     => null;
      end case;
      drive_ar<=(others=>toggle);
    end if;
  end process;

gnd<=(others=>'0');
mod_out<=cnt(15);

end Behavioral;

-----------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity row is
    Port ( clk  : in std_logic;
           data : in std_logic;
           dout : out std_logic);
end row;

architecture Behavioral of row is

signal my_array: std_logic_vector (49 downto 0);

begin

-- generate 50 FFs with clock enable

  process (clk)
  begin
    if clk='1' and clK'event then
      my_array<=(others=>data);     
    end if;
  end process;

-- combine all into a BIG OR

  process(my_array)
  variable tmp: std_logic;
  begin
    tmp:='0';
    l: for i in 0 to 49 loop
      tmp:=tmp or my_array(i);
    end loop;
    dout<=tmp;
  end process;

end Behavioral;