--The IEEE standard 1164 package, declares std_logic, rising_edge(), etc.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;


entity glitch is
    port (
        clk_in        : in  STD_LOGIC;
        bad_clk       : out std_logic;
        glitch_detect : out STD_LOGIC
    );
end glitch;

architecture glitch_arch of glitch is

component LUT2
  port (
    I0 : in std_logic;
    I1 : in std_logic;
    O  : out std_logic
  );
end component;

-- Attribute applied to instantiation 
attribute INIT : string; 
attribute INIT of L_XOR : label is "6"; 

signal S1, S2, S3, clk_bad, clk:    std_logic;

begin
  -- a demonstration of a decoder generating a glitch
  
  -- toggling FlipFlops
  
  process(clk_in)  
  begin
    if clk_in='1' and clk_in'event then
      s1<=not S1;       -- these two signals are always inverted to each other
      s2<=S1;
    end if;  
  end process;

-- this is a big NO-NO, because the decoder produces glitches
-- clk_bad<=s1 xor s2;

-- we use a LUT instanciation so we can easy place then using LOC constraints

L_XOR: LUT2
  port map(
    I0 => S1,
    I1 => S2,
    O  => clk_bad
  );
  
  process(clk_bad)
  begin
    if clk_bad='1' and clk_bad'event then
      s3<=not s3;       -- a toggle FF, which would never toggle if the decoder output was glitch free
    end if;
  end process;
 
  glitch_detect<=s3;
  bad_clk<=clk_bad;
    
end glitch_arch;