

block mac {
  port ce_2_sg: in "std_logic"  "" 
    attrs {
      "width" => 1
      "domain" => ""
      "rate_pair" => [
        1
        2
      ]
      "is_ce" => true
      "type" => "logic"
    }
  port clk_2_sg: in "std_logic"  "" 
    attrs {
      "width" => 1
      "domain" => ""
      "rate_pair" => [
        1
        2
      ]
      "is_clk" => true
      "type" => "logic"
    }
  port gateway_in: in "std_logic_vector(7 downto 0)"  "[7 : 0]" 
    attrs {
      "source_block" => "mac/Gateway In"
      "is_gateway_port" => true
      "width" => 8
      "type" => "Fix_8_6"
      "must_be_hdl_vector" => true
      "is_floating_block" => true
      "port_id" => "1"
      "simulink_name" => "mac/Gateway In"
      "bin_pt" => 6
      "timing_constraint" => "none"
      "period" => 2
    }
  port gateway_in1: in "std_logic_vector(7 downto 0)"  "[7 : 0]" 
    attrs {
      "source_block" => "mac/Gateway In1"
      "is_gateway_port" => true
      "width" => 8
      "type" => "Fix_8_6"
      "must_be_hdl_vector" => true
      "is_floating_block" => true
      "port_id" => "1"
      "simulink_name" => "mac/Gateway In1"
      "bin_pt" => 6
      "timing_constraint" => "none"
      "period" => 2
    }
  port gateway_out: out "std_logic_vector(15 downto 0)"  "[15 : 0]" 
    attrs {
      "source_block" => "mac/Gateway Out"
      "is_gateway_port" => true
      "width" => 16
      "type" => "Fix_16_12"
      "must_be_hdl_vector" => true
      "is_floating_block" => true
      "port_id" => "1"
      "simulink_name" => "mac/Gateway Out"
      "bin_pt" => 12
      "timing_constraint" => "none"
      "period" => 2
    }


  ce_2_sg <= .ce_2_sg
  clk_2_sg <= .clk_2_sg
  gateway_in <= .gateway_in
  gateway_in1 <= .gateway_in1
  accumulator.q <= gateway_out

  subblock accumulator mac_accumulator {
    b => mult1.p
    ce => .ce_2_sg
    clk => .clk_2_sg
    clr => '0' : 1'b0
    en => sl2v.dout
    rst => sl2v_0.dout
    q => accumulator.q
  }
  subblock counter mac_counter {
    ce => .ce_2_sg
    clk => .clk_2_sg
    clr => '0' : 1'b0
    en => sl2v_1.dout
    rst => sl2v_2.dout
    q => counter.q
  }
  subblock mult1 mac_mult1 {
    a => .gateway_in
    b => .gateway_in1
    ce => .ce_2_sg
    clk => .clk_2_sg
    clr => '0' : 1'b0
    core_ce => '0' : 1'b0
    core_clk => '0' : 1'b0
    core_clr => '0' : 1'b0
    en => sl2v_3.dout
    rst => sl2v_4.dout
    p => mult1.p
  }
  subblock relational1 xlrelational {
    a => counter.q
    b => zero1.dout
    ce => '0' : 1'b0
    clk => '0' : 1'b0
    clr => '0' : 1'b0
    en => sl2v_5.dout
    dout => relational1.dout
  }
  subblock sl2v xlsl2slv {
    din => '1' : 1'b1
    dout => sl2v.dout
  }
  subblock sl2v_0 xlsl2slv {
    din => v2sl.dout
    dout => sl2v_0.dout
  }
  subblock sl2v_1 xlsl2slv {
    din => '1' : 1'b1
    dout => sl2v_1.dout
  }
  subblock sl2v_2 xlsl2slv {
    din => '0' : 1'b0
    dout => sl2v_2.dout
  }
  subblock sl2v_3 xlsl2slv {
    din => '1' : 1'b1
    dout => sl2v_3.dout
  }
  subblock sl2v_4 xlsl2slv {
    din => '0' : 1'b0
    dout => sl2v_4.dout
  }
  subblock sl2v_5 xlsl2slv {
    din => '1' : 1'b1
    dout => sl2v_5.dout
  }
  subblock v2sl xlslv2sl {
    din => relational1.dout
    dout => v2sl.dout
  }
  subblock zero1 xlconstant {
    dout => zero1.dout
  }
}
  attrs {
    "simulink_name" => "mac"
    "is_top_level" => true
  }


block mac_accumulator {
  port b: in "std_logic_vector(b_width - 1 downto 0)"  "[15 : 0]" 
    attrs {
      "port_id" => "1"
      "bin_pt" => 12
      "must_be_hdl_vector" => true
      "type" => "Fix_16_12"
      "simulink_name" => "mac/Accumulator/b"
      "width" => 16
      "period" => 2
    }
  port ce: in "std_logic"  "" 
    attrs {
      "width" => 1
      "rate_pair" => [
        1
        2
      ]
      "is_ce" => true
      "type" => "logic"
    }
  port clk: in "std_logic"  "" 
    attrs {
      "width" => 1
      "rate_pair" => [
        1
        2
      ]
      "is_clk" => true
      "type" => "logic"
    }
  port clr: in "std_logic"  "" 
    attrs {
      "width" => 1
      "is_clr" => true
      "valid_bit_used" => false
      "rate_pair" => [
        1
        2
      ]
      "type" => "logic"
    }
  port en: in "std_logic_vector(en_width - 1 downto 0)"  "" 
    attrs {
      "valid_bit_used" => false
      "port_id" => "3"
      "simulink_name" => "mac/Accumulator/en"
      "period" => -1
      "width" => 1
      "dangling_value" => 1
      "bin_pt" => 0
      "must_be_hdl_vector" => true
      "type" => "UFix_1_0"
    }
  port rst: in "std_logic_vector(rst_width - 1 downto 0)"  "" 
    attrs {
      "port_id" => "2"
      "bin_pt" => 0
      "must_be_hdl_vector" => true
      "type" => "Bool"
      "simulink_name" => "mac/Accumulator/rst"
      "width" => 1
      "period" => 2
    }
  port q: out "std_logic_vector(q_width - 1 downto 0)"  "[15 : 0]" 
    attrs {
      "port_id" => "1"
      "bin_pt" => 12
      "must_be_hdl_vector" => true
      "type" => "Fix_16_12"
      "simulink_name" => "mac/Accumulator/q"
      "width" => 16
      "period" => 2
    }
}
  attrs {
    "is_floating_block" => false
    "needs_vhdl_wrapper" => false
    "simulink_name" => "mac/Accumulator"
    "generics" => [
      [
        "b_width"
        "integer"
        "16"
      ]
      [
        "b_arith"
        "integer"
        "xlSigned"
      ]
      [
        "b_bin_pt"
        "integer"
        "12"
      ]
      [
        "en_width"
        "integer"
        "1"
      ]
      [
        "en_arith"
        "integer"
        "xlUnsigned"
      ]
      [
        "en_bin_pt"
        "integer"
        "0"
      ]
      [
        "q_width"
        "integer"
        "16"
      ]
      [
        "q_arith"
        "integer"
        "xlSigned"
      ]
      [
        "q_bin_pt"
        "integer"
        "12"
      ]
      [
        "rst_width"
        "integer"
        "1"
      ]
      [
        "rst_arith"
        "integer"
        "xlUnsigned"
      ]
      [
        "rst_bin_pt"
        "integer"
        "0"
      ]
      [
        "core_name0"
        "string"
        "\"accumulator_virtex2_7_0_d2672eba15a96a68\""
      ]
      [
        "c_add_mode"
        "integer"
        "0"
      ]
      [
        "c_b_type"
        "integer"
        "0"
      ]
      [
        "c_b_width"
        "integer"
        "16"
      ]
      [
        "c_enable_rlocs"
        "integer"
        "1"
      ]
      [
        "c_has_bypass"
        "integer"
        "0"
      ]
      [
        "c_has_sclr"
        "integer"
        "1"
      ]
      [
        "c_high_bit"
        "integer"
        "15"
      ]
      [
        "c_out_width"
        "integer"
        "16"
      ]
      [
        "c_saturate"
        "integer"
        "0"
      ]
      [
        "c_scale"
        "integer"
        "0"
      ]
      [
        "latency"
        "integer"
        "1"
      ]
    ]
  }


block mac_counter {
  port ce: in "std_logic"  "" 
    attrs {
      "width" => 1
      "rate_pair" => [
        1
        2
      ]
      "is_ce" => true
      "type" => "logic"
    }
  port clk: in "std_logic"  "" 
    attrs {
      "width" => 1
      "rate_pair" => [
        1
        2
      ]
      "is_clk" => true
      "type" => "logic"
    }
  port clr: in "std_logic"  "" 
    attrs {
      "width" => 1
      "is_clr" => true
      "valid_bit_used" => false
      "rate_pair" => [
        1
        2
      ]
      "type" => "logic"
    }
  port en: in "std_logic_vector(en_width - 1 downto 0)"  "" 
    attrs {
      "valid_bit_used" => false
      "port_id" => "2"
      "simulink_name" => "mac/counter/en"
      "period" => -1
      "width" => 1
      "dangling_value" => 1
      "bin_pt" => 0
      "must_be_hdl_vector" => true
      "type" => "UFix_1_0"
    }
  port rst: in "std_logic_vector(rst_width - 1 downto 0)"  "" 
    attrs {
      "valid_bit_used" => false
      "port_id" => "1"
      "simulink_name" => "mac/counter/rst"
      "period" => -1
      "width" => 1
      "dangling_value" => 0
      "bin_pt" => 0
      "must_be_hdl_vector" => true
      "type" => "UFix_1_0"
    }
  port q: out "std_logic_vector(q_width - 1 downto 0)"  "[2 : 0]" 
    attrs {
      "port_id" => "1"
      "bin_pt" => 0
      "must_be_hdl_vector" => true
      "type" => "UFix_3_0"
      "simulink_name" => "mac/counter/q"
      "width" => 3
      "period" => 2
    }
}
  attrs {
    "is_floating_block" => false
    "needs_vhdl_wrapper" => false
    "simulink_name" => "mac/counter"
    "generics" => [
      [
        "en_width"
        "integer"
        "1"
      ]
      [
        "en_arith"
        "integer"
        "xlUnsigned"
      ]
      [
        "en_bin_pt"
        "integer"
        "0"
      ]
      [
        "q_width"
        "integer"
        "3"
      ]
      [
        "q_arith"
        "integer"
        "xlUnsigned"
      ]
      [
        "q_bin_pt"
        "integer"
        "0"
      ]
      [
        "rst_width"
        "integer"
        "1"
      ]
      [
        "rst_arith"
        "integer"
        "xlUnsigned"
      ]
      [
        "rst_bin_pt"
        "integer"
        "0"
      ]
      [
        "core_name0"
        "string"
        "\"binary_counter_virtex2_7_0_bdfbbc7b13847ea8\""
      ]
      [
        "c_count_mode"
        "integer"
        "0"
      ]
      [
        "c_enable_rlocs"
        "integer"
        "1"
      ]
      [
        "c_has_load"
        "integer"
        "0"
      ]
      [
        "c_has_up"
        "integer"
        "0"
      ]
      [
        "cnt_to_high"
        "integer"
        "0"
      ]
      [
        "cnt_to_low"
        "integer"
        "4"
      ]
      [
        "count_limited"
        "integer"
        "1"
      ]
      [
        "*c_ainit_val"
        "string"
        "\"000\""
      ]
      [
        "*c_count_by"
        "string"
        "\"001\""
      ]
      [
        "*c_sinit_val"
        "string"
        "\"000\""
      ]
    ]
  }


block mac_mult1 {
  port a: in "std_logic_vector(a_width - 1 downto 0)"  "[7 : 0]" 
    attrs {
      "port_id" => "1"
      "bin_pt" => 6
      "must_be_hdl_vector" => true
      "type" => "Fix_8_6"
      "simulink_name" => "mac/Mult1/a"
      "width" => 8
      "period" => 2
    }
  port b: in "std_logic_vector(b_width - 1 downto 0)"  "[7 : 0]" 
    attrs {
      "port_id" => "2"
      "bin_pt" => 6
      "must_be_hdl_vector" => true
      "type" => "Fix_8_6"
      "simulink_name" => "mac/Mult1/b"
      "width" => 8
      "period" => 2
    }
  port ce: in "std_logic"  "" 
    attrs {
      "width" => 1
      "rate_pair" => [
        1
        2
      ]
      "is_ce" => true
      "type" => "logic"
    }
  port clk: in "std_logic"  "" 
    attrs {
      "width" => 1
      "rate_pair" => [
        1
        2
      ]
      "is_clk" => true
      "type" => "logic"
    }
  port clr: in "std_logic"  "" 
    attrs {
      "width" => 1
      "is_clr" => true
      "valid_bit_used" => false
      "rate_pair" => [
        1
        2
      ]
      "type" => "logic"
    }
  port core_ce: in "std_logic"  "" 
    attrs {
      "width" => 1
      "valid_bit_used" => false
      "rate_pair" => [
        1
        1
      ]
      "is_ce" => true
      "type" => "logic"
    }
  port core_clk: in "std_logic"  "" 
    attrs {
      "width" => 1
      "valid_bit_used" => false
      "rate_pair" => [
        1
        1
      ]
      "is_clk" => true
      "type" => "logic"
    }
  port core_clr: in "std_logic"  "" 
    attrs {
      "width" => 1
      "is_clr" => true
      "valid_bit_used" => false
      "rate_pair" => [
        1
        1
      ]
      "type" => "logic"
    }
  port en: in "std_logic_vector(en_width - 1 downto 0)"  "" 
    attrs {
      "valid_bit_used" => false
      "port_id" => "4"
      "simulink_name" => "mac/Mult1/en"
      "period" => -1
      "width" => 1
      "dangling_value" => 1
      "bin_pt" => 0
      "must_be_hdl_vector" => true
      "type" => "UFix_1_0"
    }
  port rst: in "std_logic_vector(rst_width - 1 downto 0)"  "" 
    attrs {
      "valid_bit_used" => false
      "port_id" => "3"
      "simulink_name" => "mac/Mult1/rst"
      "period" => -1
      "width" => 1
      "dangling_value" => 0
      "bin_pt" => 0
      "must_be_hdl_vector" => true
      "type" => "UFix_1_0"
    }
  port p: out "std_logic_vector(p_width - 1 downto 0)"  "[15 : 0]" 
    attrs {
      "port_id" => "1"
      "bin_pt" => 12
      "must_be_hdl_vector" => true
      "type" => "Fix_16_12"
      "simulink_name" => "mac/Mult1/p"
      "width" => 16
      "period" => 2
    }
}
  attrs {
    "is_floating_block" => false
    "needs_vhdl_wrapper" => false
    "simulink_name" => "mac/Mult1"
    "generics" => [
      [
        "a_width"
        "integer"
        "8"
      ]
      [
        "a_arith"
        "integer"
        "xlSigned"
      ]
      [
        "a_bin_pt"
        "integer"
        "6"
      ]
      [
        "b_width"
        "integer"
        "8"
      ]
      [
        "b_arith"
        "integer"
        "xlSigned"
      ]
      [
        "b_bin_pt"
        "integer"
        "6"
      ]
      [
        "en_width"
        "integer"
        "1"
      ]
      [
        "en_arith"
        "integer"
        "xlUnsigned"
      ]
      [
        "en_bin_pt"
        "integer"
        "0"
      ]
      [
        "p_width"
        "integer"
        "16"
      ]
      [
        "p_arith"
        "integer"
        "xlSigned"
      ]
      [
        "p_bin_pt"
        "integer"
        "12"
      ]
      [
        "rst_width"
        "integer"
        "1"
      ]
      [
        "rst_arith"
        "integer"
        "xlUnsigned"
      ]
      [
        "rst_bin_pt"
        "integer"
        "0"
      ]
      [
        "core_name0"
        "string"
        "\"multiplier_virtex2_7_0_8b164aaa836b8553\""
      ]
      [
        "bram_addr_width"
        "integer"
        "4"
      ]
      [
        "c_a_type"
        "integer"
        "0"
      ]
      [
        "c_a_width"
        "integer"
        "8"
      ]
      [
        "c_b_type"
        "integer"
        "0"
      ]
      [
        "c_b_width"
        "integer"
        "8"
      ]
      [
        "c_baat"
        "integer"
        "8"
      ]
      [
        "c_enable_rlocs"
        "integer"
        "1"
      ]
      [
        "c_has_ce"
        "integer"
        "1"
      ]
      [
        "c_has_nd"
        "integer"
        "0"
      ]
      [
        "c_has_o"
        "integer"
        "1"
      ]
      [
        "c_has_q"
        "integer"
        "0"
      ]
      [
        "c_mult_type"
        "integer"
        "0"
      ]
      [
        "c_output_hold"
        "integer"
        "0"
      ]
      [
        "c_output_width"
        "integer"
        "16"
      ]
      [
        "c_pipelined"
        "integer"
        "1"
      ]
      [
        "c_reg_inputs"
        "integer"
        "0"
      ]
      [
        "c_type"
        "integer"
        "0"
      ]
      [
        "c_use_luts"
        "integer"
        "1"
      ]
      [
        "extra_registers"
        "integer"
        "0"
      ]
      [
        "latency"
        "integer"
        "2"
      ]
      [
        "multsign"
        "integer"
        "xlSigned"
      ]
      [
        "overflow"
        "integer"
        "xlWrap"
      ]
      [
        "oversample"
        "integer"
        "1"
      ]
      [
        "quantization"
        "integer"
        "xlTruncate"
      ]
    ]
  }


block xlrelational {
  port a: in "std_logic_vector(a_width - 1 downto 0)"  "[2 : 0]" 
    attrs {
      "port_id" => "1"
      "bin_pt" => 0
      "must_be_hdl_vector" => true
      "type" => "UFix_3_0"
      "simulink_name" => "mac/Relational1/a"
      "width" => 3
      "period" => 2
    }
  port b: in "std_logic_vector(b_width - 1 downto 0)"  "[2 : 0]" 
    attrs {
      "port_id" => "2"
      "bin_pt" => 0
      "must_be_hdl_vector" => true
      "type" => "UFix_3_0"
      "simulink_name" => "mac/Relational1/b"
      "width" => 3
      "period" => -1
    }
  port ce: in "std_logic"  "" 
    attrs {
      "width" => 1
      "valid_bit_used" => false
      "rate_pair" => [
        1
        2
      ]
      "is_ce" => true
      "type" => "logic"
    }
  port clk: in "std_logic"  "" 
    attrs {
      "width" => 1
      "valid_bit_used" => false
      "rate_pair" => [
        1
        2
      ]
      "is_clk" => true
      "type" => "logic"
    }
  port clr: in "std_logic"  "" 
    attrs {
      "width" => 1
      "is_clr" => true
      "valid_bit_used" => false
      "rate_pair" => [
        1
        2
      ]
      "type" => "logic"
    }
  port en: in "std_logic_vector(en_width - 1 downto 0)"  "" 
    attrs {
      "valid_bit_used" => false
      "port_id" => "3"
      "simulink_name" => "mac/Relational1/en"
      "period" => -1
      "width" => 1
      "dangling_value" => 1
      "bin_pt" => 0
      "must_be_hdl_vector" => true
      "type" => "UFix_1_0"
    }
  port dout: out "std_logic_vector(dout_width - 1 downto 0)"  "" 
    attrs {
      "port_id" => "1"
      "bin_pt" => 0
      "must_be_hdl_vector" => true
      "type" => "Bool"
      "simulink_name" => "mac/Relational1/dout"
      "width" => 1
      "period" => 2
    }
}
  attrs {
    "is_floating_block" => false
    "needs_vhdl_wrapper" => false
    "simulink_name" => "mac/Relational1"
    "generics" => [
      [
        "a_width"
        "integer"
        "3"
      ]
      [
        "a_arith"
        "integer"
        "xlUnsigned"
      ]
      [
        "a_bin_pt"
        "integer"
        "0"
      ]
      [
        "b_width"
        "integer"
        "3"
      ]
      [
        "b_arith"
        "integer"
        "xlUnsigned"
      ]
      [
        "b_bin_pt"
        "integer"
        "0"
      ]
      [
        "dout_width"
        "integer"
        "1"
      ]
      [
        "dout_arith"
        "integer"
        "xlUnsigned"
      ]
      [
        "dout_bin_pt"
        "integer"
        "0"
      ]
      [
        "en_width"
        "integer"
        "1"
      ]
      [
        "en_arith"
        "integer"
        "xlUnsigned"
      ]
      [
        "en_bin_pt"
        "integer"
        "0"
      ]
      [
        "full_arith"
        "integer"
        "xlUnsigned"
      ]
      [
        "full_bin_pt"
        "integer"
        "0"
      ]
      [
        "full_width"
        "integer"
        "4"
      ]
      [
        "latency"
        "integer"
        "0"
      ]
      [
        "operator_type"
        "integer"
        "0"
      ]
    ]
  }


block xlsl2slv {
  port din: in "std_logic"  "" 
    attrs {
      "width" => 1
      "type" => "logic"
      "period" => -1
    }
  port dout: out "std_logic_vector(dout_width - 1 downto 0)"  "" 
    attrs {
      "width" => 1
      "bin_pt" => 0
      "must_be_hdl_vector" => true
      "type" => "UFix_1_0"
      "period" => -1
    }
}
  attrs {
    "generics" => [
      [
        "dout_width"
        "integer"
        "1"
      ]
      [
        "dout_arith"
        "integer"
        "xlUnsigned"
      ]
      [
        "dout_bin_pt"
        "integer"
        "0"
      ]
    ]
  }


block xlslv2sl {
  port din: in "std_logic_vector(din_width - 1 downto 0)"  "" 
    attrs {
      "width" => 1
      "bin_pt" => 0
      "must_be_hdl_vector" => true
      "type" => "UFix_1_0"
      "period" => 2
    }
  port dout: out "std_logic"  "" 
    attrs {
      "width" => 1
      "type" => "logic"
      "period" => 2
    }
}
  attrs {
    "generics" => [
      [
        "din_width"
        "integer"
        "1"
      ]
      [
        "din_arith"
        "integer"
        "xlUnsigned"
      ]
      [
        "din_bin_pt"
        "integer"
        "0"
      ]
    ]
  }


block xlconstant {
  port dout: out "std_logic_vector(dout_width - 1 downto 0)"  "[2 : 0]" 
    attrs {
      "port_id" => "1"
      "bin_pt" => 0
      "must_be_hdl_vector" => true
      "type" => "UFix_3_0"
      "simulink_name" => "mac/Zero1/dout"
      "width" => 3
      "period" => -1
    }
}
  attrs {
    "is_floating_block" => false
    "needs_vhdl_wrapper" => false
    "simulink_name" => "mac/Zero1"
    "generics" => [
      [
        "dout_width"
        "integer"
        "3"
      ]
      [
        "dout_arith"
        "integer"
        "xlUnsigned"
      ]
      [
        "dout_bin_pt"
        "integer"
        "0"
      ]
      [
        "const_val"
        "bit_vector"
        "b\"100\""
      ]
    ]
  }

attrs {
  "part_family" => "Virtex2"
  "coregen_part_family" => "Virtex2"
  "design" => "mac"
  "device" => "xc2v1000-4fg456"
  "simulink_names" => {
    "mult1" => "mac/Mult1"
    "accumulator" => "mac/Accumulator"
    "counter" => "mac/counter"
    "zero1" => "mac/Zero1"
    "relational1" => "mac/Relational1"
  }
  "system_clock_period" => 10
  "verilog" => [  ]
  "sysgen" => "C:/MATLAB701/toolbox/xilinx/sysgen"
  "top_level" => "mac"
  "vhdl" => [  ]
  "config_script" => "T:/Juan2/netlist/temp/mac_config.m"
  "stop_time" => 20
  "target_dir" => "t:/juan2/netlist"
  "start_time" => 0
  "clk_iob_map" => [
    "Fixed"
  ]
  "use_strict_names" => false
  "version" => "6.3"
  "mdl_path" => "t:/juan2/mac.mdl"
  "matlab_perl_directory" => "C:/MATLAB701/sys/perl/win32/bin/"
  "synthesis_tool" => "XST"
  "clocks_gcd" => 0.5
  "ise_version" => "6.3i"
  "xilinx" => "C:/Xilinx63"
  "hdl_kind" => "vhdl"
  "design_file" => "t:\\juan2\\netlist\\temp/mac.vhd"
  "hdl_files" => [
    "conv_pkg.vhd"
    "synth_reg.vhd"
    "synth_reg_w_init.vhd"
    "xlclkprobe.vhd"
    "xlclockdriver.vhd"
    "xlclockgenerator.vhd"
    "xlsl2slv.vhd"
    "xlslv2sl.vhd"
    "xlslicer.vhd"
    "mac_accumulator.vhd"
    "xlconstant.vhd"
    "mac_counter.vhd"
    "mac_mult1.vhd"
    "xlrelational.vhd"
    "mac.vhd"
  ]
  "matlab_java_directory" => "C:/MATLAB701/sys/java/jre/win32/jre1.4.2_04/bin"
}
