/****************************************************************************/
/*                                   IC.H                                   */
/*                                                                          */
/*             DEFINITIONS FOR MBII INTERCONNECT SPACE OPERATIONS           */
/*                                                                          */
/*                  LAST UPDATE: March 21, 1991 [16:59:04]                  */
/****************************************************************************/

/****************************************************************************/
/* HEADER RECORD                                                            */
/****************************************************************************/

#define IC_VENDOR_ID_B0                     0x00
#define   IC_VENDOR_INTEL_B0                0x01
#define IC_VENDOR_ID_B1                     0x01
#define   IC_VENDOR_INTEL_B1                0x00
#define IC_BOARD_ID_B1                      0x02   /* ASCII */
#define IC_BOARD_ID_B2                      0x03   /* ASCII */ 
#define IC_BOARD_ID_B3                      0x04   /* ASCII */ 
#define IC_BOARD_ID_B4                      0x05   /* ASCII */ 
#define IC_BOARD_ID_B5                      0x06   /* ASCII */ 
#define IC_BOARD_ID_B6                      0x07   /* ASCII */ 
#define IC_BOARD_ID_B7                      0x08   /* ASCII */ 
#define IC_BOARD_ID_B8                      0x09   /* ASCII */ 
#define IC_BOARD_ID_B9                      0x0a   /* ASCII */ 
#define IC_BOARD_ID_B10                     0x0b   /* ASCII */ 
#define IC_REVISION_NO                      0x10   /* BCD */
#define IC_CLASS_ID                         0x11
#define   IC_CLASS_MASK                     0xf0
#define     IC_CLASS_CSM                    0x00
#define     IC_CLASS_MEMORY                 0x10
#define     IC_CLASS_PERIPHERAL             0x20
#define     IC_CLASS_GRAPHICS               0x30
#define     IC_CLASS_COMMUNICATIONS         0x40
#define     IC_CLASS_NETWORK                0x50
#define     IC_CLASS_ANALOG_IO              0x70
#define     IC_CLASS_8_BIT_PROCESSOR        0xd0
#define     IC_CLASS_16_BIT_PROCESSOR       0xe0
#define     IC_CLASS_32_BIT_PROCESSOR       0xf0
#define   IC_SUBCLASS_MASK                  0x0f
#define     IC_SUBCLASS_RAM                 0x00   /* MEMORY */
#define     IC_SUBCLASS_DP_RAM              0x01   /* MEMORY */
#define     IC_SUBCLASS_RAM_PARITY          0x02   /* MEMORY */
#define     IC_SUBCLASS_DP_RAM_PARITY       0x03   /* MEMORY */
#define     IC_SUBCLASS_RAM_ECC             0x04   /* MEMORY */
#define     IC_SUBCLASS_DP_RAM_ECC          0x05   /* MEMORY */
#define     IC_SUBCLASS_JEDEC               0x06   /* MEMORY */
#define     IC_SUBCLASS_BUBBLE              0x07   /* MEMORY */
#define     IC_SUBCLASS_NON_ROTATING        0x00   /* PERIPHERAL */
#define     IC_SUBCLASS_GENERAL_PURPOSE     0x01   /* PROCESSOR */
#define     IC_SUBCLASS_PERIPHERAL          0x02   /* PROCESSOR */
#define     IC_SUBCLASS_GRAPHICS            0x03   /* PROCESSOR */
#define     IC_SUBCLASS_COMMUNICATIONS      0x04   /* PROCESSOR */
#define     IC_SUBCLASS_NETWORK             0x05   /* PROCESSOR */
#define     IC_SUBCLASS_ANALOG_IO           0x07   /* PROCESSOR */
#define     IC_SUBCLASS_SPECIAL_PURPOSE     0x09   /* PROCESSOR */
#define IC_IC_TEMPLATE_FLAG                 0x12
#define   IC_STANDARD_IC_TEMPLATE           0x00
#define   IC_EXTENDED_IC_TEMPLATE           0x01
#define IC_RESET_STATUS                     0x15
#define IC_PROGRAM_TABLE_INDEX              0x16
#define IC_INTERRUPT_CONTROL                0x17
#define   IC_ENABLE_DIAGNOSTIC_INTERRUPT    0x01
#define   IC_ENABLE_DEBUGGER_INTERRUPT      0x02
#define   IC_ENABLE_SOFTWARE_INTERRUPT      0x04
#define   IC_ENABLE_POWER_FAIL_INTERRUPT    0x40
#define   IC_ENABLE_ERROR_INTERRUPT         0x80
#define IC_GENERAL_STATUS                   0x18
#define   IC_NO_ERRORS                      0x00
#define   IC_LOCAL_ERROR_MASK               0x03
#define     IC_LOCAL_VALUE_ERROR            0x01
#define     IC_LOCAL_READ_ONLY_ERROR        0x02
#define   IC_GLOBAL_ERROR_MASK              0x0c
#define     IC_GLOBAL_VALUE_ERROR           0x04
#define     IC_GLOBAL_READ_ONLY_ERROR       0x08
#define     IC_GLOBAL_PROTECTION_ERROR      0x0c
#define   IC_POWER_FAILURE                  0x40
#define   IC_GENERAL_ERROR                  0x80
#define IC_GENERAL_CONTROL                  0x19
#define   IC_DIAGNOSTIC_REQUEST             0x01
#define   IC_DEBUGGER_ENTRY                 0x02
#define   IC_SOFTWARE_INTERRUPT             0x04
#define   IC_LOCAL_RESET                    0x80
#define IC_BIST_SUPPORT_LEVEL               0x1a
#define   IC_BIST_SUPPORT_LEVEL_MASK        0x07
#define   IC_BIST_LOOPS_FOREVER             0x08
#define   IC_BIST_ENABLED                   0x10
#define   IC_BIST_POTENTIAL_MASTER          0x80
#define IC_BIST_DATA_IN                     0x1b
#define IC_BIST_DATA_OUT                    0x1c
#define IC_BIST_SLAVE_STATUS                0x1d
#define   IC_BIST_OUT_DATA_VALID            0x01
#define   IC_BIST_IN_DATA_ACCEPTED          0x02
#define   IC_BIST_RUNNING                   0x04
#define   IC_BIST_OUTPUT_PENDING            0x08
#define   IC_BIST_CHECKS_RUNNING            0x10
#define   IC_BIST_TIMED_OUT                 0x20
#define   IC_BIST_ABORTED                   0x40
#define   IC_BIST_FAILED                    0x80
#define IC_BIST_MASTER_STATUS               0x1e
#define   IC_BIST_IN_DATA_VALID             0x01
#define   IC_BIST_OUT_DATA_ACCEPTED         0x02
#define   IC_BIST_ATTENTION                 0x04
#define   IC_BIST_INPUT_PENDING             0x08
#define   IC_BIST_COMPLETE                  0x20
#define   IC_BIST_REMOTE_PACKET             0x80
#define IC_BIST_TEST_ID                     0x1f

/****************************************************************************/
/* LITERALS TO ASSIST IN ACCESSING COMMON FIELDS IN ALL OTHER RECORDS       */
/****************************************************************************/

#define IC_FIRST_RECORD_OFFSET              0x20

#define IC_RECORD_LENGTH_OFFSET             0x01
#define IC_RECORD_DATA_OFFSET               0x02

/****************************************************************************/
/* EXTENDED RECORD                                                          */
/****************************************************************************/

#define IC_EXTENDED_RECORD_TYPE             0x00

#define IC_EXTENDED_TYPE_B0_OFFSET          0x02
#define IC_EXTENDED_TYPE_B1_OFFSET          0x03
#define IC_EXTENDED_DATA_OFFSET             0x04

/****************************************************************************/
/* MEMORY RECORD                                                            */
/****************************************************************************/

#define IC_MEMORY_RECORD_TYPE               0x01

#define IC_MEMORY_SIZE_B0_OFFSET            0x02
#define IC_MEMORY_SIZE_B1_OFFSET            0x03
#define IC_MEMORY_CONTROL_OFFSET            0x04
#define   IC_ENABLE_MEMORY_REFRESH          0x01
#define   IC_WRITE_PROTECT_MEMORY           0x02
#define IC_MEMORY_STATUS_OFFSET             0x05
#define   IC_MEMORY_TYPE_MASK               0x0f
#define     IC_MEMORY_TYPE_UNKNOWN          0x00
#define     IC_MEMORY_DYNAMIC_RAM           0x01
#define     IC_MEMORY_STATIC_RAM            0x02
#define     IC_MEMORY_EPROM_OR_ROM          0x03
#define     IC_MEMORY_EEPROM                0x04
#define     IC_MEMORY_NON_VOLATILE_RAM      0x05
#define     IC_MEMORY_MULTIPLE_TYPES        0x0f
#define   IC_MEMORY_PRESERVES_CONTENTS      0x10
#define   IC_MEMORY_SUPPORTS_WRITING        0x20
#define   IC_MEMORY_WIDTH_MASK              0xc0
#define     IC_MEMORY_8_BITS_WIDE           0x00
#define     IC_MEMORY_16_BITS_WIDE          0x40
#define     IC_MEMORY_32_BITS_WIDE          0x80
#define     IC_MEMORY_64_BITS_WIDE          0xc0

/****************************************************************************/
/* PSB MEMORY RECORD (OFTEN REFERRED TO AS THE PSB BANK RECORD)             */
/****************************************************************************/

#define IC_PSB_MEMORY_RECORD_TYPE           0x02

#define IC_PSB_START_ADDR_B0_OFFSET         0x02
#define IC_PSB_START_ADDR_B1_OFFSET         0x03
#define IC_PSB_END_ADDR_B0_OFFSET           0x04
#define IC_PSB_END_ADDR_B1_OFFSET           0x05
#define IC_PSB_MEMORY_CONTROL_OFFSET        0x06
#define   IC_DISABLE_PSB_MEMORY_ACCESS      0x01
#define   IC_DISABLE_PSB_MEMORY_WRITING     0x02

/****************************************************************************/
/* LBX MEMORY RECORD                                                        */
/****************************************************************************/

#define IC_LBX_MEMORY_RECORD_TYPE           0x03

#define IC_LBX_START_ADDR_B0_OFFSET         0x02
#define IC_LBX_START_ADDR_B1_OFFSET         0x03
#define IC_LBX_END_ADDR_B0_OFFSET           0x04
#define IC_LBX_END_ADDR_B1_OFFSET           0x05
#define IC_LBX_CLOCK_FREQUENCY_OFFSET       0x06
#define IC_LBX_SLOT_ID_OFFSET               0x07
#define IC_LBX_MEMORY_CONTROL_OFFSET        0x08
#define   IC_DISABLE_LBX_MEMORY_ACCESS      0x01

/****************************************************************************/
/* MEMORY PARITY RECORD                                                     */
/****************************************************************************/

#define IC_MEMORY_PARITY_RECORD_TYPE        0x04

#define IC_PARITY_CONTROL_OFFSET            0x02
#define   IC_ENABLE_PARITY_DETECTION        0x01
#define   IC_ENABLE_PARITY_RAM              0x02
#define   IC_SET_PARITY_STATUS_EACH_CYCLE   0x04
#define   IC_FORCE_PARITY_ERRORS            0x08
#define   IC_PARITY_ERROR_ADDRESS_VALID     0x10
#define   IC_PARITY_ERROR_UNSERVICED        0x20
#define   IC_PARITY_ERROR_OVERFLOW          0x40
#define   IC_PARITY_ERROR_DETECTED          0x80
#define IC_PARITY_STATUS_OFFSET             0x03
#define IC_ERROR_BANK_NO_OFFSET             0x04
#define IC_ERROR_OFFSET_B0_OFFSET           0x05
#define IC_ERROR_OFFSET_B1_OFFSET           0x06
#define IC_ERROR_OFFSET_B2_OFFSET           0x07
#define IC_ERROR_OFFSET_B3_OFFSET           0x08

/****************************************************************************/
/* CACHE MEMORY RECORD                                                      */
/****************************************************************************/

#define IC_CACHE_MEMORY_RECORD_TYPE         0x05

#define IC_CACHE_SIZE_B0_OFFSET             0x02
#define IC_CACHE_SIZE_B1_OFFSET             0x03
#define IC_CACHE_ENTRY_SIZE_OFFSET          0x04
#define IC_CACHE_CONTROL_OFFSET             0x05
#define   IC_CACHE_OPERATION_MODE_MASK      0x03
#define     IC_CACHE_NORMAL_OPERATION       0x00
#define     IC_CACHE_HIT_ONLY_OPERATION     0x01
#define     IC_CACHE_MISS_ONLY_OPERATION    0x02

/****************************************************************************/
/* PSB CONTROL RECORD                                                       */
/****************************************************************************/

#define IC_PSB_CONTROL_RECORD_TYPE          0x06

#define IC_PSB_SLOT_ID_OFFSET               0x02
#define   IC_PSB_SLOT_ID_MASK               0xf8
#define IC_PSB_ARBITRATION_ID_OFFSET        0x03
#define   IC_PSB_ARBITRATION_ID_MASK        0xf8
#define IC_PSB_ERROR_OFFSET                 0x04
#define   IC_PSB_AGENT_ERROR_MASK           0x07
#define     IC_PSB_NO_AGENT_ERROR           0x00
#define     IC_PSB_WIDTH_ERROR              0x01
#define     IC_PSB_CONTINUATION_ERROR       0x02
#define     IC_PSB_TRANSFER_ERROR           0x03
#define     IC_PSB_CANNOT_RESPOND_ERROR     0x04
#define     IC_PSB_AGENT_DATA_ERROR         0x05
#define   IC_PSB_BUS_TIMEOUT                0x08
#define   IC_PSB_BUS_ERROR                  0x10
#define   IC_PSB_REFERENCE_ERROR            0x40
#define   IC_PSB_ERROR_OCCURRED             0x80
#define IC_PSB_CONTROL_STATUS_OFFSET        0x05
#define   IC_PSB_RESET_TYPE_MASK            0x03
#define     IC_PSB_RESET_COMPLETE           0x00
#define     IC_PSB_RESET_WARM               0x01
#define     IC_PSB_RESET_RECOVERY           0x02
#define     IC_PSB_RESET_COLD               0x03
#define   IC_PSB_RESET_NOT_COMPLETE         0x04
#define   IC_PSB_PREVIOUS_RESET_MASK        0x18
#define     IC_PSB_PREVIOUS_RESET_WARM      0x08
#define     IC_PSB_PREVIOUS_RESET_RECOVERY  0x10
#define     IC_PSB_PREVIOUS_RESET_COLD      0x18
#define   IC_PSB_HIGH_PRIORITY_REQUEST      0x80
#define IC_PSB_DIAGNOSTICS_OFFSET           0x06
#define   IC_PSB_DISABLE_BUS_ERROR          0x01
#define   IC_PSB_DISABLE_BUS_PARITY         0x02
#define   IC_PSB_DISABLE_BUS_REQUEST        0x04
#define   IC_PSB_ENABLE_MESSAGE_LOOPBACK    0x08

/****************************************************************************/
/* LBX PRIMARY (MASTER) RECORD                                              */
/****************************************************************************/

#define IC_LBX_PRIMARY_RECORD_TYPE          0x07

#define IC_LBXPM_START_ADDR_B0_OFFSET       0x02
#define IC_LBXPM_START_ADDR_B1_OFFSET       0x03
#define IC_LBXPM_END_ADDR_B0_OFFSET         0x04
#define IC_LBXPM_END_ADDR_B1_OFFSET         0x05
#define IC_LBXPM_CONTROL_OFFSET             0x06
#define   IC_LBXPM_ENABLE_BUS_MEMORY        0x40
#define   IC_LBXPM_ENABLE_BUS_CONTROL       0x80
#define IC_LBXPM_SLOT_ID_OFFSET             0x07
#define   IC_LBXPM_SLOT_ID_MASK             0xf8
#define IC_LBXPM_CLOCK_FREQUENCY_OFFSET     0x08

/****************************************************************************/
/* CSM RECORD                                                               */
/****************************************************************************/

#define IC_CSM_RECORD_TYPE                  0x08

#define IC_CSM_COMMAND_OFFSET               0x02
#define   IC_CSM_RESET_GENERATION_MASK      0x03
#define     IC_CSM_PERFORM_NO_RESET         0x00
#define     IC_CSM_PERFORM_COLD_RESET       0x01
#define     IC_CSM_PERFORM_WARM_RESET       0x02
#define     IC_CSM_PERFORM_RECOVERY_RESET   0x03
#define   IC_CSM_ENABLE_PSB_TIMEOUT         0x00
#define   IC_CSM_DISABLE_PSB_TIMEOUT        0x80

/****************************************************************************/
/* DATE/TIME RECORD                                                         */
/****************************************************************************/

#define IC_DATE_TIME_RECORD_TYPE            0x09

#define IC_DATE_TIME_COMMAND_OFFSET         0x02
#define   IC_DATE_TIME_COMMAND_MASK         0x07
#define     IC_RELEASE_DATE_TIME_RECORD     0x00
#define     IC_READ_DATE_AND_TIME           0x01
#define     IC_WRITE_TIME                   0x02
#define     IC_WRITE_DATE                   0x03
#define     IC_WRITE_DATE_AND_TIME          0x04
#define   IC_DATE_TIME_COMMAND_COMPLETE     0x40
#define   IC_DATE_TIME_RECORD_BUSY          0x80
#define IC_FRACTIONS_OF_SECOND_OFFSET       0x03   /* BCD */
#define IC_SECONDS_OFFSET                   0x04   /* BCD */
#define IC_MINUTES_OFFSET                   0x05   /* BCD */
#define IC_HOURS_OFFSET                     0x06   /* BCD */
#define IC_DAY_OF_MONTH_OFFSET              0x07   /* BCD */
#define IC_MONTH_OFFSET                     0x08   /* BCD */
#define IC_YEAR_B0_OFFSET                   0x09   /* BCD */
#define IC_YEAR_B1_OFFSET                   0x0a   /* BCD */
#define IC_DAY_OF_WEEK                      0x0b
#define   IC_DAY_OF_WEEK_NOT_SUPPORTED      0x00

/****************************************************************************/
/* RESERVED RECORD                                                          */
/****************************************************************************/

#define IC_RESERVED_RECORD_TYPE             0x0a

/****************************************************************************/
/* PROTECTION RECORD                                                        */
/****************************************************************************/

#define IC_PROTECTION_RECORD_TYPE           0x0b

#define IC_PROTECTION_LEVEL_OFFSET          0x02
#define   IC_PREVENT_WRITE_OPERATIONS       0x01

/****************************************************************************/
/* PSB WINDOW RECORD                                                        */
/****************************************************************************/

#define IC_PSB_WINDOW_RECORD_TYPE           0x0c

#define IC_PSB_WINDOW_ADDR_B0_OFFSET        0x02
#define IC_PSB_WINDOW_ADDR_B1_OFFSET        0x03
#define IC_PSB_WINDOW_CONTROL_OFFSET        0x04
#define   IC_ENABLE_PSB_WINDOW              0x01
#define IC_PSB_WINDOW_STATUS_OFFSET         0x05
#define   IC_PSB_WINDOW_SIZE_MASK           0x03
#define     IC_NO_PSB_WINDOW                0x00
#define     IC_64K_PSB_WINDOW               0x01
#define     IC_128K_PSB_WINDOW              0x02
#define     IC_256K_PSB_WINDOW              0x03

/****************************************************************************/
/* SERIAL COMMUNICATIONS RECORD                                             */
/****************************************************************************/

#define IC_SERIAL_COMM_RECORD_TYPE          0x0d

#define IC_SERIAL_DATA_IN_OFFSET            0x02
#define IC_SERIAL_DATA_OUT_OFFSET           0x03
#define IC_SERIAL_STATUS_OFFSET             0x04
#define   IC_TRANSMIT_BUFFER_EMPTY          0x01
#define   IC_RECEIVE_BUFFER_FULL            0x02
#define   IC_RECEIVER_OVERFLOW              0x04
#define IC_SERIAL_INTERRUPT_MASK_OFFSET     0x05
#define   IC_DISABLE_ALL_SERIAL_INTS        0x00
#define   IC_DISABLE_SERIAL_TRANSMIT_INT    0x00
#define   IC_ENABLE_SERIAL_TRANSMIT_INT     0x01
#define   IC_DISABLE_SERIAL_RECEIVE_INT     0x00
#define   IC_ENABLE_SERIAL_RECEIVE_INT      0x02
#define   IC_DISABLE_SERIAL_OVERFLOW_INT    0x00
#define   IC_ENABLE_SERIAL_OVERFLOW_INT     0x04
#define IC_SERIAL_OPTIONS_OFFSET            0x06
#define   IC_BAUD_RATE_MASK                 0x07
#define     IC_300_BAUD                     0x00
#define     IC_600_BAUD                     0x01
#define     IC_1200_BAUD                    0x02
#define     IC_2400_BAUD                    0x03
#define     IC_4800_BAUD                    0x04
#define     IC_9600_BAUD                    0x05
#define     IC_19200_BAUD                   0x06
#define   IC_DISABLE_RECEIVER               0x00
#define   IC_ENABLE_RECEIVER                0x80

/****************************************************************************/
/* PERIPHERAL COMMUNICATIONS RECORD (FOR COMMUNICATIONS VIA DUAL-PORT)      */
/****************************************************************************/

#define IC_PERIPHERAL_COMM_RECORD_TYPE      0x0e

#define IC_MESSAGE_ID_OFFSET                0x02
#define IC_QUEUE_ADDR_B0_OFFSET             0x03
#define IC_QUEUE_ADDR_B1_OFFSET             0x04
#define IC_QUEUE_ADDR_B2_OFFSET             0x05
#define IC_QUEUE_ADDR_B3_OFFSET             0x06

/****************************************************************************/
/* FIRMWARE COMMUNICATIONS RECORD                                           */
/****************************************************************************/

#define IC_FIRMWARE_COMM_RECORD_TYPE        0x0f

#define IC_FIRMWARE_COMM_B1_OFFSET          0x02
#define IC_FIRMWARE_COMM_B2_OFFSET          0x03
#define IC_FIRMWARE_COMM_B3_OFFSET          0x04
#define IC_FIRMWARE_COMM_B4_OFFSET          0x05
#define IC_FIRMWARE_COMM_B5_OFFSET          0x06
#define IC_FIRMWARE_COMM_B6_OFFSET          0x07
#define IC_FIRMWARE_COMM_B7_OFFSET          0x08
#define IC_FIRMWARE_COMM_B8_OFFSET          0x09
#define IC_FIRMWARE_COMM_B9_OFFSET          0x0a
#define IC_FIRMWARE_COMM_B10_OFFSET         0x0b
#define IC_FIRMWARE_COMM_B11_OFFSET         0x0c
#define IC_FIRMWARE_COMM_B12_OFFSET         0x0d
#define IC_FIRMWARE_COMM_B13_OFFSET         0x0e
#define IC_FIRMWARE_COMM_B14_OFFSET         0x0f
#define IC_FIRMWARE_COMM_B15_OFFSET         0x10
#define IC_FIRMWARE_COMM_B16_OFFSET         0x11

/****************************************************************************/
/* HOST ID RECORD                                                           */
/****************************************************************************/

#define IC_HOST_ID_RECORD_TYPE              0x10

#define IC_HOST_ID_B0_OFFSET                0x02
#define IC_HOST_ID_B1_OFFSET                0x03
#define IC_AGENT_MESSAGE_ID_OFFSET          0x04

/****************************************************************************/
/* LOCAL MEMORY RECORD                                                      */
/****************************************************************************/

#define IC_LOCAL_MEMORY_RECORD_TYPE         0x11

#define IC_LOCAL_START_ADDR_B0_OFFSET       0x02
#define IC_LOCAL_START_ADDR_B1_OFFSET       0x03
#define IC_LOCAL_END_ADDRESS_B0_OFFSET      0x04
#define IC_LOCAL_END_ADDRESS_B1_OFFSET      0x05
#define IC_LOCAL_MEMORY_CONTROL_OFFSET      0x06
#define   IC_DISABLE_LOCAL_MEMORY           0x01
#define   IC_DISABLE_LOCAL_MEMORY_WRITES    0x02

/****************************************************************************/
/* CPU PROTECTION RECORD                                                    */
/****************************************************************************/

#define IC_CPU_PROTECTION_RECORD_TYPE       0x12

#define IC_EXTENDED_ADDRESS_OFFSET          0x02
#define   IC_EXTENDED_ADDRESS_ENABLED       0x01

/****************************************************************************/
/* LOCAL PROCESSOR (CPU) RECORD                                             */
/****************************************************************************/

#define IC_LOCAL_CPU_RECORD_TYPE            0x13

#define IC_LOCAL_CPU_CONTROL_OFFSET         0x02
#define   IC_RESET_LOCAL_CPU                0x01
#define IC_LOCAL_CPU_STATUS_OFFSET          0x03
#define   IC_LAST_RESET_TYPE_MASK           0x01
#define     IC_LAST_RESET_WAS_LOCAL_CPU     0x01
#define     IC_LAST_RESET_WAS_GLOBAL        0x00

/****************************************************************************/
/* HARDWARE EXTENSION RECORD                                                */
/****************************************************************************/

#define IC_HW_EXT_RECORD_TYPE               0x14

#define IC_HW_EXT_TYPE_B0_OFFSET            0x02
#define   IC_CSM_HW_EXT_B0                  0x00
#define IC_HW_EXT_TYPE_B1_OFFSET            0x03
#define   IC_CSM_HW_EXT_B1                  0x00
#define IC_HW_EXT_VENDOR_ID_B0_OFFSET       0x04
#define IC_HW_EXT_VENDOR_ID_B1_OFFSET       0x05
#define IC_HW_EXT_ID_B1_OFFSET              0x06   /* ASCII */
#define IC_HW_EXT_ID_B2_OFFSET              0x07   /* ASCII */ 
#define IC_HW_EXT_ID_B3_OFFSET              0x08   /* ASCII */ 
#define IC_HW_EXT_ID_B4_OFFSET              0x09   /* ASCII */ 
#define IC_HW_EXT_ID_B5_OFFSET              0x0a   /* ASCII */ 
#define IC_HW_EXT_ID_B6_OFFSET              0x0b   /* ASCII */ 
#define IC_HW_EXT_ID_B7_OFFSET              0x0c   /* ASCII */ 
#define IC_HW_EXT_ID_B8_OFFSET              0x0d   /* ASCII */ 
#define IC_HW_EXT_ID_B9_OFFSET              0x0e   /* ASCII */ 
#define IC_HW_EXT_ID_B10_OFFSET             0x0f   /* ASCII */ 
#define IC_HW_EXT_REVISION_NO_OFFSET        0x10   /* BCD */
#define IC_HE_EXT_RECORD_COUNT_OFFSET       0x11

/****************************************************************************/
/* ALARM RECORD                                                             */
/****************************************************************************/

#define IC_ALARM_RECORD_TYPE                0x20

#define IC_ALARM_COMMAND_OFFSET             0x02
#define IC_ALARM_SECONDS_OFFSET             0x03
#define IC_ALARM_MINUTES_OFFSET             0x04
#define IC_ALARM_HOURS_OFFSET               0x05
#define IC_ALARM_DAY_OF_WEEK_OFFSET         0x06
#define IC_ALARM_DAY_OF_MONTH_OFFSET        0x07
#define IC_ALARM_MONTH_OFFSET               0x08

/****************************************************************************/
/* NON-VOLATILE MEMORY RECORD                                               */
/****************************************************************************/

#define IC_NVRAM_RECORD_TYPE                0x21

#define IC_NVRAM_B1_OFFSET                  0x02
#define IC_NVRAM_B2_OFFSET                  0x03
#define IC_NVRAM_B3_OFFSET                  0x04
#define IC_NVRAM_B4_OFFSET                  0x05
#define IC_NVRAM_B5_OFFSET                  0x06
#define IC_NVRAM_B6_OFFSET                  0x07
#define IC_NVRAM_B7_OFFSET                  0x08
#define IC_NVRAM_B8_OFFSET                  0x09
#define IC_NVRAM_B9_OFFSET                  0x0a
#define IC_NVRAM_B10_OFFSET                 0x0b
#define IC_NVRAM_B11_OFFSET                 0x0c
#define IC_NVRAM_B12_OFFSET                 0x0d
#define IC_NVRAM_B13_OFFSET                 0x0e
#define IC_NVRAM_B14_OFFSET                 0x0f
#define IC_NVRAM_B15_OFFSET                 0x10
#define IC_NVRAM_B16_OFFSET                 0x11
#define IC_NVRAM_B17_OFFSET                 0x12
#define IC_NVRAM_B18_OFFSET                 0x13
#define IC_NVRAM_B19_OFFSET                 0x14
#define IC_NVRAM_B20_OFFSET                 0x15
#define IC_NVRAM_B21_OFFSET                 0x16
#define IC_NVRAM_B22_OFFSET                 0x17
#define IC_NVRAM_B23_OFFSET                 0x18
#define IC_NVRAM_B24_OFFSET                 0x19
#define IC_NVRAM_B25_OFFSET                 0x1a
#define IC_NVRAM_B26_OFFSET                 0x1b
#define IC_NVRAM_B27_OFFSET                 0x1c
#define IC_NVRAM_B28_OFFSET                 0x1d

/****************************************************************************/
/* CHASSIS ID RECORD                                                        */
/****************************************************************************/

#define IC_CHASSIS_RECORD_TYPE              0x22

#define IC_CHASSIS_ID_B0_OFFSET             0x02
#define IC_CHASSIS_ID_B1_OFFSET             0x03

/****************************************************************************/
/* BOARD-SPECIFIC FUNCTION RECORDS.                                         */
/****************************************************************************/

#define IC_FUNCTION_RECORD_TYPE_LOW         0xf0
#define IC_FUNCTION_RECORD_TYPE_HIGH        0xfe

/****************************************************************************/
/* EOT RECORD                                                               */
/****************************************************************************/

#define IC_EOT_RECORD_TYPE                  0xff

