* I am :

Currently an Alumni of

** My Whereabouts :

** A Little Bit About Me:

• Born: In Calcutta, the capital of the state of West Bengal in India on the 18th of November 1970.
• Grade School:  At St Mary's Orphanage & Day School, Dum Dum, Calcutta. Passed Indian Certificate of Secondary Education Exams - 1987.
• High School:   Calcutta Boys School, Moulali, Calcutta. Passed Indian School Certificate Exams - 1989.
• Undergraduate Education:  Indian Institute Technology, Kharagpur, majoring in Computer Science and Engineering - graduated 1993.
• Next:  Got a Master of Arts(surprisingly) degree for passing qualifiers/candidacy exams in the Department of Electrical Engineering, Princeton University - May, 1995.
• Then:  Obtained my Ph.D. from the above Department in April 1998.
• Finally:  Joined Fujitsu Labs. of America in Silicon Valley, California as a member of research staff.
• Finer details: In my Resume.

** My Better Half

** My Pride and Joy:

** My Family

** Research Interests:

• High level testing and diagnosis of VLSI circuits.
• High level verification of VLSI circuits.

** Publications:

Tutorial Presentations :

• ``High level design validation - current practices and future trends,'' (with M. Prasad, R. Mukherjee and M. Fujita), Full day tutorial in International Conference on VLSI Design, Mumbai, India, Jan. 2004

Journal Publications :

• ``VLSI implementation of an efficient ASIC architecture for real-time rotation of digital images,'' (with B. Majumdar), International Journal of Pattern Recognition and Artificial Intelligence, April 1995.
• ``Design for hierarchical testability of RTL circuits obtained by behavioral synthesis,'' (with A. Raghunathan and N.K. Jha), IEEE Transactions on CAD, Sept. 1997.
• ``A design for testability technique for RTL circuits using control/data flow extraction,'' (with A. Raghunathan and N.K. Jha), IEEE Transactions on CAD., Aug. 1998
• ``Controller re-synthesis for testability enhancements in RTL controller/data paths,'' (with S. Ravi, R. Roy and S. Dey), Journal of Electronic Testing: Theory and Applications (JETTA)., Oct. 1998
• ``High level test synthesis: A survey,'' (with N.K. Jha), Integration, the VLSI Journal, Dec. 1998
• ``Hierarchical test generation and design for testability for ASPPs and ASIPs,'' (with A. Raghunathan and N.K. Jha), IEEE Transactions on CAD., Mar. 1999
• ``A low overhead design for testability and test generation technique for core-based systems,'' (with N.K. Jha and S. Dey), IEEE Transactions on CAD., Nov. 1999
• ``A BIST scheme for RTL controller/data paths based on symbolic testability analysis,'' (with N.K. Jha and S. Bhawmik), IEEE Transactions on CAD., Jan. 2000
• ``A fast and low cost testing technique for core-based system chips,'' (with S. Dey and N.K. Jha), IEEE Transactions on CAD., Aug. 2000
• ``Automatic test pattern generation for functional RTL circuits using assignment decision diagrams,'' (with M. Fujita), IEEE Transactions on CAD, March 2001
• ``Fault-Diagnosis-Based technique for establishing RTL and gate-Level correspondences,'' (with S. Ravi, N.K. Jha and V. Boppana), IEEE Transactions on CAD., Dec. 2001

Conference Publications :

• ``Design of an application specific VLSI chip for image rotation,'' (with B. Majumdar), in Proc. International Conference on VLSI Design, Calcutta, India, Jan., 1994.
• ``Design for hierarchical testability of RTL circuits obtained by behavioral synthesis,'' (with A. Raghunathan and N.K. Jha), in Proc. IEEE International Conference on Computer Design, Austin, Texas, Oct. 1995.
• ``A design for testability technique for RTL circuits using control/data flow extraction,'' (with A. Raghunathan and N.K. Jha), in Proc. IEEE International Conference on Computer-Aided Design, San Jose, California, Nov. 1996.
• ``Speeding up flip-flop selection for partial scan,'' (with Sudipta Bhawmik), in Proc. International Conference on VLSI design, Hyderabad, India, Jan. 1997.
• ``Hierarchical test Generation and design for testability for ASPPs and ASIPs,'' (with A. Raghunathan and N.K. Jha), in Proc. IEEE/ACM Design Automation Conference, Anaheim, California, June 1997.
• ``A low overhead design for testability and test generation technique for core-based systems,'' (with N.K. Jha and S. Dey), in Proc. IEEE International Test Conference, Washington, D.C., Nov. 1997.
• ``Controller re-synthesis for testability enhancements in RTL controller/data paths,'' (with S. Ravi, R. Roy and S. Dey), in Proc. International Conference on VLSI Design, Chennai, India, Jan. 1998.
• ``A BIST scheme for RTL controller/data paths based on symbolic testability analysis,'' (with N.K. Jha and S. Bhawmik), in Proc. IEEE/ACM Design Automation Conference, San Francisco, California, June 1998.
• ``A fast and low cost testing technique for core-based system-on-a-chip,'' (with S. Dey and N.K. Jha), in Proc. IEEE/ACM Design Automation Conference, San Francisco, California, June 1998.
• ``Hierarchical diagnosis targeting RTL circuits,'' (with V. Boppana, R. Mukherjee, J. Jain, and M. Fujita), in Proc. International Conference on VLSI Design, Calcutta, India, Jan. 2000.
• ``Automatic test pattern generation for functional RTL circuits using assignment decision diagrams,'' (with M. Fujita), in Proc. IEEE/ACM Design Automation Conference, Los Angeles, California, June 2000.
• ``A technique for identifying RTL and gate-level correspondences,'' (with S. Ravi, V. Boppana and N.K. Jha), in Proc. IEEE International Conference on Computer Design, Austin, Texas, Sept. 2000.
• ``Design for verification at the register transfer level,'' (with K. Sekar and V. Boppana), in Proc. Asia and South Pacific Design Automation Conference, Bangalore, India, Jan. 2002.
• ``Event driven observability enhanced coverage analysis of C programs for functional validation,'' (with F. Fallah and M. Fujita), in Proc. Asia and South Pacific Design Automation Conference, Kitakyushu, Japan, Jan. 2003.
• ``On automatic generation of RTL validation test benches using circuit testing techniques,'' (with S. Ravi) in Great Lakes Symposium on VLSI, Washington D.C, April 2003
• ``Efficient sequential ATPG for functional RTL circuits,'' (with L. Zhang and M. Hsiao), in International Test Conference, Charlotte, North Carolina, Sept. 2003
• ``Precomputation-based guarding for dynamic and leakage power reduction,'' (with A. Abdollahi, F. Fallah, amd M. pedram), in Int. Conf. on Computer Design, San Jose, California, Oct. 2003
• ``Automatic Design Validation Framework for HDL Descriptions via RTL ATPG,'' (with L. Zhang and M. Hsiao), in Asian Test Symposium, Xian, China, Nov. 2003

Workshop Publications :

• ``A new design for testability and test generation technique for core-based systems,'' (with N.K. Jha and S. Dey), Fourth International Test Synthesis Workshop, Santa Barbara, California, May 1997.
• ``SOCET: System-on-chip testing method to trade off area overheads and testing time,'' (with S. Dey and N.K. Jha), Fifth International Test Synthesis Workshop, Santa Barbara, California, Mar. 1998.
• ``Automatic test bench generation for equivalence checking of C programs based on ATPG techniques,'' (with M. Fujita), Workshop on Software and Compilers for Embedded Systems, St. Goar, Germany, March 2001
• ``Observability enhanced coverage analysis of C programs for functional validation,'' with (F. Fallah), High Level Design Validation and Test Workshop, Monetery, California, Nov. 2001
• ``Observability-Based validation of C Programs,'' (with F. Fallah and M. Fujita), International Workshop on Microprocessor Test and Verification, Austin, Texas, June 2002 (invited talk)
• ``High-level automatic test generation for design validation,'' (with L. Zhang and M. Hsiao), Tenth International Test Synthesis Workshop, Santa Barbara, California, May 2003.