EDUCATION      :        M. S. in Electrical Engineering Department with a cumulative Grade
                                        Point average of 8.4/10 (3.36/4.0) from I. I. T. Madras.

Specialisation         :         DSP

                                       B. Tech. In ECE with 78% of marks from S. V. University, Tirupati, P.
SKILLS:

• Expertise in FPGA Design (Full cycle including simulation)
• Expertise in VHDL
• Expertise in System Level Simulation Tools like

• Expertise in Front End Synthesizing Tools like – Synopsys

• Expertise in ASIC Prototype Tool – Certify
• Expertise in Backend Tools like- Altera’s Maxplus and Quantus, Xilinx’s Foundation series
• Expertise in EDA simulation tools – Modelsim
• DSP Tool:- Worked with TI’s Code composure studio for TMS320C6202
• M. P: Worked with MPC 850 (knowledge of CPM) familiarity with Diab data compiler
• Domain knowledge of W-CDMA (3Gpp) wireless system Physical Layer

1. EMPLOYER                     :         Centre for development of Telematics (C-DOT) Bangalore

JOB TITLE                           :         Research Engineer

PERIOD                                 :         3^rd August 1998 till date

GROUP                                 :         W-CDMA group in C-DOT, Bangalore.

2. EMPLOYER                       :         I. I. T. - Madras

JOB TITLE                               :         Project Associate (Gr-I) in in DSP lab

PERIOD                                    :         Mar – 1998 to July - 1998

GROUP                                     :           Involved in the Defence Research and Development
                                                              Organization Project entitled "AMTD processor for RADAR Signal Processing"

PROJECT HANDLED:

Implementation of W-CDMA (3Gpp) Tx- Link

Description                                 :         I was involved in Design and implementation of Tx chain
                                                            (Chiprate) comprising of Spreading, Scrambling, Power Control, Digital QPSK
                                                            Modulator, for W-CDMA RTS

Duration                                     :         4 months

Team Size                                  :         2 people

Implemented in                          :          VHDL, fused in Flex 10K20RC208 device and tested

Implementation of Synchronization Channel for WCDMA (3Gpp) RTS

Description                               :         I was involved in Design and implementation of Primary and
                                                          Secondary Synchronizing Channels for W-CDMA RTS

Duration                                   :         1 month

Team Size                                 :         2 people

Implemented in                          :         VHDL, fused in Flex 10K20RC208 and tested

Implementation of RRC Filter for W-CDMA based RTS:

Description                                :         I was involved in Design and implementation of RRC Filter for
                                                           W-CDMA based RTS the filter has been simulated in Synopsys
                                                           COSSAP Tool.

Duration                                   :           2 months

Team Size                                 :          2 people

Implemented in                          :         VHDL, fused in Flex 10K20RC208 device and tested
 
 

Design and Implementation of Near End Loop Back Chain for W-CDMA based RTS testing:

Description                                 :         Near End Loop Back Chain containing blocks like Spread/Despread,
                                                            Scramble/Descramble, RRC Filter in Tx & Rx Chain and Tx Power Control.
                                                            This has been implemented to check the functionality of full Tx-Chain in W-CDMA
                                                            RTS for different data rates upto 2 Mbps channel rate.

Duration                                     :         2 months

Team Size                                  :         Taken full responsibility

Tools used                                 :         VHDL, and simulated upto place & route timings

Simulation of Rake-Receiver and SIC

Description                                :          I had simulated the Rake-Receiver and Serial Interference Cancellor (SIC) for
                                                            W-CDMA RTS. Entire uplink has been built for testing the same

Duration                                     :             6 months

Team Size                                   :             Taken full responsibility

Tools Used                                 :             HP’s Advanced Design System (ADS) (System Level Simulation Tool)

Simulation and Design of 256 Tap Matched Filter:

Description                                     :             Matched filter is required for the acquisition and Synchronization  purpose
                                                                    in W-CDMA RTS receiver

Duration                                         :             2 months

Team Size                                      :             Taken full responsibility

Tools Used                                    :             Simulation has been done using HP’s ADS

Implemented in                              :             VHDL and tested

Design of Baseband Card for RTS:

Description                                     :             I was involved in the Architecture Design of W-CDMA RTS and
                                                                   Baseband Processing Card which consists of CDMA Physical layer processing

Duration                                          :             1 month

Team Size                                        :             6 for Architecture Design of W-CDMA RTS
                                                                     3 for Basebend Card Design

Tools Used                                     :             Mentor Graphics tools for Schematic entry
                                                                    Place & route, CAD under progress

Design and implementation of RAKE Receiver for W-CDMA RTS:

Description                                      :             RAKE Receiver is used for the CDMA Multipath Reception

Duration                                          :             Under Progress

Team Size                                       :             Taken full responsibility

Tools Used                                     :             Altera’s Quartus/Synopsys FPGA Express, Modeltech’s modelsim
                                                                    Matlab for simulating channel estimation
                                                                    Symplicity’s synplify and certify

Device                                             :             Altera’s Apex 20 K 600 EFC – 672
                                                                      DSP Tools used: TI’s TMS 320 C6202 – Device and code composer
                                                                      studio for code entry and emulation.

Research Publications:

Refereed Journals:

• J. Giridhar and K. M. M. Prabhu, " Implementation Details of MTD-WVD on a TMS320C30 DSP Processor", Microprocessor & Microsystems Journals, Vol. 22, No.1, PP. 1-12, 1998.

• K. M. M. Prabhu and J. Giridhar, " The detection performance of MTD with WVD as a Doppler filter bank", European Signal Processing Journal (under review)

• J. Giridhar and K. M. M. Prabhu, " Doppler Resolution analysis of Radar returns using Choi-Williams Distribution", 13^th International conference in Digital Signal Processing held at Greece, July 2-4, 1997.

• J. Giridhar and K. M. M. Prabhu, "Doppler Resolution analysis using

• Holder of University 4^th Rank in B. Tech
• College Second in 10^th Std and Receiver of National Merit Scholarship for two years.

• Member of IETE Society
• Guided two M. tech students after joining in C-DOT.