entity decoder is
port(
	clk	: in bit;
	reset	: in bit;
	cin 	: in bit;
	opcode	: in bit_vector(2 downto 0);
	op1	: in bit_vector(3 downto 0);
	op2 	: in bit_vector(3 downto 0);
	aluout	: in bit_vector(3 downto 0);
	ramout	: in bit_vector(3 downto 0);
	s0	: out bit;
	s1	: out bit;
	s2	: out bit;
	rwn	: out bit;
	csn	: out bit;
	dcin	: out bit;
	aluin1	: out bit_vector(3 downto 0);
	aluin2	: out bit_vector(3 downto 0);
	addr	: out bit_vector(3 downto 0);
	ramin	: out bit_vector(3 downto 0)
);
end decoder;

architecture dec1 of decoder is
SIGNAL tstate,t1state : bit_vector(1 downto 0);
SIGNAL state : reg_vector(1 downto 0) register;

begin


with reset SELECT 
	tstate (1 downto 0) <= t1state(1 downto 0)    WHEN "1",
                       	 "11"        WHEN "0" ;

L0 : BLOCK (clk = '1' and not clk'STABLE)
   BEGIN
        state<= GUARDED tstate;
   END BLOCK; 
    
with state select
	t1state <= "01" when "00",
		"10" when "01",
		"00" when others;

with state select
	csn	<= "0" when "00",
		"0" when "10",
		"1" when others;

	
with state select
	rwn	 <= "1" when "00",
		"0" when others;
			
--with state select
--	ramin	 <=aluout  when "10",
--		"0000" when others;
--		 
--with state select
--	aluin	 <=ramout  when "01",
--		"0000" when others;

ramin <= aluout;
aluin1<= op2;
aluin2 <= ramout;
addr <=op1;

s2 <= opcode(2);
s1 <= opcode(1);
s0 <= opcode(0);
dcin <= cin;


end dec1;
