`include"genlib.h"
module and_or(w,p,bhairav,bus,car,deepu,synth_01,phani); 
input [5:0] bhirav; 
input [5:0] bus,car; 
output [3:0] vay; 
output [5:0] synth_01; 
output [5:0] phani; 
output naresh; 
input w,p,deepu; 
reg c; 
AND2 AND_0(synth_0[5] , bhairav[5] , bus[5]);
AND2 AND_1(synth_0[4] , bhairav[4] , bus[4]);
AND2 AND_2(synth_0[3] , bhairav[3] , bus[3]);
AND2 AND_3(synth_0[2] , bhairav[2] , bus[2]);
AND2 AND_4(synth_0[1] , bhairav[1] , bus[1]);
AND2 AND_5(synth_0[0] , bhairav[0] , bus[0]);
XNOR2 XNOR_0(phani[5] , synth_0[5] , car[5]);
XNOR2 XNOR_1(phani[4] , synth_0[4] , car[4]);
XNOR2 XNOR_2(phani[3] , synth_0[3] , car[3]);
XNOR2 XNOR_3(phani[2] , synth_0[2] , car[2]);
XNOR2 XNOR_4(phani[1] , synth_0[1] , car[1]);
XNOR2 XNOR_5(phani[0] , synth_0[0] , car[0]);
NOT NOT_0(naresh , deepu);
AND2 AND_6(vay[3] , bus[3] , car[3]);
AND2 AND_7(vay[2] , bus[2] , car[2]);
AND2 AND_8(vay[1] , bus[1] , car[1]);
AND2 AND_9(vay[0] , bus[0] , car[0]);
OR2 OR_0(synth_0[3] , vay[3] , bus[3]);
OR2 OR_1(synth_0[2] , vay[2] , bus[2]);
OR2 OR_2(synth_0[1] , vay[1] , bus[1]);
OR2 OR_3(synth_0[0] , vay[0] , bus[0]);
OR2 OR_4(alw_0[3] , synth_0[3] , den[3]);
OR2 OR_5(alw_0[2] , synth_0[2] , den[2]);
OR2 OR_6(alw_0[1] , synth_0[1] , den[1]);
OR2 OR_7(alw_0[0] , synth_0[0] , den[0]);
OR2 OR_8(synth_0[5] , bus[5] , car[5]);
OR2 OR_9(synth_0[4] , bus[4] , car[4]);
OR2 OR_10(synth_0[3] , bus[3] , car[3]);
OR2 OR_11(synth_0[2] , bus[2] , car[2]);
OR2 OR_12(synth_0[1] , bus[1] , car[1]);
OR2 OR_13(synth_0[0] , bus[0] , car[0]);
AND2 AND_10(synth_01[5] , synth_0[5] , alw[5]);
AND2 AND_11(synth_01[4] , synth_0[4] , alw[4]);
AND2 AND_12(synth_01[3] , synth_0[3] , alw[3]);
AND2 AND_13(synth_01[2] , synth_0[2] , alw[2]);
AND2 AND_14(synth_01[1] , synth_0[1] , alw[1]);
AND2 AND_15(synth_01[0] , synth_0[0] , alw[0]);

endmodule
