module and_or(w,p,bhairav,bus,car,deepu,synth_01,phani);
input [5:0] bhirav;
input [5:0] bus,car;
output [3:0] vay;
output [5:0] synth_01;
output [5:0] phani;
output naresh;
input w,p,deepu;
reg c;
assign phani=bhairav & bus ~^ car;
assign naresh=~deepu;

always @ (bus)
begin
vay=bus&car;
if  (vay|bus|den)
	synth_01 =bus|car;
end


endmodule
