//   This appendix describes the components used in the
// synthesized netlists shown in the text. Functionality
// of each component is specified using comments. 
 module AND2 (Z,A,B);
  input A, B;
  output Z;
  and (Z, A, B);  
endmodule 

module AOI21 ( Z,A1, A2, B);
  input A1, A2, B;
  output Z;
  wire X, Y;
  and (X, A1, A2);
  or (Y, X, B);
  not (Z, X); 
endmodule
 
module AOI211 (Z,A1, A2, B1, B2);
  input A1, A2, B1, B2;
  output Z;
  wire X, Y1, Y2;
  and (X, A1, A2);
  or (Y1, X, B1);
  or (Y2, Y1, B2);
  not (Z, Y2);
endmodule 

module AOI22 (Z,A1, A2, B1, B2);
  input A1, A2, B1, B2;
  output Z;
  wire X1, X2, X3;
  and (X1, A1, A2);
  and (X2, B1, B2);
  or (X3, X1, X2);
  not (Z, X3);
  // Z = ! ((A1&A2) | (B1&B2));
endmodule 

module BN20T20D (Z,PADO,A, ST, STN, PADI);
  input A, ST, STN, PADI;
  output Z, PADO;
  reg Z ,PADO;
  always @ (A or ST or STN or PADI)
  begin
  Z = PADI;
  if (!A && !STN)
  PADO = 0;
  else if (A && ST)
  PADO = 1;
  else
  PADO = 'bz;
  end 
  // Bidirectional buffer.
  // Z=PADI;
  // PADO = 0 when (!A && !STN) else
  //        1 when (A && ST) else
  //        'bz;
endmodule 

module BUF (Z,A);
  input A;
  output Z;
  assign Z = A; 
  // Z = A;
endmodule  

module FD1P3AX (Q,QN,D, SP, CK);
  input D, SP, CK;
  output Q, QN;
  reg Q,QN;
  always @ (posedge CK)
	begin
  Q <= D;
  QN <= SP;  
  end
  // Positive edge-triggered, positive-level sample,
  // static D-type FF.
endmodule 

module FD1S1A (D, CK, Q, QN);
  input D, CK;
  output Q, QN;

  // Positive-level sense static D-type FF(latch).
endmodule 

module FD1S1B (D, CK, CD, Q, QN);
  input D, CK, CD;
  output Q, QN;
  // Positive-level sense,positive asynchronous
  // preset, static D-type FF(latch).
endmodule 

module FD1S1D (D, CK, PD, Q, QN);
  input D, CK, PD;
  output Q, QN;
  // Positive-level sense,positive asynchronous
  // clear, static D-type FF(latch).
endmodule 

module FD1S1E (D, CK, CDN, Q, QN);
  input D, CK, CDN;
  output Q, QN;
  // Positive-level sense,negative asynchronous
  // clear, static D-type FF(latch).
endmodule 

module FD1S1F(D, CK, PD, CDN, Q, QN);
  input D, CK, PD, CDN;
  output Q, QN;
  // Positive-level sense,positive asynchronous clear
  // positive asynchronous preset
  // D-type FF(latch).
endmodule 

module FD1S2AX (D, CK, Q, QN);
  input D, CK;
  output Q, QN;
  // Negative edge-triggered,
  // static D-type FF(latch).
endmodule 

module FD1S2BX (D, CK, PD, Q, QN);
  input D, CK, PD;
  output Q, QN;
  // Negative edge-triggered,positive asynchronous
  // preset, static D-type FF(latch).
endmodule 

module FD1S2CX (D, CK, PD, Q, QN);
  input D, CK, PD;
  output Q, QN;
  // Negative edge-triggered,positive asynchronous
  // preset, positive asynchronous clear,
  // static D-type FF(latch).
endmodule 

module FD1S2DX (D, CK, CD, Q, QN);
  input D, CK, CD;
  output Q, QN;
  // Negative edge-triggered,positive asynchronous
  // clear, static D-type FF.
endmodule 

module FD1S2EX (D, CK, CDN, Q, QN);
  input D, CK, CDN;
  output Q, QN;
  // Negative edge-triggered,negative asynchronous
  // clear, static D-type FF.
endmodule 

module FD1S2FX (D, CK, PD, CDN, Q, QN);
  input D, CK, PD, CDN;
  output Q, QN;
  // Negative edge-triggered,negative asynchronous
  // clear,positive asynchronous preset,
  // static D-type FF.
endmodule 

module FD1S2GX (D, CK, PD, CDN, Q, QN);
  input D, CK, PD, CDN;
  output Q, QN;
  // Negative edge-triggered,negative asynchronous
  // preset, static D-type FF.
endmodule 

module FD1S2IX (D, CK, CD, Q, QN);
  input D, CK, CD;
  output Q, QN;
  // Negative edge-triggered,positive synchronous
  // clear, static D-type FF.
endmodule 

module FD1S2JX (D, CK, PD, Q, QN);
  input D, CK, PD;
  output Q, QN;
  // Negative edge-triggered,positive synchronous
  // preset, static D-type FF.
endmodule 

module FD1S2NX (D, CK, PDN, CD, Q, QN);
  input D, CK, PDN, CD;
  output Q, QN;
  // Negative edge-triggered,positive asynchronous
  // clear,negative asynchronous preset,
  // static D-type FF.
endmodule 

module FD1S2OX (D, CK, PD, CD, Q, QN);
  input D, CK, PD, CD;
  output Q, QN;
  // Negative edge-triggered,positive synchronous
  // clear,positive synchronous preset,
  // static D-type FF.
endmodule 

module FD1S3AX (D, CK, Q, QN);
  input D, CK;
  output Q, QN;
  // Positive edge-triggered,static D-type FF.
endmodule 

module FD1S3BX (D, CK, Q, QN);
  input D, CK;
  output Q, QN;
  // Positive edge-triggered,positive asynchronous
  // preset, static D-type FF.
endmodule 

module FD1S3CX (D, CK, Q, QN);
  input D, CK;
  output Q, QN;
  //Position adge-triggered,position asynchronous
  //clear,positive asynchronous preset,static
  //D-type FF.
endmodule 

module FD1S3EX(D, CK, CDN, Q, QN);
  input D, CK, CDN;
  output Q, QN;
  //Positive edge-triggered,negative synchronous
  //clear,static D-type FF.
endmodule 

module FL1S2AX(D0, D1, CK, SD, Q, QN);
  input D0, D1, CK, SD;
  output Q, QN;
  //Negative edge-triggered, data select front end,
  //scan FF.
endmodule 

module FL1S2EX(D0, D1, CK, SD, CDN, Q, QN);
  input D0, D1, CK, SD, CDN;
  output Q, QN;
  //Negative edge-triggered, data select front end,
  //negative asynchronous clear, scan FF.
endmodule 

module FL1S3AX(D0, D1, CK, SD, Q, QN);
  input D0, D1, CK, SD;
  output Q, QN;
  //Positive edge-triggered, data select front end,
  //scan FF.
endmodule 

module FL1S3CX(D0, D1, CK, SD, Q, QN);
  input D0, D1, CK, SD;
  output Q, QN;
  //Positive edge-triggered, data select front end,
  //positive asynchronous clear,positive asynchronous
  //preset, scan FF.
endmodule 

module FL1S3EX(D0, D1, CK, SD, CDN, Q, QN);
  input D0, D1, CK, SD, CDN;
  output Q, QN;
  //Positive edge-triggered, data select front end,
  //negative asynchronous clear, scan FF.
endmodule 

module FS0S1D(S, R, CD, Q, QN);
  input S, R, CD;
  output Q, QN;
  //Positive-level S input,positive-level R input,
  //positive asynchronous clear, R-S FF(latch).
endmodule 

module INRB (Z,A);
  input A;
  output Z;
  not (Z, A);
  //Z=!A;(same as INRB)
endmodule 

module ND2 (Z, A, B);
  input A, B;
  output Z;
wire X;
  and ( X, A, B);
  not (Z, X);
  //Z=!(A & B);
endmodule 

module ND3 (Z, A, B, C);
  input A, B, C;
  output Z;
  wire X, X1;
  and (X, A, B);
  and (X1, X, C);
  not (Z, X1);
  //Z=!(A & B & C);
endmodule 

module ND4 (Z, A, B, C, D);
  input A, B, C, D;
  output Z;
 wire X1, X2, X3;
  and (X1, A, B);
  and (X2, C, D);
  and (X3, X1, X2);
  not (Z, X3);
  //Z=!(A & B & C & D);
endmodule 

module NR2 (Z, A, B);
  input A, B;
  output Z;
  wire X;
  or (X, A, B);
  not (Z, X);
  //Z=!(A | B);
endmodule 

module NR3 (Z, A, B, C);
  input A, B, C;
  output Z;
  wire X1, X2;
  or (X1, A, B);
  or (X2, X1, C);
  not (Z, X2); 
  //Z=!(A | B | C);
endmodule 

module NR4 (Z, A, B, C, D);
  input A, B, C, D;
  output Z;
 wire X1, X2, X3;
  or (X1, A, B);
  or (X2, C, D);
  or (X3, X1, X2);
  not (Z, X3);
  //Z=!(A | B | C | D);
endmodule 

module OAI21 (Z, A1, A2, B);
  input A1, A2, B;
  output Z;
 wire X1, X2;
 or (X1, A1, A2);
 and (X2, X1, B);
 not (Z, X2);
  //Z=!((A1| A2) & B);
endmodule 

module OAI22 (Z, A1, A2, B1, B2);
  input A1, A2, B1, B2;
  output Z;
 wire X1, X2,X3;
  or (X1, A1, A2);
  or (X2, B1, B2);
  and (X3, X1, X2);
  not (Z, X3);
  //Z=!((A1| A2) & (B1 | B2));
endmodule 

module OAI4321 (Z, A1, A2, A3, A4, B1, B2, B3, C1, C2, D);
  input A1, A2, A3, A4, B1, B2, B3, C1, C2, D;
  output Z;
wire X1, X2, X3, Y1, Y2, Y3, C;
 or (X1, A1, A2);
 or (X2, A3, A4);
 or (x3, x1, x2);
 or (Y1, B1, B2);
 or (Y2, B3, B4);
 or (Y3, Y1, Y2);
 and (C, X3, Y3);
 not (Z, C);   
//Z=!((A1| A2 | A3 |A4) & (B1 | B2 | B3))
  //  & (C1 & C2) & D);
endmodule 

module OR2 (Z, A, B);
  input A, B;
  output Z;
 or (Z, A, B);
  //Z= A | B;
endmodule 

module OR4 (Z, A, B, C, D);
  input A, B, C, D;
  output Z;
 wire X1, X2;
 or (X1, A, B);
 or (X2, C, D);
 or (Z, X1, X2);
  //Z=A | B | C | D;
endmodule 

module TBUS (D, CK, CKN, Q);
  input D, CK, CKN;
  output Q;
  //Q= `bz when (! Ck && CKN),
  //   `b0 when (CK && ! D),
  //   `b1 when (! CKN && D);
endmodule 
module XNOR2 (Z, A, B);
  input A, B;
  output Z;
  xor (X1, A, B);
 not (Z, X1);
  //Z= | (A ^ B);
endmodule

 module XOR2 (Z, A, B);
  input A, B;
  output Z;
  xor (Z, A, B);
  //Z= A ^ B;
endmodule 

module XOR2Z (Z,Z1,A, B);
  input A, B;
  output Z, Z1;
 wire X1;
  xor (Z, A, B);
 or (X1, A, B);
 not (Z1, X1);
  //Z= A ^ B;Z1= !(A | B);
endmodule
