
	/*** 4-Bit processor ***/

module processor(opcode,op1,op2,clk,cin,reset,dout);

input clk,reset,cin;
input [2:0] opcode;
input [3:0] op1,op2;
output [3:0] dout;
wire [3:0] addr,rdata,adin1,adin2,adout;
wire csn,rwn,cout,s0,s1,s2;

//performs all the necessary wiring operations
 
decoder dec(.opcode(opcode),.op1(op1),.op2(op2),.clk(clk),.cin(cin),.reset(reset),.csn(csn),.rwn(rwn),.addr(addr),.rdata(rdata),.adin1(adin1),.adin2(adin2),.s0(s0),.s1(s1),.s2(s2),.adout(adout));

ram1 ra(.addr(addr),.data(rdata),.csn(csn),.rwn(rwn),.clk(clk),.reset(reset));

alu au(.reset(reset),.clk(clk),.s0(s0),.s1(s1),.s2(s2),.in1(adin1),.in2(adin2),.cin(cin),.f(adout),.cout(cout)); 

//gives output of the instruction  
assign  dout = rdata;

endmodule

