	/***  Synchronous Ram with Bidirectional Data  ***/

module ram1(addr,csn,rwn,data,clk,reset);

input [3:0] addr;
input csn,rwn,clk,reset;
inout [3:0] data;
reg [3:0] mem[15:0];
reg [3:0] dataout,datain,temp;

always @ (posedge clk)
begin
	if(csn==0) 	//Memory in use 
	begin
		 if(rwn==1)  // Read Memory
		 begin

//reading from memory

			dataout=mem[addr];
		 end
		 else
		 begin
//writing to memory
			 mem[addr]=data;
			 dataout=4'bzzzz;
		 end
	end
	else
	begin	
//memory not selected
		dataout=4'bzzzz;
	end
end

//interfacing with the tristate bus 

assign data = temp;
always @(csn | rwn |reset)
	if (~reset)
		temp=4'bzzzz;
	else
		if ((!csn) && rwn)
			temp = dataout;
		else
			temp = 4'bzzzz;   
endmodule


