//---------------------------------------------------
// Verilog stimulus code for a 4-bit processor
// Machine-generated : Don't edit
// Created with vsm-to-verilog converter v0.0,
// written in perl.
//---------------------------------------------------

`include "processor.v"

module stimulus;

reg [3:0] op1;
reg [3:0] op2;
reg [2:0] opcode;

reg clk;
reg reset;
reg next_inst;

Processor proc(.opcode(opcode),.op1(op1),.op2(op2),
			.clk(clk),.reset(reset), .next_inst(next_inst));

initial
begin
clk = 1'b0;
next_inst=1'b0;
reset = 1'b1;
forever #5 clk = ~clk;
end

initial
$dumpfile("proc.dmp");

initial
$dumpvars(3,stimulus);

initial
begin
#200;// STO instruction
#0 opcode = 3'b001;
op1 = 1;
op2 = 14;
next_inst = ~next_inst;

// STO instruction
#10 opcode = 3'b001;
op1 = 2;
op2 = 14;
next_inst = ~next_inst;

// STO instruction
#10 opcode = 3'b001;
op1 = 3;
op2 = 14;
next_inst = ~next_inst;

// STO instruction
#10 opcode = 3'b001;
op1 = 4;
op2 = 14;
next_inst = ~next_inst;

// STO instruction
#10 opcode = 3'b001;
op1 = 5;
op2 = 14;
next_inst = ~next_inst;

// STO instruction
#10 opcode = 3'b001;
op1 = 6;
op2 = 14;
next_inst = ~next_inst;

// ADD instruction
#10 opcode = 3'b010;
op1 = 6;
op2 = 6;
next_inst = ~next_inst;

// SUB instruction
#60 opcode = 3'b011;
op1 = 2;
op2 = 6;
next_inst = ~next_inst;

// XOR instruction
#60 opcode = 3'b110;
op1 = 3;
op2 = 6;
next_inst = ~next_inst;

// OR instruction
#60 opcode = 3'b101;
op1 = 4;
op2 = 6;
next_inst = ~next_inst;

// NOT instruction
#60 opcode = 3'b111;
op1 = 5;
op2 = 6;
next_inst = ~next_inst;

// ONEOP instruction
#60 opcode = 3'b000;
op1 = 0;
op2 = 5;
next_inst = ~next_inst;

// ONEOP instruction
#60 opcode = 3'b000;
op1 = 1;
op2 = 5;
next_inst = ~next_inst;

#100 stimulus.proc.ram.dumpmem;

#60 $finish;

end

endmodule
