
//--------------------------------------------------------
// We design a fast look-ahead carry adder.
// It has a delay equivalent of 3 gates whereas a ripple 
// carry adder for the same circuit will have more delay
// logic gates.(typically 12 gates,but depends upon the 
// implementation.	
//--------------------------------------------------------

module full_adder(cout,sum,in1,in2,cin);

output cout,sum;
input in1,in2,cin;

wire cout;
wire [3:0] sum;
wire [3:0] in1;
wire [3:0] in2;
wire cin;

// RTL description of the adder

wire c_temp1,c_temp2,c_temp3,c_temp4,c_temp5,c_temp6,c_temp7,c_temp8,c_temp9,c_temp10;

wire cg_0,cg_1,cg_2,cg_3;

wire cp_0,cp_1,cp_2,cp_3;

wire co_0,co_1,co_2;


half_adder HA_1(.sum(sum[0]),.p(in1[0]),.q(in2[0]),
							.carry(cin));

carry_gen_prop CGP_1(.cg_and(cg_0),.cp_or(cp_0),.p(in1[0]),
							.q(in2[0]));
and (c_temp1,cp_0,cin);
or (co_0,c_temp1,cg_0);

half_adder HA_2(.sum(sum[1]),.p(in1[1]),.q(in2[1]),
							.carry(co_0));

carry_gen_prop CGP_2(.cg_and(cg_1),.cp_or(cp_1),.p(in1[1]),
							.q(in2[1]));
and (c_temp2,cp_1,cg_0);
and (c_temp3,cp_1,cp_0,cin);
or (co_1,cg_1,c_temp2,c_temp3);

half_adder HA_3(.sum(sum[2]),.p(in1[2]),.q(in2[2]),
							.carry(co_1));

carry_gen_prop CGP_3(.cg_and(cg_2),.cp_or(cp_2),.p(in1[2]),
							.q(in2[2]));

and (c_temp4,cp_2,cg_1);
and (c_temp5,cp_2,cp_1,cg_0);
and (c_temp6,cp_2,cp_1,cp_0,cin);
or (co_2,cg_2,c_temp4,c_temp5,c_temp6);

half_adder HA_4(.sum(sum[3]),.p(in1[3]),.q(in2[3]),
							.carry(co_2));

carry_gen_prop CGP_4(.cg_and(cg_3),.cp_or(cp_3),.p(in1[3]),
							.q(in2[3]));


and (c_temp7,cp_3,cg_2);
and (c_temp8,cp_3,cp_2,cg_1);
and (c_temp9,cp_3,cp_2,cp_1,cg_0);
and (c_temp10,cp_3,cp_2,cp_1,cp_0,cin);
or (cout,cg_3,c_temp7,c_temp8,c_temp9,c_temp10);

endmodule

module half_adder(sum,p,q,carry);

output sum;
input p,q,carry;
wire sum;

wire temp;

my_xor xor1(.out(temp),.in1(p),.in2(q));
my_xor xor2(.out(sum),.in1(temp),.in2(carry));

endmodule

module carry_gen_prop(cg_and,cp_or,p,q);

input p,q;
output cg_and,cp_or;

and (cg_and,p,q);
or (cp_or,p,q);

endmodule

