`include "alu.v"

module top;

reg [3:0] a;
reg [3:0] b;
reg [2:0] ctrl_in;
reg carry_in;
reg clk;
reg reset;

wire [3:0] res;
integer i,j;

ALU alu(.clk(clk),.reset(reset),.cin(carry_in),.in1(a),
		.in2(b),.ctrl_in(ctrl_in),.f(res));

initial
begin
reset = 1'b1;
clk = 1'b0;
forever #1 clk = ~clk;
end

initial
$dumpfile("alu.dmp");

initial 
$dumpvars(0,top);

initial 
begin
#5;
j=$random(3);
for(i=0;i<20;i=i+1)
begin
	a = $random();
	b = $random();
	ctrl_in = $random();
	carry_in = $random();
	#10;
end
#400 $finish;
end


initial
$monitor($time," a=%b b=%b alu_cntl=%b cin=%b result=%b",a,b,ctrl_in,carry_in,res);

endmodule	
