`define TEST1 1
`define READ 1'b1
`define WRITE 1'b0
`define SEL 1'b0
`define DESEL 1'b1
`include "syncmem.v"

`ifdef TEST1
module ramstim;

wire [3:0] out;
reg [3:0] cnt;
wire [3:0] data;
reg [3:0] addr;
reg csn,clk,reset;

Syncram r (data, addr, csn, `WRITE,clk,reset);		// chip always in write mode

assign data = cnt;

initial
$dumpfile("ram.dmp");

initial 
$dumpvars(0,ramstim);

initial
begin
clk = 0;
forever #1 clk = ~clk;
end

initial 
begin
	reset = 1'b1;
	cnt = 4'b0110;
	addr = 4'b0000;
	#50 r.dumpmem;
	#0 $finish;
end

always
begin
	#2 csn = `DESEL;
	#2 cnt = cnt+1;
	addr = addr+1;
	csn = `SEL;
end

endmodule
`endif

`ifdef TEST2
module ramstim;

wire [3:0] out;
reg [3:0] in;
reg [3:0] addr;
reg rwn, csn;
ram r (out, addr, in, 1'b0, rwn);

reg[3:0] i;
integer j, k;

initial 
begin
	rwn = `WRITE;
	csn = `SEL;
	for (j=0; j<16; j=j+1)
	begin
		#1 addr = j;
		in = j;
	end

	#1000 r.dumpmem;
	$finish;
end

initial 
#16 begin							// CRUX : change this to 16 and see
	for (k=0; k <= 15; k=k+1)
	begin
		csn = `DESEL;
		#0 rwn = `READ;
		#0 addr = k-1;
		#10 csn = `SEL;
		#`MEMDELAY in = out;
		#1 csn = `DESEL;
		#0 rwn = `WRITE;
		#0 addr = k;
		#10 csn = `SEL;
	end
end

endmodule
`endif
