`include "decoder.v"
`include "alu.v"
`include "mem.v"
`include "syncmem.v"

`define SYNC_RAM

//----------------------------------------------------------
// The Processor Module
//	This merely connects the appropriate ports of the ALU,
//	Decoder and the memory unit.
//---------------------------------------------------------

module Processor(opcode,op1,op2,clk,reset, next_inst);

input opcode,op1,op2,reset,clk,next_inst;

wire [3:0] op1,op2;
wire [2:0] opcode;

wire [3:0] dataout,addr,datain,in1,in2,alu_out;
wire [3:0] databus;			
wire [2:0] ctrl_in;
wire csn,rwn,cin,cout, next_inst;

Instruction_Decoder decoder(.datain(datain),
				.dataout(dataout),.addr(addr),
				.chipsel(csn),
				.readwrite(rwn),
		
			.ctrl_in(ctrl_in),.in1(in1),.in2(in2),
			.cin(cin), .alu_out(alu_out),
		
			.clk(clk),.reset(reset),
			.op1(op1),.op2(op2),.opcode(opcode),.next_inst(next_inst));



`ifdef SYNC_RAM

// make the tristate connections
bufif1 bin0(databus[0], datain[0], ~rwn&~csn&reset);
bufif1 bin1(databus[1], datain[1], ~rwn&~csn&reset);
bufif1 bin2(databus[2], datain[2], ~rwn&~csn&reset);
bufif1 bin3(databus[3], datain[3], ~rwn&~csn&reset);

bufif1 bout0(dataout[0], databus[0], rwn&~csn&reset);
bufif1 bout1(dataout[1], databus[1], rwn&~csn&reset);
bufif1 bout2(dataout[2], databus[2], rwn&~csn&reset);
bufif1 bout3(dataout[3], databus[3], rwn&~csn&reset);
		
						
Syncram ram(.databus(databus), .addr(addr),.csn(csn), .rwn(rwn),
			.clk(clk),.reset(reset));

`else 

Ram ram(.dataout(dataout), .addr(addr), .datain(datain), 
		.csn(csn), .rwn(rwn));
`endif


ALU alu(.cout(cout),.f(alu_out),.ctrl_in(ctrl_in),.cin(cin),
		.in1(in1),.in2(in2),.clk(clk),.reset(reset));

endmodule
