SEMICONDUCTOR DEVICES

• Introduction
• Junction Diodes
• BJTs Bipolar Junction Transistors
• JFETsJunction Field Effect Transistors
• The .MODEL Card
• The Diode Model
• The BJT Model
• The JFET Model
• The MOSFET Model

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Semiconductor Devices:Introduction

The elements that have been described to this point typically require only a few parameter values to specify completely the electrical characteristics of the element. However, the models for the four semiconductor devices that are included in the SPICE program require many parameter values. Moreover, many devices in a circuit often are defined by the same set of device model parameters. For these reasons, a set of device model parameters is defined on a separate .MODEL card and assigned a unique model name. The device element cards in SPICE then reference the model name. This scheme alleviates the need to specify all of the model parameters on each device element card. Each device element card contains the device name, the nodes to which the device is connected, and the device model name. In addition, other optional parameters may be specified fo specified on the MOSFET device card.

Two different forms of initial conditions may be specified for devices. The first form is included to improve the dc con- vergence for circuits that contain more than one stable state. If a device is specified OFF, the dc operating point is deter- mined with the terminal voltages for that device set to zero. After convergence is obtained, the program continues to iterate to obtain the exact value for the terminal voltages. If a cir- cuit has more than one dc stable state, the OFF option can be used to force the solution to correspond to a desired state. If a device is specified OFF when in reality the device is conduct- ing, the program will still obtain the correct solution (assuming the solutions converge) but more iterations will be required since the program must independently converge to two separate solutions. The .NODESET card serves a similar purpose as the OFF option. The .NODESET option is easier to apply and is the pre- ferred means to aid convergence.

The second form of initial conditions are specified for use with the transient analysis. These are true 'initial conditions' as opposed to the convergence aids above. See the description of the .IC card and the .TRAN card for a detailed explanation of initial conditions.

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Junction Diodes

General form:

DXXXXXXX N+ N- MNAME < AREA > < OFF > < IC=VD >

Examples:

DBRIDGE 2 10 DIODE1
DCLMP 3 7 DMOD 3.0 IC=0.2

N+ and N- are the positive and negative nodes, respectively. MNAME is the model name, AREA is the area factor, and off indicates an (optional) starting condition on the device for dc analysis. If the area factor is omitted, a value of 1.0 is assumed. The (optional) initial condition specification using IC=VD is intended for use with the UIC option on the .TRAN card, when a transient analysis is desired starting from other than the quiescent operating point.

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Bipolar Junction Transistors (BJT's)

General form:

QXXXXXXX NC NB NE < NS > MNAME < AREA > < OFF > < IC=VBE,VCE >

Examples:

Q23 10 24 13 QMOD IC=0.6,5.0
Q50A 11 26 4 20 MOD1

NC, NB, and NE are the collector, base, and emitter nodes, respectively. NS is the (optional) substrate node. If unspeci- fied, ground is used. MNAME is the model name, AREA is the area factor, and OFF indicates an (optional) initial condition on the device for the dc analysis. If the area factor is omitted, a value of 1.0 is assumed. The (optional) initial condition specification using IC=VBE,VCE is intended for use with the UIC option on the .TRAN card, when a transient analysis is desired starting from other than the quiescent operating point. See the .IC card description for a better way to set transient initial conditions.

The BJT Model

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Junction Field-Effect Transistors (JFET's)

General form:

JXXXXXXX ND NG NS MNAME < AREA > < OFF > < IC=VDS,VGS >

Examples:

J1 7 2 3 JM1 OFF

ND, NG, and NS are the drain, gate, and source nodes, respectively. MNAME is the model name, AREA is the area factor, and OFF indicates an (optional) initial condition on the device for dc analysis. If the area factor is omitted, a value of 1.0 is assumed. The (optional) initial condition specification, using IC=VDS,VGS is intended for use with the UIC option on the .TRAN card, when a transient analysis is desired starting from other than the quiescent point.

PD=40U PS=40U
M1 2 9 3 0 MOD1 10U 5U 2P 2P

ND, NG, NS, and NB are the drain, gate, source, and bulk (sub- strate) nodes, respectively. MNAME is the model name. L and W are the channel length and width, in meters. AD and AS are the areas of the drain and source diffusions, in sq-meters. Note that the suffix U specifies microns (1E-6 m) and P sq-microns (1E-12 sq-m). If any of L, W, AD, or AS are not specified, default values are used. The user may specify the values to be used for these default parameters on the .OPTIONS card. The use of defaults simplifies input deck preparation, as well as the editing required if device geometries are to be changed. PD and PS are the perimeters of the drain and source junctions, in meters. NRD and NRS designate the equivalent number of squares of the drain and source diffusions; these values multiply the sheet resistance RSH specified on the .MODEL card for an accurate representation of the parasitic series drain and source resis- tance of each transistor. PD and PS default to 0.0 while NRD and NRS to 1.0. OFF indicates an (optional) initial condition on the device for dc analysis. The (optional) initial condition specif- ication using IC=VDS,VGS,VBS is intended for use with the UIC option on the .TRAN card, when a transient analysis is desired starting from other than the quiescent operating point. See the .IC card for a better and more convenient way to specify tran- sient initial conditions.

The JFET Model

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The .MODEL Card

General form:

.MODEL MNAME TYPE(PNAME1=PVAL1 PNAME2=PVAL2 ... )

Examples:

.MODEL MOD1 NPN BF=50 IS=1E-13 VBF=50

The .MODEL card specifies a set of model parameters that will be used by one or more devices. MNAME is the model name, and type is one of the following seven types:

NPN	NPN BJT Model
PNP	PNP BJT Model
D	Diode Model
NJF	N-channel JFET
PJF	P-channel JFET
NMOS	N-channel MOSFET
PMOS	P-channel MOSFET

Parameter values are defined by appending the parameter name, as given below for each model type, followed by an equal sign and the parameter value. Model parameters that are not given a value are assigned the default values given below for each model type.

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Diode Model

The dc characteristics of the diode are determined by the parameters IS and N. An ohmic resistance, RS, is included. Charge storage effects are modeled by a transit time, TT, and a nonlinear depletion layer capacitance which is determined by the parameters CJO, VJ, and M. The temperature dependence of the saturation current is defined by the parameters EG, the energy and XTI, the saturation current temperature exponent. Reverse breakdown is modeled by an exponential increase in the reverse diode current and is determined by the parameters BV and IBV (both of which are positive numbers).

NAME	PARAMETER
IS	Saturation Current
RS	Ohmic Resistance
N	Emission Coefficient
TT	Transit Time
CJO	Zero-bias Junction Capacitance
VJ	Junction Potential
M	Grading Coefficient
EG	Activation Energy (eV)
XTI	Saturation Current temp. exp
KF	Flicker Noise Coefficient
AF	Flicker Noise Exponent
FC	Coeff. for forward bias depletion capacitance formula
BV	Reverse Breakdown Voltage
IBV	Current at breakdown voltage

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BJT Models (both NPN and PNP)

The bipolar junction transistor model in SPICE is an adaptation of the integral charge control model of Gummel and Poon. This modified Gummel-Poon model extends the original model to include several effects at high bias levels. The model will automatically simplify to the simpler Ebers-Moll model when cer- tain parameters are not specified. The parameter names used in the modified Gummel-Poon model have been chosen to be more easily understood by the program user, and to reflect better both physi- cal and circuit design thinking.

The dc model is defined by the parameters IS, BF, NF, ISE, IKF, and NE which determine the forward current gain characteris- tics, IS, BR, NR, ISC, IKR, and NC which determine the reverse current gain characteristics, and VAF and VAR which determine the output conductance for forward and reverse regions. Three ohmic resistances RB, RC, and RE are included, where RB can be high current dependent. Base charge storage is modeled by forward and reverse transit times, TF and TR, the forward transit time TF being bias dependent if desired, and nonlinear depletion layer capacitances which are determined by CJE, VJE, and MJE for the B-E junction , CJC, VJC, and MJC for the B-C junction and CJS, VJS, and MJS for the C-S (Collector-Substrate) junction. The temperature dependence of the saturation current, IS, is deter- mined by the energy-gap, EG, and the saturation current tempera- ture exponent, XTI. Additionally base current temperature depen- dence is modeled by the beta temperature exponent XTB in the new model.

The BJT parameters used in the modified Gummel-Poon model are listed below. The parameter names used in earlier versions of SPICE2 are still accepted.

Modified Gummel-Poon BJT Parameters.

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JFET Models (both N and P Channel)

The JFET model is derived from the FET model of Shichman and Hodges. The dc characteristics are defined by the parameters VTO and BETA, which determine the variation of drain current with gate voltage, LAMBDA, which determines the output conductance, and IS, the saturation current of the two gate junctions. Two ohmic resistances, RD and RS, are included. Charge storage is modeled by nonlinear depletion layer capacitances for both gate junctions which vary as the -1/2 power of junction voltage and are defined by the parameters CGS, CGD, and PB.

name	parameter
VTO	threshold voltage
BETA	transconductance parameter
LAMBDA	channel length modulation parameter
RD	drain ohmic resistance
RS	source ohmic resistance
CGS	zero-bias G-S junction capacitance
CGD	zero-bias G-D junction capacitance
PB	gate junction potential
IS	gate junction saturation current
KF	flicker noise coefficient
AF	flicker noise exponent
FC	coefficient for forward-bias depletion capacitance formula

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MOSFET Models

SPICE provides three MOSFET device models which differ in the formulation of the I-V characteristic. The variable LEVEL specifies the model to be used:

LEVEL=1->Shichman-Hodges
LEVEL=2->MOS2
LEVEL=3->MOS3

Descriptions of these are available in:
A. Vladimirescu and S. Liu, "The Simulation of MOS Integrated Circuits Using SPICE2", ERL Memo No. ERL M80/7,Electronics Research Laboratory, University of California, Berkeley, Oct. 1980.

The dc characteristics of the MOSFET are defined by the device parameters VTO, KP, LAMBDA, PHI and GAMMA. These parameters are computed by SPICE if process parameters (NSUB, TOX, ...) are given, but user-specified values always override. VTO is posi- tive (negative) for enhancement mode and negative (positive) for depletion mode N-channel (P-channel) devices. Charge storage is modeled by three constant capacitors, CGSO, CGDO, and CGBO which represent overlap capacitances, by the nonlinear thin-oxide capa- citance which is distributed among the gate, source, drain, and bulk regions, and by the nonlinear depletion-layer capacitances for both substrate junctions divided into bottom and periphery, which vary as the MJ and MJSW power of junction voltage respec- tively, and are determined by the parameters CBD, CBS, CJ, CJSW, MJ, MJSW and PB. There are two built-in models of the charge storage effects associated with the thin-oxide. The default is the piecewise linear voltage-dependent capacitance model proposed by Meyer. The second choice is the charge-controlled capacitance model of Ward and Dutton [1]. The XQC model parameter acts as a flag and a coefficient at the same time. As the former it causes the program to use Meyer's model whenever larger than 0.5 or not specified, and the charge-controlled model when between 0 and 0.5. In the latter case its value defines the share of the chan- nel charge associated with the drain terminal in the saturation region. The thin-oxide charge storage effects are treated slightly different for the LEVEL=1 model. These voltage- dependent capacitances are included only if TOX is specified in the input description and they are represented using Meyer's for- mulation.

There is some overlap among the parameters describing the junctions, e.g. the reverse current can be input either as IS (in A) or as JS (in A/m**2). Whereas the first is an absolute value the second is multiplied by AD and AS to give the reverse current of the drain and source junctions respectively. This methodology has been chosen since there is no sense in relating always junc- tion characteristics with AD and AS entered on the device card; the areas can be defaulted. The same idea applies also to the zero-bias junction capacitances CBD and CBS (in F) on one hand, and CJ (in F/m**2) on the other. The parasitic drain and source series resistance can be expressed as either RD and RS (in ohms) or RSH (in ohms/sq.), the latter being multiplied by the number of squares NRD and NRS input on the device card.

name	parameter
LEVEL	model index
VTO	zero-bias threshold voltage
KP	transconductance parameter
GAMMA	bulk threshold parameter
PHI	surface potential
LAMBDA	channel-length modulation(MOS1&2 only)
RD	drain ohmic resistance
RS	source ohmic resistance
CBD	zero-bias B-D junction capacitance
CBS	zero-bias B-S junction capacitance
IS	bulk junction saturation current
PB	bulk junction potential
CGSO	gate-source overlap capacitance per meter channel width
CGDO	gate-drain overlap capacitance per meter channel width
CGBO	gate-bulk overlap capacitance per meter channel length
RSH	drain and source diffusion sheet resisitance
CJ	zero-bias bulk junction bottom cap. per sq-meter of junction area
MJ	bulk junction bottom grading coef.
SW	zero-bias bulk junction sidewall cap.		per meter of junction perimeter
MJSW	bulk junction sidewall grading coef.
JS	bulk junction saturation current		per sq-meter of junction area
TOX	oxide thickness
NSUB	substrate doping
NSS	surface state density
NFS	fast surface state density
TPG	type of gate material: +1 opp. to substrate -1 same as substrate
XJ	metallurgical junction depth
LD	lateral diffusion (in meters)
UO	surface mobility
UCRIT	critical field for mobility degradation (MOS2 only)(Volts/m)
UEXP	critical field exponent in mobility degradation (MOS2 only)
UTRA	transverse field coef (mobility)(deleted for MOS2)
VMAX	maximum drift velocity of carriers
NEFF	total channel charge (fixed and mobile) coefficient (MOS2 only)
XQC	thin-oxide capacitance model flag and coefficient of channel charge share attributed to drain (0-0.5)
KF	flicker noise coefficient
AF	flicker noise exponent
FC	coefficient for forward-bias depletion capacitance formula
DELTA	width effect on threshold voltage (MOS2 and MOS3)
THETA	mobility modulation (MOS3 only)
ETA	static feedback (MOS3 only)
KAPPA	saturation field factor (MOS3 only)

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