ObjectiveWe consider here a method to investigate the inexpensive high performance hardwired implementation of elementary functions. Our aim is to try to design an architecture to get more precision - this means to reduce the errors - for these functions. In the approach described in [Vassiliadis, Zhang and Delgado-Frias] the average error of the elementary functions is in the order of 1/1000 and the maximum error is in the order of 1/100. We feel that this precision can be increased.The general idea behind this objective is that once we can achieve a satisfactory level of precision and computing speed in a uniprocessor model we can readily extend it to a multiprocessor platform. Neural computing hardware is by its nature a parallel processing machine and so it can exploit the inherent parallelism of elementary functions. Computing performance would be greatly improved if we could do so.
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