Hitesh I Patel hitpatel256@yahoo.com OBJECTIVE: To seek a challenging job in VLSI Design field. Educational Qualifications: --------------------------- 1)P. G. Diploma In VLSI DESIGN at, BIT MAPPER INTEGRATION TECHNOLOGIES PVT. LTD. An ISO9001 certified training Institute based in PUNE. 2)B.E(Electronics from PUNE UNIVERSITY) Course Details: --------------- Subjects: Synthesis, Simulation, CMOS VLSI, Memory Modeling, VHDL,Verilog, Finite State machines, Static Timing Analysis. Tools Used: ----------- 1) Foundation Series v2.1 from Xilinx, it is a complete Package which supports, Which include FPGA express from Synopsys for synthesis Design entry in Schematic, VHDL, FSM. Design Synthesis. Simulation (both Functional and Timing). Implementation for Xilinx FPGAs and CPLDs. 2) Synplify release 5.3 with HDL Analyst, a Synthesis Tool from Synplicity Inc. 3) Model Sim plus II release 5.3, a Simulation Tool from Mentor Graphics. Seminar ------ 1)MEMS( MicroElectroMechanical Systems) Mini Projects ------------- 1. UART It was implemented, synthesized & verified using Xilinx Foundation Series. 2. FIFO (Synch/Asynch) It was implemented, synthesized & verified using Xilinx Foundation Series. 3. Floating Point Adder/Subtractor It was implemented, synthesized & verified using Xilinx Foundation Series. Project ------- 1)Implemented Digital Filter. An 16 Tab 8 bit FIR Filter was Implemented. ------------------------------------------------------------------------------ B.E. Electronics Institution : S.E.S College Of Engineering. Board/Univesity : Pune University. Percentage : 63.5%. Year : 2001. H.S.C. Institution : A.E.S College of Arts Commerce & Science. Board/Univesity : Mumbai Board Percentage : 60.5%. Year : 1997. S.S.C. Institution : Maharashtra English High School. Board/Univesity : Mumbai Board Percentage : 64.00% Year : 1995. Work Experience ---------------- Organisation Name : CD Consultancy & Services Designation : Design Engineer. Responsibilities : Designing Wireless secu