EE 176 VHDL 03/11/04 Lecture #6 Thursday

VHDL Operators

Last Week: VHDL Signals/data types

Today: The main VHDL operators for performing operators base on signals/data type.

q LOGIC OPERATORS

not (higher precedence)

---------------------------------------

and (equal precedence)

nand

nor

xor

To overcome precedence, use ()

Ex. Z<= a and not(b or c)

q Legal Type Operands and Results

o Predefined in package (STANDARDS)

Boolean

Bit

Bit_vector

o Extended by IEEE 1164 (in package std_logic_1164);

A

B

std_ulogic

?

Z

Z

std_logic

std_ulogic_vector

std_logic_vector

o Extended by IEEE 1176.3 (in package numeric_bit/_std );

Unsigned-TYPE unsigned IS ARRAY(natural range( ) of bit ;

Signed - TYPE signed IS ARRAY(natural range( ) of std_logic;

q NOTE (for logic operator)

1. Type of operands and results must match

2. For array operands

a. Sizes of operands and results must match

b. Operands are applied to matching elements by position

EX: :

SIGNAL a_bus, b_bus, z_bus:std_ulogic_vector( 3 downto 0);

Z_bus<=a_bus AND b_bus;

Equals

Z_bus(3) <=a_bus(3) AND b_bus(3);

Z_bus(2) <=a_bus(2) AND b_bus(2);

Z_bus(1) <=a_bus(1) AND b_bus(1);

Z_bus(0) <=a_bus(0) AND b_bus(0);

q Relational Operator

= Equal

/= Not Equal

< Less then

<= Less then and equal to

> Greater then

>= Greater then and equal to

q Legal operand and results

o Predefined in STANDARD package

o Extended by IEEE 1176.3 (in package numeric_bit/_std );

/= (Any Type)

-------------------------------

< (Any Scalar type: integer, Boolean, char, real, time, etc)

<= or

> 1-D array of integer/enumerated type (Boolean, bit, char, etc)

q NOTE

1. Usage of relational operators

a. Mostly in “if-else” statement

2. Array operands can be of different lengths and if so, the operands are aligned to the LEFT and compared to the right.

1011 ßà 111

111

3. Outputs are always in Boolean

4. In VHDL, vector signal DOES NOT have a numerical value.

q ARITHMATIC OPERATOR

o Extended by IEEE 1176.3 (in package numeric_bit/_std );

+ addition

- subtraction

* multiplication

/ division

** exponent

abs absolute value

rem remainder x= L rem R sign(x)=sign(L)

mod mod x= L rem R sign(x)=sign(R)

1. As in VHDL vectors do not require a numerical values, these operators CANNOT be used w/ types

BIT_VECTOR

STD_ULOGIC_VECTOR

STD_LOGIC_VECTOR

2. In general, operand and results needs to be in the same type.

EX: Exception

Integer * time

3. Range of results need to specified (be careful!)

EX: ENITY ADD IS

PORT(a, b:integer Range 0 to 7;

Z:out integer range 0 to 15);

ARCHITECTURE arithmetic ADD is

Z<=a+b;

END arithmetic;

q OTHER OPERATOR-SHIFT/ROTATE OPERATOR

o Not predefined in STANDARD PACKAGE

o Need to include package

SLL Shift Left Logic

SRL Shift Right Logic

SLA Shift Left Arithmetic

SRA Shift Right Arithmetic

ROL Rotate Left

ROR Rotate Right

q CONCEPT OF OVERLOADING

o VHDL allows multiple functions to be defined with the same name, but different in their input/output

Type x {

Type y {

o When apply overloading concept to operators, we can define multiple version for a specific operator (eg. “and”, “+”, etc) to deal with different types of operands/results

o Overloading done by IEEE 1176.3 (in package numeric_bit/_std );

(also called the IEEE synthesis Package)

o Example:

Let v={unsigned and signed} vector

S={integer, natural}

Opa={abs, +, -, * , /, mod, rem} (set of arithmetic operation)

Opr={=, /=, <, <=, >, >=} (relational)

V

V

OPA

V

S

V

OPA

OPA

V

V

V

OPR