TB_FSM

--=========================T_DUT_FSM_ANS1====================

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

ENTITY T_MEALY IS
END T_MEALY;

ARCHITECTURE behavior OF T_MEALY IS

COMPONENT fsm_ans1 PORT(
        DT: IN std_logic;
        RG: IN std_logic;
        EG: IN std_logic;
        EM: IN std_logic;
        CLK: IN std_logic;
        RST: IN std_logic;
        CN: OUT std_logic;
        PL: OUT std_logic;
        RD: OUT std_logic

);
END COMPONENT;

SIGNAL DT_tb : std_logic;
SIGNAL RG_tb : std_logic;
SIGNAL EG_tb : std_logic;
SIGNAL EM_tb : std_logic;
SIGNAL CN_tb : std_logic;
SIGNAL PL_tb : std_logic;
SIGNAL RD_tb : std_logic;
SIGNAL CLK_tb : std_logic;
SIGNAL RST_tb : std_logic;

BEGIN

uut: fsm_ans1 PORT MAP(
    DT => DT_tb,
    RG => RG_tb,
    EG => EG_tb,
    EM => EM_tb,
    CN => CN_tb,
    PL => PL_tb,
    RD => RD_tb,
    CLK => CLK_tb,
    RST => RST_tb
);

Clock : PROCESS
BEGIN
    CLK_tb <= '0';
    wait for 20 ns;
    CLK_tb <= '1';
    wait for 20 ns;
    IF (NOW > 1600 ns) then
        wait;
    end if;
end process;

-- *** Test Bench - User Defined Section ***
tb : PROCESS
BEGIN
    RST_tb <= '1';
    wait for 50 ns;

    RST_tb <= '0';

    DT_tb <= '0';
    RG_tb <= '0';
    EG_tb <= '0';
    EM_tb <= '0';
    wait for 50 ns;


    DT_tb <= '0';
    RG_tb <= '0';
    EG_tb <= '0';
    EM_tb <= '1';
    wait for 50 ns;


    DT_tb <= '0';
    RG_tb <= '0';
    EG_tb <= '1';
    EM_tb <= '0';
    wait for 50 ns;

    DT_tb <= '0';
    RG_tb <= '0';
    EG_tb <= '1';
    EM_tb <= '1';
    wait for 50 ns;

    DT_tb <= '0';
    RG_tb <= '1';
    EG_tb <= '0';
    EM_tb <= '0';
    wait for 50 ns;

    DT_tb <= '0';
    RG_tb <= '1';
    EG_tb <= '0';
    EM_tb <= '1';
    wait for 50 ns;

    DT_tb <= '0';
    RG_tb <= '1';
    EG_tb <= '1';
    EM_tb <= '0';
    wait for 50 ns;

    DT_tb <= '0';
    RG_tb <= '1';
    EG_tb <= '1';
    EM_tb <= '1';
    wait for 50 ns;

    DT_tb <= '1';
    RG_tb <= '0';
    EG_tb <= '0';
    EM_tb <= '0';
    wait for 50 ns;

    DT_tb <= '1';
    RG_tb <= '0';
    EG_tb <= '0';
    EM_tb <= '1';
    wait for 50 ns;

    DT_tb <= '1';
    RG_tb <= '0';
    EG_tb <= '1';
    EM_tb <= '0';
    wait for 50 ns;

    DT_tb <= '1';
    RG_tb <= '0';
    EG_tb <= '1';
    EM_tb <= '1';
    wait for 50 ns;

    DT_tb <= '1';
    RG_tb <= '1';
    EG_tb <= '0';
    EM_tb <= '0';
    wait for 50 ns;

    DT_tb <= '1';
    RG_tb <= '1';
    EG_tb <= '0';
    EM_tb <= '1';
    wait for 50 ns;

    DT_tb <= '1';
    RG_tb <= '1';
    EG_tb <= '1';
    EM_tb <= '1';

    wait; -- will wait forever
END PROCESS;
-- *** End Test Bench - User Defined Section ***

END; --archietecture

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