--=========================FSM_ANS1=======================


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;


entity FSM_ANS1 is
Port (DT, RG, EG, EM: in STD_LOGIC;
      CN, PL, RD:     out STD_LOGIC;
      CLK, RST:       in STD_LOGIC);
end entity FSM_ANS1;

architecture EXPLICIT of FSM_ANS1 is
type ANS_STATES is (W,P,R);
signal CS, NS: ANS_STATES;
begin
    NS_LOGIC: process (CS, DT, RG, EG, EM)
    begin
        case CS is
            when W =>
                if (RG = '0') then
                    NS <= W;
                else
                    NS <= P;
                end if;
            when P =>
                if (EG = '0' and DT = '0') then
                    NS <= P;
                elsif (EG = '1' and DT = '0') then
                    NS <= R;
                else
                    NS <= W;
                end if;
            when R =>
                if (EM = '0' and DT = '0') then
                    NS <= R;
                else
                    NS <= W;
                end if;
            when others =>
                    NS <= W;
        end case;
    end process NS_LOGIC;
 

    STATE_REG: process (CLK, RST)
    begin
        if( RST = '1') then
            CS <= W;
        elsif RISING_EDGE (CLK) then
            CS <= NS;
        else
            null;
        end if;
    end process STATE_REG;

    OUT_LOGIC: process (CS)
    begin
        case CS is
            when W =>
                CN <= '0';
                PL <= '0';
                RD <= '0';
            when P =>
                CN <= '1';
                PL <= '1';
                RD <= '0';
            when R =>
                CN <= '1';
                PL <= '0';
                RD <= '1';
            when others =>
                CN <= '0';
                PL <= '0';
                RD <= '0';
         end case;
    end process OUT_LOGIC;
 

end architecture EXPLICIT;