Copyright: Copyright 1999, Emil Vladkov
Citation: Philips Data Handbook IC20


8051 User's Manual

•	Complete Instruction Set of the 8051 Processor

•	Instructions that affect Flag settings

•	Addressing Modes

•	Reset

•	Memory Map of the internal RAM

•	Accessing External Memory

•	Interrupts

•	Interrupt Priority

•	Timer Set-Up

•	Serial Port Set-Up

•	8051 Special Function Registers

•	Special Function Register's assigned functions

•	80C51 Pin Descriptions

•	On-circuit Emulation Mode


CompleteInstrSet
Complete Instruction Set for the 8051 Family Processors

•	ACALL addr11

•	ADD A,<src-byte>

•	ADDC A,<src-byte>

•	AJMP addr11

•	ANL <dest-byte>,<src-byte>

•	ANL C,<src-bit>

•	CJNE <dest-byte>,<src-byte>,rel

•	CLR A

•	CLR bit

•	CPL A

•	CPL bit

•	DA A

•	DEC byte

•	DIV AB

•	DJNZ <byte>,<rel-addr>

•	INC <byte>

•	INC DPTR

•	JB bit,rel

•	JBC bit,rel

•	JC rel

•	JMP @A+DPTR

•	JNB bit,rel

•	JNC rel

•	JNZ rel

•	JZ rel

•	LCALL addr16

•	LJMP addr16

•	MOV <dest-byte>,<src-byte>

•	MOV <dest-bit>,<src-bit>

•	MOV DPTR,#data16

•	MOVC A,@A+<base-reg>

•	MOVX <dest-byte>,<src-byte>

•	MUL AB

•	NOP

•	ORL <dest-byte>,<src-byte>

•	ORL C,<src-bit>

•	POP direct

•	PUSH direct

•	RET

•	RETI

•	RL A

•	RLC A

•	RR A

•	RRC A

•	SETB <bit>

•	SJMP rel

•	SUBB A,<src-byte>

•	SWAP A

•	XCH A,<byte>

•	XCHD A,@Ri

•	XRL <dest-byte>,<src-byte>


ACALL addr11

Function: 	Absolute Call

Description: 	ACALL unconditionally calls a subroutine located at the indicated address. The instruction increments the PC twice to obtain the address of the following instruction, then pushes the 16-bit result onto the stack (low-order byte first) and increments the Stack Pointer twice. The destination address is obtained by successively concatenating the five high-order bits of the incremented PC, opcode bits 7-5, and the second byte of the instruction. The subroutine called must therefore start within the same 2k block of the program memory as the first byte of the instruction following ACALL. No flags are affected.

Example: 	Initially SP equals 07H. The label "SUBRTN" is at program memory location 0345H. After executing the instruction,

ACALL	 SUBRTN

at location 0123H, SP will contain 09H, internal RAM locations 08H and 09H will contain 25H and 01H, respectively, and the PC will contain 0345H.

Bytes: 	2

Cycles: 	2

Encoding:	| a10 a9 a8 1 | 0 0 0 1 |   | a7 a6 a5 a4 | a3 a2 a1 a0 |

Operation:	ACALL

(PC) <-- (PC) + 2

(SP) <-- (SP) + 1

(SP) <-- (PC7-0)

(SP) <-- (SP) + 1

(SP) <-- (PC15-8)

(PC10-0) <-- page address


ADD A,<src-byte>

Function: 	Add

Description: 	ADD adds the byte variable indicated to the Accumulator, leaving the result in the Accumulator. The carry and auxiliary-carry flags are set, respectively, if there is a carry-out from bit 7 or bit 3, and cleared otherwise. When adding unsigned integers, the carry flag indicates an overflow occured.

OV is set if there is a carry-out of bit 6 but not out of bit 7, or a carry-out of bit 7 but not bit 6; otherwise OV is cleared. When adding signed integers, OV indicates a negative number produced as the sum of two postive operands, or a positive sum from two negative operands.

Four source operand addressing modes are allowed: register, direct, register-indirect, or immediate.

Example: 	The Accumulator holds 0C3H (11000011B) and register 0 holds 0AAH (10101010B). The instruction,

ADD A,R0

will leave 6DH (01101101B) in the Accumulator with the AC flag cleared and both the Carry flag and OV set to 1.

•	ADD A,Rn

•	ADD A,direct

•	ADD A,@Ri

•	ADD A,#data


ADD A,Rn

Bytes: 	1

Cycles: 	1

Encoding:	| 0 0 1 0 | 1 r r r |

R0 - 28h

R1 - 29h

R2 - 2Ah

R3 - 2Bh

R4 - 2Ch

R5 - 2Dh

R6 - 2Eh

R7 - 2Fh

Operation:	ADD

(A) <-- (A) + (Rn)

UP


ADD A,direct

Bytes: 	2

Cycles: 	1

Encoding:	| 0 0 1 0 | 0 1 0 1 |   | direct address |

Operation:	ADD

(A) <-- (A) + (direct)

UP


ADD A,@Ri

Bytes: 	1

Cycles: 	1

Encoding:	| 0 0 1 0 | 0 1 1 i |

R0 - 26h

R1 - 27h

Operation:	ADD

(A) <-- (A) + ((Ri))

UP


ADD A,#data

Bytes: 	2

Cycles: 	1

Encoding:	| 0 0 1 0 | 0 1 0 0 |   | immediate data |

Operation:	ADD

(A) <-- (A) + #data

UP


ADDC A,<src-byte>

Function: 	Add with Carry

Description: 	ADDC simultaneously adds the byte variable indicated, the carry flag and the Accumulator contents, leaving the result in the Accumulator. The carry and auxiliary-carry flags are set, respectively, if there is a carry-out from bit 7 or bit 3, and cleared otherwise. When adding unsigned integers, the carry flag indicates an overflow occurred.

OV is set if there is a carry-out of bit 6 but not out of bit 7, or a carry-out of bit 7 but not out of bit 6; otherwise OV is cleared. When adding signed integers, OV indicates a negative number produced as the sum of two positive operands, or a positive sum from two negative operands.

Four source operand addressing modes are allowed: register, direct, register-indirect, or immediate.

Example: 	The Accumulator holds 0C3H (11000011B) and register 0 holds 0AAH (10101010B) with the carry flag set. The instruction,

ADDC A,R0

will leave 6EH (01101110B) in the Accumulator with the AC flag cleared and both the Carry flag and OV set to 1.

•	ADDC A,Rn

•	ADDC A,direct

•	ADDC A,@Ri

•	ADDC A,#data


ADDC A,Rn

Bytes: 	1

Cycles: 	1

Encoding:	| 0 0 1 1 | 1 r r r |

R0 - 38h

R1 - 39h

R2 - 3Ah

R3 - 3Bh

R4 - 3Ch

R5 - 3Dh

R6 - 3Eh

R7 - 3Fh

Operation:	ADDC

(A) <-- (A) + (C) + (Rn)

UP


ADDC A,direct

Bytes: 	2

Cycles: 	1

Encoding:	| 0 0 1 1 | 0 1 0 1 |   | direct address |

Operation:	ADDC

(A) <-- (A) + (C) + (direct)

UP


ADDC A,@Ri

Bytes: 	1

Cycles: 	1

Encoding:	| 0 0 1 1 | 0 1 1 i |

R0 - 36h

R1 - 37h

Operation:	ADDC

(A) <-- (A) + (C) + ((Ri))

UP


ADDC A,#data

Bytes: 	2

Cycles: 	1

Encoding:	| 0 0 1 1 | 0 1 0 0 |   | immediate data |

Operation:	ADDC

(A) <-- (A) + (C) + #data

UP


AJMP addr11

Function: 	Absolute Jump

Description: 	AJMP transfers program execution to the indicated address, which is formed at run-time by concatenating the high-order five bits of the PC (after incrementing the PC twice), opcode bits 7-5, and the second byte of the instruction. The destination must therefore be within the same 2k block of program memory as the first byte of the instruction following AJMP.

Example: 	The label "JMPADR" is at program memory location 0123H. The instruction,

AJMP JMPADR

i

s at location 0345H and will load the PC with 0123H.

Bytes: 	2

Cycles: 	2

Encoding:	| a10 a9 a8 0 | 0 0 0 1 |   | a7 a6 a5 a4 | a3 a2 a1 a0 |

Operation:	AJMP

(PC) <-- (PC) + 2

(PC10-0) <-- page address


ANL <dest-byte>,<src-byte>

Function: 	Logical-AND for byte variables

Description: 	ANL performs the bitwise logical-AND operation between the variables indicated and stores the results in the destination variable. No flags are affected.

The two operands allow six addressing mode combinations. When the destination is the Accumulator, the source can use register, direct, register-indirect, or immediate addressing; when the destination is a direct address, the source can be the Accumulator or immediate data.

Note:  When this instruction is used to modify an output port, the value used as the original port data will be read from the output data latch, not  the input pins.

Example: 	If the Accumulator holds 0C3H (11000011B) and register 0 holds 55H (01010101B) then the instruction,

ANL	A,R0

will leave 41H (01000001B) in the Accumulator.

When the destination is a directly addressed byte, this instruction will clear combinations of bits in any RAM location or hardware register. The mask byte determining the pattern of bits to be cleared would either be a constant contained in the instruction or a value computed in the Accumulator at run-time. The instruction,

ANL	P1,#01110011B

will clear bits 7, 3, and 2 of output port 1.

•	ANL A,Rn

•	ANL A,direct

•	ANL A,@Ri

•	ANL A,#data

•	ANL direct,A

•	ANL direct,#data


ANL A,Rn

Bytes: 	1

Cycles: 	1

Encoding:	| 0 1 0 1 | 1 r r r |

R0 - 58h

R1 - 59h

R2 - 5Ah

R3 - 5Bh

R4 - 5Ch

R5 - 5Dh

R6 - 5Eh

R7 - 5Fh

Operation:	ANL

(A) <-- (A) ^ (Rn)

UP


ANL A,direct

Bytes: 	2

Cycles: 	1

Encoding:	| 0 1 0 1 | 0 1 0 1 |   | direct address |

Operation:	ANL

(A) <-- (A) ^ (direct)

UP


ANL A,@Ri

Bytes: 	1

Cycles: 	1

Encoding:	| 0 1 0 1 | 0 1 1 i |

R0 - 56h

R1 - 57h

Operation:	ANL

(A) <-- (A) ^ ((Ri))

UP


ANL A,#data

Bytes: 	2

Cycles: 	1

Encoding:	| 0 1 0 1 | 0 1 0 0 |   | immediate data |

Operation:	ANL

(A) <-- (A) ^ #data

UP


ANL direct,A

Bytes: 	2

Cycles: 	1

Encoding:	| 0 1 0 1 | 0 0 1 0 |   | direct address |

Operation:	ANL

(A) <-- (direct) ^ (A)

UP


ANL direct,#data

Bytes: 	3

Cycles: 	2

Encoding:	| 0 1 0 1 | 0 0 1 1 | | direct address | | immediate data |

Operation:	ANL

(direct) <-- (direct) ^ #data

UP


ANL C,<src-bit>

Function: 	Logical-AND for bit variables

Description: 	If the Boolean value of the source bit is a logical 0 then clear the carry flag; otherwise leave the carry flag in its current state. A slash ("/") preceding the operand in the assembly language indicates that the logical complement of the addressed bit is used as the source value, but the source bit itself is not affected . No other flags are affected.

Only direct addressing is allowed for the source operand.

Example: 	Set the carry flag if, and only if, P1.0 = 1, ACC.7 = 1, and OV = 0:

MOV	C,P1.0	;LOAD CARRY WITH INPUT PIN STATE

ANL	C,ACC.7 ;AND CARRY WITH ACCUM.BIT 7

ANL	C,/OV	;AND WITH INVERSE OF OVERFLOW FLAG

•	ANL C,bit

•	ANL C,/bit


ANL C,bit

Bytes: 	2

Cycles: 	2

Encoding:	| 1 0 0 0 | 0 0 1 0 |   | bit address |

Operation:	ANL

(C) <-- (C) ^ (bit)

UP


ANL C,/bit

Bytes: 	2

Cycles: 	2

Encoding:	| 1 0 1 1 | 0 0 0 0 |   | bit address |

Operation:	ANL

(C) <-- (C) ^ /(bit)

UP


CJNE <dest-byte>,<src-byte>,rel

Function: 	Compare and Jump if Not Equal

Description: 	CJNE compares the magnitudes of the first two operands, and branches if their values are not equal. The branch destination is computed by adding the signed relative-displacement in the last instruction byte to the PC, after incrementing the PC to the start of the next instruction. The carry flag is set if the unsigned integer value of <dest-byte> is less than the unsigned integer value of <src-byte>; otherwise, the carry is cleared. Neither operand is affected.

The first two operands allow four addressing mode combinations: the Accumulator may be compared with any directly addressed byte or immediate data, and any indirect RAM location or working register can be compared with an immediate constant.

Example: 	The Accumulator contains 34H. Register 7 contains 56H. The first instruction in the sequence,

CJNE	R7,#60H,NOT_EQ

;	...	...	;R7 = 60H.

NOT_EQ:  JC	REQ_LOW	;IF R7 < 60H.

;	...	...	;R7 > 60H.

sets the carry flag and branches to the instruction at label NOT_EQ. By testing the carry flag, this instruction determines whether R7 is greater or less than 60H.

If the data being presented to Port 1 is also 34H, then the instruction,

WAIT:	CJNE	A,P1,WAIT

clears the carry flag and continues with the next instruction in sequence, since the Accumulator does equal the data read from P1. (If some other value was being input on P1, the program will loop at this point untill the P1 data changes to 34H.)

•	CJNE A,direct,rel

•	CJNE A,#data,rel

•	CJNE Rn,#data,rel

•	CJNE @Ri,#data,rel


CJNE A,direct,rel

Bytes: 	3

Cycles: 	2

Encoding:	| 1 0 1 1 | 0 1 0 1 | | direct address | | rel.address |

Operation:	(PC) <-- (PC) + 3

IF (A) < > (direct)

THEN

(PC) <-- (PC) + relative offset

IF (A) < (direct)

THEN

(C) <-- 1

ELSE

(C) <-- 0

UP


CJNE A,#data,rel

Bytes: 	3

Cycles: 	2

Encoding:	| 1 0 1 1 | 0 1 0 0 | | immediate data | | rel.address |

Operation:	(PC) <-- (PC) + 3

IF (A) < > data

THEN

(PC) <-- (PC) + relative offset

IF (A) < data

THEN

(C) <-- 1

ELSE

(C) <-- 0

UP


CJNE Rn,#data,rel

Bytes: 	3

Cycles: 	2

Encoding:	| 1 0 1 1 | 1 r r r | | immediate data | | rel.address |

R0 - 0B8h

R1 - 0B9h

R2 - 0BAh

R3 - 0BBh

R4 - 0BCh

R5 - 0BDh

R6 - 0BEh

R7 - 0BFh

Operation:	(PC) <-- (PC) + 3

IF (Rn) < > data

THEN

(PC) <-- (PC) + relative offset

IF (Rn) < data

THEN

(C) <-- 1

ELSE

(C) <-- 0

UP


CJNE @Ri,#data,rel

Bytes: 	3

Cycles: 	2

Encoding:	| 1 0 1 1 | 0 1 1 i | | immediate data | | rel.address |

R0 - 0B6h

R1 - 0B7h

Operation:	(PC) <-- (PC) + 3

IF ((Ri)) < > data

THEN

(PC) <-- (PC) + relative offset

IF ((Ri)) < data

THEN

(C) <-- 1

ELSE

(C) <-- 0

UP


CLR A

Function: 	Clear Accumulator

Description: 	The Accumulator is cleared (all bits reset to zero). No flags are affected.

Example: 	The Accumulator contains 5CH (01011100B). The instruction,

CLR A

will leave the Accumulator set to 00H (00000000B).

Bytes: 	1

Cycles: 	1

Encoding:	| 1 1 1 0 | 0 1 0 0 |

Operation:	CLR

(A) <-- 0


CLR bit

Function: 	Clear bit

Description: 	The indicated bit is cleared (reset to zero). No other flags are affected. CLR can operate on the carry flag or any directly addressable bit.

Example: 	Port 1 has previously been written with 5DH (01011101B). The instruction,

CLR 	P1.2

will leave the port set to 59H (01011001B).

•	CLR C

•	CLR bit


CLR C

Bytes: 	1

Cycles: 	1

Encoding:	| 1 1 0 0 | 0 0 1 1 |

Operation:	CLR

(C) <-- 0

UP


CLR bit 1
CLR bit

Bytes: 	2

Cycles: 	1

Encoding:	| 1 1 0 0 | 0 0 1 0 |  | bit address |

Operation:	CLR

(bit) <-- 0

UP


CPL A

Function: 	Complement Accumulator

Description: 	Each bit of the Accumulator is logically complemented (one's complement). Bits which previously contained a one are changed to a zero and vice-versa. No flags are affected.

Example: 	The Accumulator contains 5CH (01011100B). The instruction,

CPL A

will leave the Accumulator set to 0A3H (10100011B).

Bytes: 	1

Cycles: 	1

Encoding:	| 1 1 1 1 | 0 1 0 0 |

Operation:	CPL

(A) <-- /(A)


CPL bit

Function: 	Complement bit

Description: 	The bit variable specified is complemented. A bit which had been a one is changed to zero and vice-versa. No other flags are affected. CPL can operate on the carry or any directly addressable bit.

Note:  When this instruction is used to modify an output pin, the value used as the original data will be read from the output data latch, not  the input pin.

Example: 	Port 1 has previously been written with 5DH (01011101B). The instruction sequence,

CPL 	P1.1

CPL	P1.2

will leave the port set to 5BH (01011011B).

•	CPL C

•	CPL bit


CPL C

Bytes: 	1

Cycles: 	1

Encoding:	| 1 0 1 1 | 0 0 1 1 |

Operation:	CPL

(C) <-- /(C)

UP


CPL bit 1
CPL bit

Bytes: 	2

Cycles: 	1

Encoding:	| 1 0 1 1 | 0 0 1 0 |  | bit address |

Operation:	CPL

(bit) <-- /(bit)

UP


DA A

Function: 	Decimal-adjust Accumulator for Addition

Description: 	DA A adjusts the eight-bit value in the Accumulator resulting from the earlier addition of two variable (each in packed-BCD format), producing two four-bit digits. Any ADD or ADDC instruction may have been used to perform the addition.

If Accumulator bits 3-0 are greater than nine (xxx1010-xxx1111), or if the AC flag is one, six is added to the Accumulator, producing the proper BCD digit in the low-order nibble. This internal addition would set the carry flag if a carry-out of the low order four-bit field propagated through all high-order bits, but it would not clear the carry flag otherwise.

If the carry flag is now set, or if the four high-order bits now exceed nine (1010xxx-1111xxx), these high-order bits are incremented by six, producing the proper BCD digit in the high-order nibble. Again, this would set the carry flag if there was a carry-out of the high-order bits, but wouldn't clear the carry. The carry flag thus indicates if the sum of the original two BCD variables is greater than 100, allowing multiple precision decimal addition. OV is not affected.

All of this occurs during the one instruction cycle. Essentially, this instruction performs the decimal conversion by adding 00H, 06H, 60H, or 66H to the Accumulator, depending on initial Accumulator and PSW conditions.

Note:  DA A cannot  simply convert a hexadecimal number in the Accumulator to BCD notation, nor does DA A apply to decimal subtraction.

Example: 	The Accumulator holds the value 56H (01010110B) representing the packed BCD digits of the decimal number 56. Register 3 contains the value 67H (01100111B) representing the packed BCD digits of the decimal number 67. The carry flag is set. The instruction sequence,

ADDC	A,R3

DA	A

will first perform a standard two's-complement binary addition , resulting in the value 0BEH (10111110B) in the Accumulator. The carry and auxiliary carry flags will be cleared.

The Decimal Adjust instruction will then alter the Accumulator to the value 24H (00100100B), indicating the packed BCD digits of the decimal number 24, the low-order two digits of the decimal sum of 56, 67, and the carry-in. The carry flag will be set by the Decimal Adjust instruction, indicating that a decimal overflow occurred. The true sum 56, 67, and 1 is 124.

BCD variables can be incremented or decremented by adding 01H or 99H. If the Accumulator initially holds 30H (representing the digits of 30 decimal), then the instruction sequence,

ADD	A,#99H

DA	A

will leave the carry set and 29 in the Accumulator, since 30+99=129. The low-order byte of the sum can be interpreted to mean 30-1=29.

Bytes: 	1

Cycles: 	1

Encoding:	| 1 1 0 1 | 0 1 0 0 |

Operation:	DA

- contents of Accumulator are BCD

IF	[[(A3-0)>9] or [(AC)=1]]

THEN (A3-0) <-- (A3-0) + 6

AND

IF	[[(A7-4)>9] or [(C)=1]]

THEN (A7-4) <-- (A7-4) + 6


DEC byte

Function: 	Decrement

Description: 	The variable indicated is decremented by 1. An original value of 00H will underflow to 0FFH. No flags are affected. Four operand addressing modes are allowed: accumulator, register, direct, or register-indirect.

Note:  When this instruction is used to modify an output port, the value used as the original data will be read from the output data latch, not  the input pin.

Example: 	Register 0 contains 7FH (01111111B). Internal RAM locations 7EH and 7FH contain 00H and 40H, respectively. The instruction sequence,

DEC	@R0

DEC	R0

DEC	@R0

will leave register 0 set to 7EH and internal RAM locations 7EH and 7FH set to 0FFH and 3FH.

•	DEC A

•	DEC Rn

•	DEC direct

•	DEC @Ri


DEC A

Bytes: 	1

Cycles: 	1

Encoding:	| 0 0 0 1 | 0 1 0 0 |

Operation:	DEC

(A) <-- (A) - 1

UP


DEC Rn

Bytes: 	1

Cycles: 	1

Encoding:	| 0 0 0 1 | 1 r r r |

R0 - 18h

R1 - 19h

R2 - 1Ah

R3 - 1Bh

R4 - 1Ch

R5 - 1Dh

R6 - 1Eh

R7 - 1Fh

Operation:	DEC

(Rn) <-- (Rn) - 1

UP


DEC direct

Bytes: 	2

Cycles: 	1

Encoding:	| 0 0 0 1 | 0 1 0 1 |  | direct address |

Operation:	DEC

(direct) <-- (direct) - 1

UP


DEC @Ri

Bytes: 	1

Cycles: 	1

Encoding:	| 0 0 0 1 | 0 1 1 i |

R0 - 16h

R1 - 17h

Operation:	DEC

((Ri)) <-- ((Ri)) - 1

UP


DIV AB

Function: 	Divide

Description: 	DIV AB divides the unsigned eight-bit integer in the Accumulator by the unsigned eight-bit integer in register B.

The Accumulator receives the integer part of the quotient; register B receives the integer remainder. The carry and OV flags will be cleared.

Exception:  if B had originally contained 00H, the values returned in the Accumulator and B-register will be undefined and the overflow flag will be set. The carry flag is cleared in any case.

Example: 	The Accumulator contains 251 (0FBh or 11111011B) and B contains 18 (12H or 00010010B). The instruction,

DIV	AB

will leave 13 in the Accumulator (0DH or 00001101B) and the value 17 (11H or 00010001B) in B, since 251=(13x18)+17. Carry and OV will both be cleared.

Bytes: 	1

Cycles: 	4

Encoding:	| 1 0 0 0 | 0 1 0 0 |

Operation:	DIV

(A)15-8 <-- (A)/(B)

(B)7-0


DJNZ <byte>,<rel-addr>

Function: 	Decrement and Jump if Not Zero

Description: 	DJNZ decrements the location indicated by 1, and branches to the address indicated by the second operand if the resulting value is not zero. An original value of 00H will underflow to 0FFH. No flags are affected. The branch destination would be computed by adding the signed relative-displacement value in the last instruction byte to the PC, after incrementing the PC to the first byte of the following instruction.

The location decremented may be a register or directly addressed byte.

Note:  When this instruction is used to modify an output port, the value used as the original port data will be read from the output data latch, not  the input pins.

Example: 	Internal RAM locations 40H, 50H, and 60H contain the values 01H, 70H, and 15H, respectively. The instruction sequence,

DJNZ 40H,LABEL_1

DJNZ 50H,LABEL_2

DJNZ 60H,LABEL_3

will cause a jump to the instruction at LABEL_2 with the values 00H, 6FH, and 15H in the three RAM locations. The first jump was not  taken because the result was zero.

This instruction provides a simple way of executing a program loop a given number of times, or for adding a moderate time delay (from 2 to 512 machine cycles) with a single instruction. The instruction sequence,

MOV	R2,#8

TOGGLE:	CPL	P1.7

DJNZ	R2,TOGGLE

will toggle P1.7 eight times, causing four output pulses to appear at bit 7 of output Port 1. Each pulse will last three machine cycles, two for DJNZ and one to alter the pin.

•	DJNZ Rn,rel

•	DJNZ direct,rel


DJNZ Rn,rel

Bytes: 	2

Cycles: 	2

Encoding:	| 1 1 0 1 | 1 r r r | | rel.address |

R0 - 0D8h

R1 - 0D9h

R2 - 0DAh

R3 - 0DBh

R4 - 0DCh

R5 - 0DDh

R6 - 0DEh

R7 - 0DFh

Operation:	DJNZ

(PC) <-- (PC) + 2

(Rn) <-- (Rn) - 1

IF (Rn) > 0 or (Rn) < 0

THEN

(PC) <-- (PC) +rel

UP


DJNZ direct,rel

Bytes: 	3

Cycles: 	2

Encoding:	| 1 1 0 1 | 0 1 0 1 | | direct data | | rel.address |

Operation:	DJNZ

(PC) <-- (PC) + 2

(direct) <-- (direct) - 1

IF (direct) > 0 or (direct) < 0

THEN

(PC) <-- (PC) + rel

UP


INC <byte>

Function: 	Increment

Description: 	INC increments the indicated variable by 1. An original value of 0FFH will overflow to 00H. No flags are affected. Three addressing modes are allowed: register, direct, or register-indirect.

Note:  When this instruction is used to modify an output port, the value used as the original port data will be read from the output data latch, not  the input pins.

Example: 	Register 0 contains 7EH (01111110B). Internal RAM locations 7EH and 7FH contain 0FFH and 40H, respectively. The instruction sequence,

INC	@R0

INC	R0

INC	@R0

will leave register 0 set to 7FH and internal RAM locations 7EH and 7FH holding (respectively) 00H and 41H.

•	INC A

•	INC Rn

•	INC direct

•	INC @Ri


INC A

Bytes: 	1

Cycles: 	1

Encoding:	| 0 0 0 0 | 0 1 0 0 |

Operation:	INC

(A) <-- (A) + 1

UP


INC Rn

Bytes: 	1

Cycles: 	1

Encoding:	| 0 0 0 0 | 1 r r r |

R0 - 08h

R1 - 09h

R2 - 0Ah

R3 - 0Bh

R4 - 0Ch

R5 - 0Dh

R6 - 0Eh

R7 - 0Fh

Operation:	INC

(Rn) <-- (Rn) + 1

UP


INC direct

Bytes: 	2

Cycles: 	1

Encoding:	| 0 0 0 0 | 0 1 0 1 |  | direct address |

Operation:	INC

(direct) <-- (direct) + 1

UP


INC @Ri

Bytes: 	1

Cycles: 	1

Encoding:	| 0 0 0 0 | 0 1 1 i |

R0 - 06h

R1 - 07h

Operation:	INC

((Ri)) <-- ((Ri)) + 1

UP


INC DPTR

Function: 	Increment Data Pointer

Description: 	Increment the 16-bit data pointer by 1. A 16-bit increment (modulo 2^16) is performed; an overflow of the low-order byte of the data pointer (DPL) from 0FFH to 00H will increment the high-order byte (DPH). No flags are affected.

This is the only 16-bit register which can be incremented.

Example: 	Registers DPH and DPL contain 12H and 0FEH, respectively. The instruction sequence,

INC	DPTR

INC	DPTR

INC	DPTR

will change DPH and DPL to 13H and 01H

Bytes: 	1

Cycles: 	2

Encoding:	| 1 0 1 0 | 0 0 1 1 |

Operation:	INC

(DPTR) <-- (DPTR) + 1


JB bit,rel

Function: 	Jump if Bit set

Description: 	If the indicated bit is a one, jump to the address indicated; otherwise proceed with the next instruction. The branch destination is computed by adding the signed relative-displacement in the third instruction byte to the PC, after incrementing the PC to the first byte of the next instruction. The bit tested is not modified.  No flags are affected.

Example: 	The data present at input port 1 is 11001010B. The Accumulator holds 56 (01010110B). The instruction sequence,

JB	P1.2,LABEL1

JB	ACC.2,LABEL2

will cause program execution to branch to the instruction at label LABEL2.

Bytes: 	3

Cycles: 	2

Encoding:	| 0 0 1 0 | 0 0 0 0 | | bit address | | rel.address |

Operation:	JB

(PC) <-- (PC) + 3

IF (bit) = 1

THEN

(PC) <-- (PC) + rel


JBC bit,rel

Function: 	Jump if Bit is set and Clear bit

Description: 	If the indicated bit is a one, branch to the address indicated; otherwise proceed with the next instruction. The bit will not be cleared if it is already a zero. The branch destination is computed by adding the signed relative-displacement in the third instruction byte to the PC, after incrementing the PC to the first byte of the next instruction. No flags are affected.

Note:  When this instruction is used to test an output pin, the value used as the original data will read from the output data latch, not the input pin.

Example: 	The Accumulator holds 56H (01010110B). The instruction sequence,

JBC	ACC.3,LABEL1

JBC	ACC.2,LABEL2

will cause program execution to continue at the instruction identified by the LABEL2, with the Accumulator modified to 52H (01010010B).

Bytes: 	3

Cycles: 	2

Encoding:	| 0 0 0 1 | 0 0 0 0 | | bit address | | rel.address |

Operation:	JBC

(PC) <-- (PC) + 3

IF (bit) = 1

THEN

(bit) <-- 0

(PC) <-- (PC) + rel


JC rel

Function: 	Jump if Carry is set

Description: 	If the carry flag is set, branch to the address indicated; otherwise proceed with the next instruction. The branch destination is computed by adding the signed relative-displacement in the second instruction byte to the PC, after incrementing the PC twice. No flags are affected.

Example: 	The carry flag is cleared. The instruction sequence,

JC	LABEL1

CPL	C

JC	LABEL2

will set the carry and cause program execution to continue at the instruction identified by the label LABEL2.

Bytes: 	2

Cycles: 	2

Encoding:	| 0 1 0 0 | 0 0 0 0 | | rel.address |

Operation:	JC

(PC) <-- (PC) + 2

IF (C) = 1

THEN

(PC) <-- (PC) + rel


JMP @A+DPTR

Function: 	Jump indirect

Description: 	Add the eight-bit unsigned contents of the Accumulator with the sixteen-bit data pointer, and load the resulting sum to the program counter. This will be the address for subsequent instruction fetches. Sixteen-bit addition is performed (modulo 2^16): a carry-out from the low-order eight bits propagates through the higher-order bits. Neither the Accumulator nor the Data Pointer is altered. No flags are affected.

Example: 	An even number from 0 to 6 is in the Accumulator. The following sequence of instructions will branch to one of four AJMP instructions in a jump table starting at JMP_TBL:

MOV	DPTR,#JMP_TBL

JMP	@A+DPTR

JMP_TBL:	AJMP	LABEL0

AJMP	LABEL1

AJMP	LABEL2

AJMP	LABEL3

If the Accumulator equals 04H when starting this sequence, execution will jump to label LABEL2. Remember that AJMP is a two-byte instruction, so the jump instruction start at every other address.

Bytes: 	1

Cycles: 	2

Encoding:	| 0 1 1 1 | 0 0 1 1 |

Operation:	JMP

(PC) <-- (A) + (DPTR)


JNB bit,rel

Function: 	Jump if Bit Not set

Description: 	If the indcated bit is a zero, branch to the indicated address; otherwise proceed with the next instruction. The branch destination is computed by adding the signed relative-displacement in the third instruction byte to the PC, after incrementing the PC to the first byte of the next instruction. The bit tested is not modified.  No flags are affected.

Example: 	The data present at input port 1 is 11001010B. The Accumulator holds 56H (01010110B). The instruction sequence,

JNB	P1.3,LABEL1

JNB	ACC.3,LABEL2

will cause program execution to continue at the instruction at label LABEL2.

Bytes: 	3

Cycles: 	2

Encoding:	| 0 0 1 1 | 0 0 0 0 | | bit address | | rel.address |

Operation:	JNB

(PC) <-- (PC) + 3

IF (bit) = 0

THEN

(PC) <-- (PC) + rel


JNC rel

Function: 	Jump if Carry Not set

Description: 	If the carry flag is a zero, branch to the address indicated; otherwise proceed with the next instruction. The branch destination is computed by adding the signed relative-displacement in the second instruction byte to the PC, after incrementing the PC twice to point to the next instruction. The carry flag is not modified.

Example: 	The carry flag is set. The instruction sequence,

JNC	LABEL1

CPL	C

JNC	LABEL2

will clear the carry and cause program execution to continue at the instruction identified by the label LABEL2.

Bytes: 	2

Cycles: 	2

Encoding:	| 0 1 0 1 | 0 0 0 0 | | rel.address |

Operation:	JNC

(PC) <-- (PC) + 2

IF (C) = 0

THEN

(PC) <-- (PC) + rel


JNZ rel

Function: 	Jump if Accumulator Not Zero

Description: 	If any bit of the Accumulator is a one, branch to the indicated address; otherwise proceed with the next instruction. The branch destination is computed by adding the signed relative-displacement in the second instruction byte to the PC, after incrementing the PC twice. The Accumulator is not modified. No flags are affected.

Example: 	The Accumulator originally holds 00H. The instruction sequence,

JNZ	LABEL1

INC	A

JNZ	LABEL2

will set the Accumulator to 01H and continue at label LABEL2.

Bytes: 	2

Cycles: 	2

Encoding:	| 0 1 1 1 | 0 0 0 0 | | rel.address |

Operation:	JNZ

(PC) <-- (PC) + 2

IF A /= 0

THEN

(PC) <-- (PC) + rel


JZ rel

Function: 	Jump if Accumulator Zero

Description: 	If all bits of the Accumulator are zero, branch to the indicated address; otherwise proceed with the next instruction. The branch destination is computed by adding the signed relative-displacement in the second instruction byte to the PC, after incrementing the PC twice. The Accumulator is not modified. No flags are affected.

Example: 	The Accumulator originally holds 01H. The instruction sequence,

JZ	LABEL1

DEC	A

JZ	LABEL2

will change the Accumulator to 00H and cause program execution to continue at the instruction identified by the label LABEL2.

Bytes: 	2

Cycles: 	2

Encoding:	| 0 1 1 0 | 0 0 0 0 | | rel.address |

Operation:	JZ

(PC) <-- (PC) + 2

IF A = 0

THEN

(PC) <-- (PC) + rel


LCALL addr16

Function: 	Long Call

Description: 	LCALL calls a subroutine located at the indicated address. The instruction adds three to the program counter to generate the address of the next instruction and then pushes the 16-bit result onto the stack (low byte first), incrementing the Stack Pointer by two. The high-order and low-order bytes of the PC are then loaded, respectively, with the second and third bytes of the LCALL instruction. Program execution continues with the instruction at this address. The subroutine may therefore begin anywhere in the full 64k-byte program memory address space. No flags are affected.

Example: 	Initially the Stack Pointer equals 07H. The label "SUBRTN" is assigned to program memory location 1234H. After executing the instruction,

LCALL SUBRTN

at location 0123H, the Stack Pointer will contain 09H, internal RAM locations 08H and 09H will contain 26H and 01H, and the PC will contain 1234H.

Bytes: 	3

Cycles: 	2

Encoding:	| 0 0 0 1 | 0 0 1 0 |   | addr15-addr8 |  | addr7-addr0 |

Operation:	LCALL

(PC) <-- (PC) + 3

(SP) <-- (SP) + 1

((SP)) <-- (PC7-0)

(SP) <-- (SP) + 1

((SP)) <-- (PC15-8)

(PC) <-- addr15-0


LJMP addr16
LJMP addr16 (Implemented in 87C751 and 87C752 for in-circuit emulation only.)

Function: 	Long Jump

Description: 	LJMP causes an unconditional branch to the indicated address, by loading the high-order and low-order bytes of the PC (respectively) with the second and third instruction bytes. The destination may therefore be anywhere in the full 64k program memory address space. No flags are affected.

Example: 	The label "JMPADR" is assigned to the instruction at program memory location 1234H. The instruction,

LJMP	JMPADR

at location 0123H will load the program counter with 1234H.

Bytes: 	3

Cycles: 	2

Encoding:	| 0 0 0 0 | 0 0 1 0 |   | addr15-addr8 |  | addr7-addr0 |

Operation:	LJMP

(PC) <-- addr15-0


MOV <dest-byte>,<src-byte>

Function: 	Move byte variable

Description: 	The byte variable indicated by the second operand is copied into the location specified by the first operand. The source byte is not affected. No other register or flag is affected.

This is by far the most flexible operation. Fifteen combinations of source and destination addressing modes are allowed.

Example: 	Internal RAM location 30H holds 40H. The value of RAM location 40H is 10H. The data present at input port 1 is 11001010B (0CAH). The instruction sequence,

MOV	R0,#30H	;R0<-30H

MOV	A,@R0	;A<-40H

MOV	R1,A	;R1<-40H

MOV	B,@R1	;B<-10H

MOV	@R1,P1	;RAM(40H)<-0CAH

MOV	P2,P1	;P2<-#0CAH

leaves the value 30H in register 0, 40H in both the Accumulator and register 1, 10H in register B, and 0CAH (11001010B) both in RAM location 40H and output on port 2.

•	MOV A,Rn

•	MOV A,direct

•	MOV A,@Ri

•	MOV A,#data

•	MOV Rn,A

•	MOV Rn,direct

•	MOV Rn,#data

•	MOV direct,A

•	MOV direct,Rn

•	MOV direct,direct

•	MOV direct,@Ri

•	MOV direct,#data

•	MOV @Ri,A

•	MOV @Ri,direct

•	MOV @Ri,#data


MOV A,Rn

Bytes: 	1

Cycles: 	1

Encoding:	| 1 1 1 0 | 1 r r r |

R0 - 0E8h

R1 - 0E9h

R2 - 0EAh

R3 - 0EBh

R4 - 0ECh

R5 - 0EDh

R6 - 0EEh

R7 - 0EFh

Operation:	MOV

(A) <-- (Rn)

UP


MOV A,direct

* MOV A,ACC is not a valid instruction.

Bytes: 	2

Cycles: 	1

Encoding:	| 1 1 1 0 | 0 1 0 1 |  | direct address |

Operation:	MOV

(A) <-- (direct)

UP


MOV A,@Ri

Bytes: 	1

Cycles: 	1

Encoding:	| 1 1 1 0 | 0 1 1 i |

R0 - 0E6h

R1 - 0E7h

Operation:	MOV

(A) <-- ((Ri))

UP


MOV A,#data

Bytes: 	2

Cycles: 	1

Encoding:	| 0 1 1 1 | 0 1 0 0 |  | immediate data |

Operation:	MOV

(A) <-- #data

UP


MOV Rn,A

Bytes: 	1

Cycles: 	1

Encoding:	| 1 1 1 1 | 1 r r r |

R0 - 0F8h

R1 - 0F9h

R2 - 0FAh

R3 - 0FBh

R4 - 0FCh

R5 - 0FDh

R6 - 0FEh

R7 - 0FFh

Operation:	MOV

(Rn) <-- (A)

UP


MOV Rn,direct

Bytes: 	2

Cycles: 	2

Encoding:	| 1 0 1 0 | 1 r r r |  | direct address |

R0 - 0A8h

R1 - 0A9h

R2 - 0AAh

R3 - 0ABh

R4 - 0ACh

R5 - 0ADh

R6 - 0AEh

R7 - 0AFh

Operation:	MOV

(Rn) <-- (direct)

UP


MOV Rn,#data

Bytes: 	2

Cycles: 	1

Encoding:	| 0 1 1 1 | 1 r r r |  | immediate data |

R0 - 78h

R1 - 79h

R2 - 7Ah

R3 - 7Bh

R4 - 7Ch

R5 - 7Dh

R6 - 7Eh

R7 - 7Fh

Operation:	MOV

(Rn) <-- #data

UP


MOV direct,A

Bytes: 	2

Cycles: 	1

Encoding:	| 1 1 1 1 | 0 1 0 1 |  | direct address |

Operation:	MOV

(direct) <-- (A)

UP


MOV direct,Rn

Bytes: 	2

Cycles: 	2

Encoding:	| 1 0 0 0 | 1 r r r |  | direct address |

R0 - 88h

R1 - 89h

R2 - 8Ah

R3 - 8Bh

R4 - 8Ch

R5 - 8Dh

R6 - 8Eh

R7 - 8Fh

Operation:	MOV

(direct) <-- (Rn)

UP


MOV direct,direct

Bytes: 	3

Cycles: 	2

Encoding:	| 1 0 0 0 | 0 1 0 1 |  | dir.addr.(src) |  | dir.addr.(dest) |

Operation:	MOV

(direct) <-- (direct)

UP


MOV direct,@Ri

Bytes: 	2

Cycles: 	2

Encoding:	| 1 0 0 0 | 0 1 1 i |  | direct address |

R0 - 86h

R1 - 87h

Operation:	MOV

(direct) <-- ((Ri))

UP


MOV direct,#data

Bytes: 	3

Cycles: 	2

Encoding:	| 0 1 1 1 | 0 1 0 1 |  | direct address |  | immediate data |

Operation:	MOV

(direct) <-- #data

UP


MOV @Ri,A

Bytes: 	1

Cycles: 	1

Encoding:	| 1 1 1 1 | 0 1 1 i |

R0 - 0F6h

R1 - 0F7h

Operation:	MOV

((Ri)) <-- (A)

UP


MOV @Ri,direct

Bytes: 	2

Cycles: 	2

Encoding:	| 1 0 1 0 | 0 1 1 i |  | direct address |

R0 - 0A6h

R1 - 0A7h

Operation:	MOV

((Ri)) <-- (direct)

UP


MOV @Ri,#data

Bytes: 	2

Cycles: 	1

Encoding:	| 0 1 1 1 | 0 1 1 i |  | immediate data |

R0 - 76h

R1 - 77h

Operation:	MOV

((Ri)) <-- #data

UP


MOV <dest-bit>,<src-bit>

Function: 	Move bit data

Description: 	The Boolean variable indicated by the second operand is copied into the location specified by the first operand. One of the operands must be the carry flag; the other may be any directly addressable bit. No other register or flag is affected.

Example: 	The carry flag is originally set. The data present at input Port 3 is 11000101B. The data previously written to output Port 1 is 35H (00110101B). The instruction sequence,

MOV	P1.3,C

MOV	C,P3.3

MOV	P1.2,C

will leave the carry cleared and change Port 1 to 39H (00111001B).

•	MOV C,bit

•	MOV bit,C


MOV C,bit

Bytes: 	2

Cycles: 	1

Encoding:	| 1 0 1 0 | 0 0 1 0 |  | bit address |

Operation:	MOV

(C) <-- (bit)

UP


MOV bit,C

Bytes: 	2

Cycles: 	2

Encoding:	| 1 0 0 1 | 0 0 1 0 |  | bit address |

Operation:	MOV

(bit) <-- (C)

UP


MOV DPTR,#data16

Function: 	Load Data Pointer with a 16-bit constant

Description: 	The Data Pointer is loaded with the 16-bit constant indicated. The 16-bit constant is loaded into the second and third bytes of the instruction. The second byte (DPH) is the high-order byte, while the third byte (DPL) holds the low-order byte. No flags are affected.

This is the only instruction which moves 16 bits of data at once.

Example: 	The instruction,

MOV	DPTR,#1234H

will load the value 1234H into the Data Pointer: DPH will hold 12H and DPL will hold 34H.

Bytes: 	3

Cycles: 	2

Encoding:	| 1 0 0 1 | 0 0 0 0 | | immed.data 15-8 | | immed.data 7-0 |

Operation:	MOV

(DPTR) <-- (#data15-0)

DPH & DPL <-- #data15-8 & #data7-0


MOVC A,@A+<base-reg>

Function: 	Move Code byte

Description: 	The MOVC instructions load the Accumulator with a code byte, or constant from program memory. The address of the byte fetched is the sum of the original unsigned eight-bit Accumulator contents and the contents of a sixteen-bit base register, which may be either the Data Pointer or the PC. In the latter case, the PC is incremented to the address of the following instruction before being added with the Accumulator; otherwise the base register is not altered. Sixteen-bit addition is performed so a carry-out from the low-order eight bits may propagate through higher-order bits. No flags are affected.

Example: 	A value between 0 and 3 is in the Accumulator. The following instructions will translate the value in the Accumulator to one of four values defined by the DB (define byte) directive:

REL_PC:	INC	A

MOVC A,@A+PC

RET

DB	66H

DB	77H

DB	88H

DB	99H

If the subroutine is called with the Accumulator equal to 01H, it will return with 77H in the Accumulator. The INC A before the MOVC instruction is needed to "get around" the RET instruction above the table. If several bytes of code separated the MOVC from the table, the corresponding number would be added to the Accumulator instead.

•	MOVC A,@A+DPTR

•	MOVC A,@A+PC


MOVC A,@A+DPTR

Bytes: 	1

Cycles: 	2

Encoding:	| 1 0 0 1 | 0 0 1 1 |

Operation:	MOVC

(A) <-- ((A) + (DPTR))

UP


MOVC A,@A+PC

Bytes: 	1

Cycles: 	2

Encoding:	| 1 0 0 0 | 0 0 1 1 |

Operation:	MOVC

(PC) <-- (PC) + 1

(A) <-- ((A) + (PC))

UP


MOVX <dest-byte>,<src-byte>
MOVX <dest-byte>,<src-byte> (Not implemented in the 8XC751 or 8XC752)

Function: 	Move External

Description: 	The MOVX instructions transfer data between the Accumulator and a byte of external data memory, hence the "X" appended to MOV. There are two types of instructions, differing in whether they provide an eight-bit or sixteen-bit indirect address to the external data RAM.

In the first type, the contents of R0 or R1 in the current register bank provide an eight-bit address multiplexed with data on P0. Eight bits are sufficient for external I/O expansion decoding or for a relatively small RAM array. For somewhat larger arrays, port pins can be used to output higher-order address bits. These pins would be controlled by an output instruction preceding the MOVX.

In the second type of MOVX instruction, the Data Pointer generates a sixteen-bit address. P2 outputs the high-order eight address bits (the contents of DPH) while P0 multiplexes the low-order eight bits (DPL) with data. The P2 Special Function Register retains its previous contents while the P2 output buffers are emitting the contents of DPH. This form is faster and more efficient when accessing very large data arrays (up to 64k bytes), since no additional instructions are needed to set up the output ports.

It is possible in some situations to mix the two MOVX types. A large RAM array with its high-order address lines driven by P2 can be addressed via the Data Pointer, or with code to output high-order address bits to P2 followed by a MOVX instruction using R0 or R1.

Example: 	An external 256 byte RAM using multiplexed address/data lines is connected to the 8051 Port 0. Port 3 provides control lines for the external RAM. Ports 1 and 2 are used for normal I/O. Registers 0 and 1 contain 12H and 34H. Location 34H of the external RAM holds the value 56H. The instruction sequence,

MOVX	A,@R1

MOVX	@R0,A

copies the value 56H into both the Accumulator and external RAM location 12H.

•	MOVX A,@Ri

•	MOVX A,@DPTR

•	MOVX @Ri,A

•	MOVX @DPTR,A


MOVX A,@Ri

Bytes: 	1

Cycles: 	2

Encoding:	| 1 1 1 0 | 0 0 1 i |

R0 - 0E2h

R1 - 0E3h

Operation:	MOVX

(A) <-- ((Ri))

UP


MOVX A,@DPTR

Bytes: 	1

Cycles: 	2

Encoding:	| 1 1 1 0 | 0 0 0 0 |

Operation:	MOVX

(A) <-- ((DPTR))

UP


MOVX @Ri,A

Bytes: 	1

Cycles: 	2

Encoding:	| 1 1 1 1 | 0 0 1 i |

R0 - 0F2h

R1 - 0F3h

Operation:	MOVX

((Ri)) <-- (A)

UP


MOVX @DPTR,A

Bytes: 	1

Cycles: 	2

Encoding:	| 1 1 1 1 | 0 0 0 0 |

Operation:	MOVX

((DPTR)) <-- (A)

UP


MUL AB

Function: 	Multiply

Description: 	MUL AB multiplies the unsigned eight-bit integers in the Accumulator and register B. The low-order byte of the sixteen-bit product is left in the Accumulator, and the high-order byte in B. If the product is greater than 255 (0FFH) the overflow flag is set; otherwise it is cleared. The carry flag is always cleared.

Example: 	Originally the Accumulator holds the value 80 (50H). Register B holds the value 160 (0A0H). The instruction,

MUL	AB

will give the product 12,800 (3200H), so B is changed to 32H (00110010B) and the Accumulator is cleared. The overflow flag is set, carry is cleared.

Bytes: 	1

Cycles: 	4

Encoding:	| 1 0 1 0 | 0 1 0 0 |

Operation:	MUL

(A)7-0 <-- (A) x (B)

(B)15-8


NOP

Function: 	No Operation

Description: 	Execution continues at the following instruction. Other than the PC, no registers or flags are affected.

Example: 	It is desired to produce a low-going output pulse on bit 7 of Port 2 lasting exactly 5 cycles. A simple SETB/CLR sequence would generate a one-cycle pulse, so four additional cycles must be inserted. This may be done with the instruction sequence,

CLR	P2.7

NOP

NOP

NOP

NOP

SETB	P2.7

Bytes: 	1

Cycles: 	1

Encoding:	| 0 0 0 0 | 0 0 0 0 |

Operation:	NOP

(PC) <-- (PC) + 1


ORL <dest-byte>,<src-byte>

Function: 	Logical-OR for byte variables

Description: 	ORL performs the bitwise logical-OR operation between the indicated variables, storing the results in the destination byte. No flags are affected.

The two operands allow six addressing mode combinations. When the destination is the Accumulator, the source can use register, direct, register-indirect, or immediate addressing; when the destination is a direct address, the source can be the Accumulator or immediate data.

Note:  When this instruction is used to modify an output port, the value used as the original port data will be read from the output data latch, not  the input pins.

Example: 	If the Accumulator holds 0C3H (11000011B) and R0 holds 55H (01010101B) then the instruction,

ORL	A,R0

will leave the Accumulator holding the value 0D7H (11010111B).

When the destination is a directly addressed byte, the instruction can set combinations of bits in any RAM location or hardware register. The pattern of bits to be set is determined by a mask byte, which may be either a constant data value in the instruction or a variable computed in the Accumulator at run-time. The instruction,

ORL	P1,#00110010B

will set bits 5, 4, and 1 of output Port 1.

•	ORL A,Rn

•	ORL A,direct

•	ORL A,@Ri

•	ORL A,#data

•	ORL direct,A

•	ORL direct,#data


ORL A,Rn

Bytes: 	1

Cycles: 	1

Encoding:	| 0 1 0 0 | 1 r r r |

R0 - 48h

R1 - 49h

R2 - 4Ah

R3 - 4Bh

R4 - 4Ch

R5 - 4Dh

R6 - 4Eh

R7 - 4Fh

Operation:	ORL

(A) <-- (A) OR (Rn)

UP


ORL A,direct

Bytes: 	2

Cycles: 	1

Encoding:	| 0 1 0 0 | 0 1 0 1 |  | direct address |

Operation:	ORL

(A) <-- (A) OR (direct)

UP


ORL A,@Ri

Bytes: 	1

Cycles: 	1

Encoding:	| 0 1 0 0 | 0 1 1 i |

R0 - 46h

R1 - 47h

Operation:	ORL

(A) <-- (A) OR ((Ri))

UP


ORL A,#data

Bytes: 	2

Cycles: 	1

Encoding:	| 0 1 0 0 | 0 1 0 0 |  | immediate data |

Operation:	ORL

(A) <-- (A) OR #data

UP


ORL direct,A

Bytes: 	2

Cycles: 	1

Encoding:	| 0 1 0 0 | 0 0 1 0 |  | direct address |

Operation:	ORL

(direct) <-- (direct) OR (A)

UP


ORL direct,#data

Bytes: 	3

Cycles: 	2

Encoding:	| 0 1 0 0 | 0 0 1 1 |  | direct address |  | immediate data |

Operation:	ORL

(direct) <-- (direct) OR #data

UP


ORL C,<src-bit>

Function: 	Logical-OR for bit variables

Description: 	Set the carry flag if the Boolean value is a logical 1; leave the carry in its current state otherwise. A slash ("/") preceding the operand in the assembly language indicates that the logical complement of the addressed bit is used as the source value, but the source bit itself is not affected. No other flags are affected.

Example: 	Set the carry flag if and only if P1.0=1, ACC.7=1, or OV=0

(one of the above is true):

ORL	C,P1.0	;LOAD CARRY WITH INPUT PIN P1.0

ORL	C,ACC.7	;OR CARRY WITH THE ACC. BIT 7

ORL	C,/OV	;OR CARRY WITH THE INVERSE OF OV.

•	ORL C,bit

•	ORL C,/bit


ORL C,bit

Bytes: 	2

Cycles: 	2

Encoding:	| 0 1 1 1 | 0 0 1 0 |  | bit address |

Operation:	ORL

(C) <-- (C) OR (bit)

UP


ORL C,/bit

Bytes: 	2

Cycles: 	2

Encoding:	| 1 0 1 0 | 0 0 0 0 |  | bit address |

Operation:	ORL

(C) <-- (C) OR (/bit)

UP


POP direct

Function: 	Pop from stack

Description: 	The contents of the internal RAM location addressed by the Stack Pointer is read, and the Stack Pointer is decremented by one. The value read is then transferred to the directly addressed byte indicated. No flags are affected.

Example: 	The Stack Pointer originally contains the value 32H, and internal RAM locations 30H through 32H contain the values 20H, 23H, and 01H, respectively. The instruction sequence,

POP	DPH

POP	DPL

will leave the Stack Pointer equal to the value 30H and the Data Pointer set to 0123H. At this point the instruction,

POP	SP

will leave the Stack Pointer set to 20H. Note that in this special case the Stack Pointer was decremented to 2FH before being loaded with the value popped (20H).

Bytes: 	2

Cycles: 	2

Encoding:	| 1 1 0 1 | 0 0 0 0 |  | direct address |

Operation:	POP

(direct) <-- ((SP))

(SP) <-- (SP) - 1


PUSH direct

Function: 	Push onto stack

Description: 	The Stack Pointer is incremented by one. The contents of the indicated variable is then copied into the internal RAM location addressed by the Stack Pointer. Otherwise no flags are affected.

Example: 	On entering an interrupt routine the Stack Pointer contains 09H. The Data Pointer holds the value 0123H. The instruction sequence,

PUSH	DPL

PUSH	DPH

will leave the Stack Pointer set to 0BH and store 23H and 01H in internal RAM locations 0AH and 0BH, respectively.

Bytes: 	2

Cycles: 	2

Encoding:	| 1 1 0 0 | 0 0 0 0 |  | direct address |

Operation:	PUSH

(SP) <-- (SP) + 1

((SP)) <-- (direct)


RET

Function: 	Return from subroutine

Description: 	RET pops the high- and low-order bytes of the PC successively from the stack, decrementing the Stack Pointer by two. Program execution continues at the resulting address, generally the instruction immediately following an ACALL or LCALL. No flags are affected.

Example: 	The Stack Pointer originally contains the value 0BH. Internal RAM locations 0AH and 0BH contain the values 23H and 01H, respectively. The instruction,

RET

will leave the Stack Pointer equal to the value 09H. Program execution will continue at location 0123H.

Bytes: 	1

Cycles: 	2

Encoding:	| 0 0 1 0 | 0 0 1 0 |

Operation:	RET

(PC15-8) <-- ((SP))

(SP) <-- (SP) - 1

(PC7-0) <-- ((SP))

(SP) <-- (SP) - 1


RETI

Function: 	Return from interrupt

Description: 	RETI pops the high- and low-order bytes of the PC successively from the stack, and restores the interrupt logic to accept additional interrupts at the same priority level as the one just processed. The Stack Pointer is left decremented by two. No other registers are affected; the PSW is not automatically restored to its pre-interrupt status. Program execution continues at the resulting address, which is generally the instruction immediately after the point at which the interrupt request was detected. If a lower- or same-level interrupt has been pending when the RETI instruction is executed, that one instruction will be executed before the pending interrupt is processed.

Example: 	The Stack Pointer originally contains the value 0BH. An interrupt was detected during the instruction ending at location 0122H. Internal RAM locations 0AH and 0BH contain the values 23H and 01H, respectively. The instruction,

RETI

will leave the Stack Pointer equal to 09H and return program execution to location 0123H.

Bytes: 	1

Cycles: 	2

Encoding:	| 0 0 1 1 | 0 0 1 0 |

Operation:	RETI

(PC15-8) <-- ((SP))

(SP) <-- (SP) - 1

(PC7-0) <-- ((SP))

(SP) <-- (SP) - 1


RL A

Function: 	Rotate Accumulator Left

Description: 	The eight bits in the Accumulator are rotated one bit to the left. Bit 7 is rotated into the bit 0 position. No flags are affected.

Example: 	The Accumulator holds the value 0C5H (11000101B). The instruction,

RL	A

leaves the Accumulator holding the value 8BH (10001011B) with the carry unaffected.

Bytes: 	1

Cycles: 	1

Encoding:	| 0 0 1 0 | 0 0 1 1 |

Operation:	RL

(An+1) <-- (An), n = 0 - 6

(A0) <-- (A7)


RLC A

Function: 	Rotate Accumulator Left through the Carry flag

Description: 	The eight bits in the Accumulator and the carry flag are together rotated one bit to the left. Bit 7 moves into the carry flag; the original state of the carry flag moves into the bit 0 position. No other flags are affected.

Example: 	The Accumulator holds the value 0C5H (11000101B), and the carry is zero. The instruction,

RLC	A

leaves the Accumulator holding the value 8AH (10001010B) with the carry set.

Bytes: 	1

Cycles: 	1

Encoding:	| 0 0 1 1 | 0 0 1 1 |

Operation:	RLC

(An+1) <-- (An), n = 0 - 6

(A0) <-- (C)

(C) <-- (A7)


RR A

Function: 	Rotate Accumulator Right

Description: 	The eight bits in the Accumulator are rotated one bit to the right. Bit 0 is rotated into the bit 7 position. No flags are affected.

Example: 	The Accumulator holds the value 0C5H (11000101B). The instruction,

RR	A

leaves the Accumulator holding the value 0E2H (11100010B) with the carry unaffected.

Bytes: 	1

Cycles: 	1

Encoding:	| 0 0 0 0 | 0 0 1 1 |

Operation:	RR

(An) <-- (An+1), n = 0 - 6

(A7) <-- (A0)


RRC A

Function: 	Rotate Accumulator Right through the Carry flag

Description: 	The eight bits in the Accumulator and the carry flag are together rotated one bit to the right. Bit 0 moves into the carry flag; the original state of the carry flag moves into the bit 7 position. No other flags are affected.

Example: 	The Accumulator holds the value 0C5H (11000101B), and the carry is zero. The instruction,

RRC	A

leaves the Accumulator holding the value 62H (01100010B) with the carry set.

Bytes: 	1

Cycles: 	1

Encoding:	| 0 0 0 1 | 0 0 1 1 |

Operation:	RRC

(An) <-- (An+1), n = 0 - 6

(A7) <-- (C)

(C) <-- (A0)


SETB <bit>

Function: 	Set Bit

Description: 	SETB sets the indicated bit to one. SETB can operate on the carry flag or any directly addressable bit. No other flags are affected.

Example: 	The carry flag is cleared. Output Port 1 has been written with the value 34H (00110100B). The instructions,

SETB	C

SETB	P1.0

will leave the carry flag set to 1 and change the data output on Port 1 to 35H (00110101B).

•	SETB C

•	SETB bit


SETB C

Bytes: 	1

Cycles: 	1

Encoding:	| 1 1 0 1 | 0 0 1 1 |

Operation:	SETB

(C) <-- 1

UP


SETB bit

Bytes: 	2

Cycles: 	1

Encoding:	| 1 1 0 1 | 0 0 1 0 |  | bit address |

Operation:	SETB

(bit) <-- 1

UP


SJMP rel

Function: 	Short Jump

Description: 	Program control branches unconditionally to the address indicated. The branch destination is computed by adding the signed displacement in the second instruction byte to the PC, after incrementing the PC twice. Therefore, the range of destinations allowed is from 128 bytes preceding this instruction to 127 bytes following it.

Example: 	The label "RELADR" is assigned to an instruction at program memory location 0123H. The instruction,

SJMP 	RELADR

will assemble into location 0100H. After the instruction is executed, the PC will contain the value 0123H.

(Note:  Under the above conditions the instruction following SJMP will be at 102H. Therefore, the displacement byte of the instruction will be the relative offset (0123H - 0102H) = 21H. Put another way, an SJMP with a displacement of 0FEH would be a one-instruction infinite loop.)

Bytes: 	2

Cycles: 	2

Encoding:	| 1 0 0 0 | 0 0 0 0 |  | rel. address |

Operation:	SJMP

(PC) <-- (PC) + 2

(PC) <-- (PC) + rel


SUBB A,<src-byte>

Function: 	Subtract with borrow

Description: 	SUBB subtracts the indicated variable and the carry flag together from the Accumulator, leaving the result in the Accumulator. SUBB sets the carry (borrow) flag if a borrow is needed for bit 7, and clears C otherwise. (If C was set before  executing a SUBB instruction, this indicates that a borrow was needed for the previous step in a multiple precision subtraction, so the carry is subtracted from the Accumulator along with the source operand.) AC is set if a borrow is needed for bit 3, and cleared otherwise. OV is set if a borrow is needed into bit 6, but not into bit 7, or into bit 7, but not bit 6.

When subtracting signed integers OV indicates a negative number produced when a negative value is subtracted from a positive value, or a positive result when a positive number is subtracted from a negative number.

The source operand allows four addressing modes: register, direct, register-indirect, or immediate.

Example: 	The Accumulator holds 0C9H (11001001B), register 2 holds 54H (01010100B), and the carry flag is set. The instruction,

SUBB	A,R2

will leave the value 74H (01110100B) in the Accumulator, with the carry flag and AC cleared but OV set.

Notice that 0C9H minus 54H is 75H. The difference between this  and the above result is due to the carry (borrow) flag being set before the operation. If the state of the carry is not known before starting a single or multiple-precision subtraction, it should be explicitly cleared by a CLR C instruction.

•	SUBB A,Rn

•	SUBB A,direct

•	SUBB A,@Ri

•	SUBB A,#data


SUBB A,Rn

Bytes: 	1

Cycles: 	1

Encoding:	| 1 0 0 1 | 1 r r r |

R0 - 98h

R1 - 99h

R2 - 9Ah

R3 - 9Bh

R4 - 9Ch

R5 - 9Dh

R6 - 9Eh

R7 - 9Fh

Operation:	SUBB

(A) <-- (A) - (C) - (Rn)

UP


SUBB A,direct

Bytes: 	2

Cycles: 	1

Encoding:	| 1 0 0 1 | 0 1 0 1 |  | direct address |

Operation:	SUBB

(A) <-- (A) - (C) - (direct)

UP


SUBB A,@Ri

Bytes: 	1

Cycles: 	1

Encoding:	| 1 0 0 1 | 0 1 1 i |

R0 - 96h

R1 - 97h

Operation:	SUBB

(A) <-- (A) - (C) - ((Ri))

UP


SUBB A,#data

Bytes: 	2

Cycles: 	1

Encoding:	| 1 0 0 1 | 0 1 0 0 |  | immediate data |

Operation:	SUBB

(A) <-- (A) - (C) - (#data)

UP


SWAP A

Function: 	Swap nibbles within the Accumulator

Description: 	SWAP A interchanges the low- and high-order nibbles (four-bit fields) of the Accumulator (bits 3-0 and bits 7-4). The operation can also be thought of as a four-bit rotate instruction. No flags are affected.

Example: 	The Accumulator holds the value 0C5H (11000101B). The instruction,

SWAP A

leaves the Accumulator holding the value 5CH (01011100B).

Bytes: 	1

Cycles: 	1

Encoding:	| 1 1 0 0 | 0 1 0 0 |

Operation:	SWAP

(A3-0) <--> (A7-4)


XCH A,<byte>

Function: 	Exchange Accumulator with byte variable

Description: 	XCH loads the Accumulator with the contents of the indicated variable, at the same time writing the original Accumulator contents to the indicated variable. The source/destination operand can use register, direct, or register-indirect addressing.

Example: 	R0 contains the address 20H. The Accumulator holds the value 3FH (00111111B). Internal RAM location 20H holds the value 75H (01110101B). The instruction,

XCH	A,@R0

will leave the RAM location 20H holding the values 3FH (00111111B) and 75H (01110101B) in the Accumulator.

•	XCH A,Rn

•	XCH A,direct

•	XCH A,@Ri


XCH A,Rn

Bytes: 	1

Cycles: 	1

Encoding:	| 1 1 0 0 | 1 r r r |

R0 - 0C8h

R1 - 0C9h

R2 - 0CAh

R3 - 0CBh

R4 - 0CCh

R5 - 0CDh

R6 - 0CEh

R7 - 0CFh

Operation:	XCH

(A) <--> (Rn)

UP


XCH A,direct

Bytes: 	2

Cycles: 	1

Encoding:	| 1 1 0 0 | 0 1 0 1 |  | direct address |

Operation:	XCH

(A) <--> (direct)

UP


XCH A,@Ri

Bytes: 	1

Cycles: 	1

Encoding:	| 1 1 0 0 | 0 1 1 i |

R0 - 0C6h

R1 - 0C7h

Operation:	XCH

(A) <--> ((Ri))

UP


XCHD A,@Ri

Function: 	Exchange Digit

Description: 	XCHD exchanges the low-order nibble of the Accumulator (bits 3-0), generally representing a hexadecimal or BCD digit, with that of the internal RAM location indirectly addressed by the specified register. The high-order nibbles (bits 7-4) of each register are not affected. No flags are affected.

Example: 	R0 contains the address 20H. The Accumulator holds the value 36H (00110110B). Internal RAM location 20H holds the value 75H (01110101B). The instruction,

XCHD	A,@R0

will leave RAM location 20H holding the value 76H (01110110B) and 35H (00110101B) in the Accumulator.

Bytes: 	1

Cycles: 	1

Encoding:	| 1 1 0 1 | 0 1 1 i |

R0 - 0D6h

R1 - 0D7h

Operation:	XCHD

(A3-0) <--> ((Ri3-0))


XRL <dest-byte>,<src-byte>

Function: 	Logical Exclusive-OR for byte variables

Description: 	XRL performs the bitwise logical Exclusive-OR operation between the indicated variables, storing the results in the destination. No flags are affected.

The two operands allow six addressing mode combinations. When the destination is the Accumulator, the source can use register, direct, register-indirect, or immediate addressing; when the destination is a direct address, the source can be the Accumulator or immediate data.

(Note:  When this instruction is used to modify an output port, the value used as the original port data will be read from the output data latch, not  the input pins.)

Example: 	If the Accumulator holds 0C3H (11000011B) and register 0 holds 0AAH (10101010B) then the instruction,

XRL	A,R0

will leave the Accumulator holding the value 69H (01101001B).

When the destination is a directly addressed byte, this instruction can complement combinations of bits in any RAM location or hardware register. The pattern of bits to be complemented is then determined by a mask byte, either a constant contained in the instruction or a variable computed in the Accumulator at run-time. The instruction,

XRL	P1,#00110001B

will complement bits 5, 4, and 0 of output Port 1.

•	XRL A,Rn

•	XRL A,direct

•	XRL A,@Ri

•	XRL A,#data

•	XRL direct,A

•	XRL direct,#data


XRL A,Rn

Bytes: 	1

Cycles: 	1

Encoding:	| 0 1 1 0 | 1 r r r |

R0 - 68h

R1 - 69h

R2 - 6Ah

R3 - 6Bh

R4 - 6Ch

R5 - 6Dh

R6 - 6Eh

R7 - 6Fh

Operation:	XRL

(A) <-- (A) XOR (Rn)

UP


XRL A,direct

Bytes: 	2

Cycles: 	1

Encoding:	| 0 1 1 0 | 0 1 0 1 |  | direct address |

Operation:	XRL

(A) <-- (A) XOR (direct)

UP


XRL A,@Ri

Bytes: 	1

Cycles: 	1

Encoding:	| 0 1 1 0 | 0 1 1 i |

R0 - 66h

R1 - 67h

Operation:	XRL

(A) <-- (A) XOR ((Ri))

UP


XRL A,#data

Bytes: 	2

Cycles: 	1

Encoding:	| 0 1 1 0 | 0 1 0 0 |  | immediate data |

Operation:	XRL

(A) <-- (A) XOR #data

UP


XRL direct,A

Bytes: 	2

Cycles: 	1

Encoding:	| 0 1 1 0 | 0 0 1 0 |  | direct address |

Operation:	XRL

(direct) <-- (direct) XOR (A)

UP


XRL direct,#data

Bytes: 	3

Cycles: 	2

Encoding:	| 0 1 1 0 | 0 0 1 1 |  | direct address |  | immediate data |

Operation:	XRL

(direct) <-- (direct) XOR #data

UP


FlagSettings
Instructions that Affect Flag Settings

Instruction	Flags:	C	OV	AC

----------------------------------------------------

ADD	X	X	X

ADDC	X	X	X

SUBB	X	X	X

MUL	0	X

DIV	0	X

DA	X

RRC	X

RLC	X

SETB C	1

CLR C	0

CPL C	X

ANL C,bit	X

ANL C,/bit	X

ORL C,bit	X

ORL C,/bit	X

MOV C,bit	X

CJNE	X

----------------------------------------------------

The operations on SFR byte address 208 or bit addresses 209-215 (i.e., the PSW or bits in the PSW) will also affect flag settings.


Addressing Modes

The addressing modes in the 80C51 instruction set are as follows:

Direct Addressing

In direct addressing the operand is specified by an 8-bit address field in the instruction. Only internal Data RAM and SFRs can be directly addressed.

Indirect Addressing

In indirect addressing the instruction specifies a register which contains the address of the operand. Both internal and external RAM can be indirectly addressed.

The address register for 8-bit addresses can be R0 or R1 of the selected bank, or the Stack Pointer. The address register for 16-bit addresses can only be the 16-bit "data pointer" register, DPTR.

Register Instructions

The register banks, containing registers R0 through R7, can be accessed by certain instructions which carry a 3-bit register specification within the opcode of the instruction. Instructions that access the registers this way are code efficient, since this mode eliminates an address byte. When the instruction is executed, one of the eight registers in the selected bank is accessed. One of four banks is selected at execution time by the two bank select bits in the PSW.

Register-Specific Instructions

Some instructions are specific to a certain register. For example, some instructions always operate on the Accumulator, or Data Pointer, etc., so no address byte is needed to point to it. The opcode itself does that. Instructions that refer to the Accumulator as A assemble as accumulator specific opcodes.

Immediate Constants

The value of a constant can follow the opcode in Program Memory. For example,

MOV	A,#100

loads the Accumulator with the decimal number 100. The same number could be specified in hex digits as 64H.

Indexed Addressing

Only Program Memory can be accessed with indexed addressing, and it can only be read. This addressing mode is intended for reading look-up tables in Program Memory. A 16-bit base register (either DPTR or the Program Counter) points to the base of the table, and the Accumulator is set up with the table entry number.

The address of the table entry in Program Memory is formed by adding the Accumulator data to the base pointer.

Another type of indexed addressing is used in the "case jump" instruction. In this case the destination address of a jump instruction is computed as the sum of the base pointer and the Accumulator data.


Reset

Power-on Reset

The reset input is the RST pin, which is the input to a Schmitt Trigger. A reset is accomplished by holding the RST pin high for at least two machine cycles (24 oscillator periods), while the oscillator is running. The CPU responds by generating an internal reset.

The external reset signal is asynchronous to the internal clock. The RST pin is sampled during State 5 Phase 2 of every machine cycle. The port pins will maintain their current activities for 19 oscillator periods after a logic 1 has been sampled at the RST pin; that is, for 19 to 31 oscillator periods after the external reset signal has been applied to the RST pin.

The internal reset algorithm writes 0s to all the SFRs except the port latches, the Stack Pointer, and SBUF. The port latches are initialized to FFh, the Stack Pointer to 07h, and SBUF is indeterminate. The internal RAM is not affected by reset. On power up the RAM content is indeterminate.

REGISTER	RESET VALUE

--------------------------------------------------

PC	0000h

ACC	00h

B	00h

PSW	00h

SP	07h

DPTR	0000h

P0-P3	FFh

IP	XXX00000b

IE	0XX00000b

TMOD	00h

TCON	00h

TH0	00h

TL0	00h

TH1	00h

TL1	00h

SCON	00h

SBUF	Indeterminate

PCON (NMOS)	0XXXXXXXb

PCON (CMOS)	0XXX0000b

--------------------------------------------------


Power-on Reset

An automatic reset can be obtained when Vcc is turned on by connecting the RST pin to Vcc through a 10uF capacitor and to Vss through an 8.2k resistor, providing the Vcc rise time does not exceed 1 millisecond and the oscillator start-up time does not exceed 10 milliseconds. The CMOS devices do not require the 8.2k pulldown resistor, although its presence does no harm.

When power is turned on, the circuit holds the RST pin high for an amount of time that depends on the value of the capacitor and the rate at which it charges. To ensure a good reset, the RST pin must be high long enough to allow the oscillator time to start-up (normally a few ms) plus two machine cycles.

Note that the port pins will be in a random state until the oscillator has started and the internal reset algorithm has written 1s to them.

With this circuit, reducing Vcc quickly to 0 causes the RST pin voltage to momentarily fall below 0V. However, this voltage is internally limited, and will not harm the device.


MemMap
Memory Map of the internal 128 Bytes RAM (direct and indirect addressable)

     ______________________________	_________________

78 |	| 7F

     ______________________________

70 |	| 77

     ______________________________

68 |	| 6F

     ______________________________

60 |	| 67

     ______________________________

58 |	| 5F	SCRATCH PAD

     ______________________________	AREA

50 |	| 57

     ______________________________

48 |	| 4F

     ______________________________

40 |	| 47

     ______________________________

38 |	| 3F

     ______________________________

30 |	| 37

     ______________________________	_________________

28 |	       ... 7F	| 2F

     ______________________________	BIT ADDRESSABLE

20 | 0 ...	| 27	SEGMENT

     ______________________________	_________________

18 |	3	| 1F

     ______________________________

10 |	2	| 17

     ______________________________	REGISTER BANKS

08 |	1	| 0F

     ______________________________

00 |	0	| 07

     ______________________________	_________________

The 128 bytes of RAM which can be accessed by both direct and indirect addressing can be divided into three segments as listed below.

1.	Register Banks 0 - 3: Locations 0 through 1FH (32 bytes). The device after reset defaults to register bank 0. To use the other register banks, the user must select them is software. Each register bank contains eight 1-byte registers 0 through 7. Reset initializes the stack pointer to location 07H, and it is incremented once to start from location 08H, which is the first register (R0) of the second register bank. Thus, in order to use more than one register bank, the SP should be initialized to a different location of the RAM where it is not used for data storage (i.e., the higher part of the RAM).

2.	Bit Addressable Area: 16 bytes have been assigned for this segment, 20H - 2FH. Each one of the 128 bits of this segment can be directly addressed (0 - 7FH). The bits can be referred to in two ways, both of which are acceptable by most assemblers. One way is to refer to their address (i.e., 0 - 7FH). The other way is with reference to bytes 20H to 2FH. Thus, bits 0 - 7 can also be referred to as bits 20.0 - 20.7, and bits 8 - FH are the same as 21.0 - 21.7, and so on. Each of the 16 bytes in this segment can also be addressed as a byte.

3.	Scratch Pad Area: 30H through 7FH are available to the user as data RAM. However, if the stack pointer has been initialized to this area, enough bytes should be left aside to prevent SP data destruction.


ExtMemory
Accessing External Memory

Accesses to external memory are of two types: accesses to external Program Memory and accesses to external Data Memory. Accesses to external Program Memory use signal PSEN\ (program store enable) as the read strobe. Accesses to external Data Memory use RD\ or WR\ (alternate functions of P3.7 and P3.6) to strobe the memory. Fetches from external Program Memory always use a 16-bit address. Accesses to external Data Memory can use either a 16-bit address (MOVX @DPTR) or an 8-bit address (MOVX @Ri).

Whenever a 16-bit address is used, the high byte of the address comes out on Port 2, where it is held for the duration of the read or write cycle. Note that the Port 2 drivers use the strong pullups during the entire time that they are emitting address bits that are 1s. This is during the execution of a MOVX @DPTR instruction. During this time the Port 2 latch (the Special Function Register) does not have to contain 1s, and the contents of the Port 2 SFR are not modified. If the external memory cycle is not immediately followed by another external memory cycle, the undisturbed contents of the Port 2 SFR will reappear in the next cycle.

If an 8-bit address is being used (MOVX @Ri), the contents of the Port 2 SFR remain at the Port 2 pins throughout the external memory cycle. This will facilitate paging.

In any case, the low byte of the address is time-multiplexed with the data byte on Port 0. The ADDR/DATA signals drive both FETs in the Port 0 output buffers. Thus, in this application the Port 0 pins are not open-drain outputs, and do not require external pullups. ALE (Address Latch Enable) should be used to capture the address byte into an external latch. The address byte is valid at the negative transition of ALE. Then, in a write cycle, the data byte to be written appears on Port 0 just before WR\ is activated, and remains there until after WR\ is deactivated. In a read cycle, the incoming byte is accepted at Port 0 just before the read strobe is deactivated.

During any access to external memory, the CPU writes 0FFH to the Port 0 latch (the Special Function Register), thus obliterating whatever information the Port 0 SFR may have been holding.

External Program Memory is accessed under two conditions: Whenever signal EA\ is active; or whenever the program counter (PC) contains a number that is larger than 0FFFH (in the 80C51). This require that the ROMless versions have EA\ wired low to enable the lower 4k program bytes to be fetched from external memory.

When the CPU is executing out of external Program Memory all 8 bits of Port 2 are dedicated to an output function and may not be used for general purpose I/O. During external program fetches they output the high byte of the PC. During this time the Port 2 drivers use the strong pullups to emit PC bits that are 1s.


Interrupts
Interrupts:

General Information about Interrupts

How Interrupts are handled

External Interrupts

Response Time

Single-Step Operation

Simulating a Third Priority Level in Software

To use any of the interrupts in the 80C51 Family, the following three steps must be taken.

1.	Set the EA (enable all) bit in the IE register to 1.

2.	Set the corresponding individual interrupt enable bit in the IE register to 1.

3.	Begin the interrupt service routine at the corresponding Vector Address of that interrupt. See Table below.

Interrupt Source	Vector Address

--------------------------------------------------

IE0	0003H

TF0	000BH

IE1	0013H

TF1	001BH

RI & TI	0023H

--------------------------------------------------

In addition, for external interrupts, pins INT0 and INT1 (P3.2 and P3.3) must be set to 1, and depending on whether the interrupt is to be level or transition activated, bits IT0 or IT1 in the TCON register may need to be set to 1.

ITx = 0	level activated

ITx = 1	transition activated


GeneralInterrupt
Interrupts - General Information

The 80C51 provides 5 interrupt sources. The External Interrupts INT0\ and INT1\ can each be either level-activated or transition-activated, depending on bits IT0 and IT1 in Register TCON. The flags that actually generate these interrupts are bits IE0 and IE1 in TCON. When an external interrupt is generated, the flag that generated it is cleared by the hardware when the service routine is vectored to only if the interrupt was transition-activated. If the interrupt was level-activated, then the external requesting source is what controls the request flag, rather than the on-chip hardware.

The Timer 0 and Timer 1 Interrupts are generated by TF0 and TF1, which are set by a rollover in their respective Timer/Counter registers (except see Timer 0 in Mode 3). When a timer interrupt is generated, the flag that generated it is cleared by the on-chip hardware when the service routine is vectored to.

The Serial Port Interrupt is generated by the logical OR of RI and TI. Neither of these flags is cleared by hardware when the service routine is vectored to. In fact, the service routine will normally have to determine whether it was RI or TI that generated the interrupt, and the bit will have to be cleared in software.

All of the bits that generate interrupts can be set or cleared by software, with the same result as though it had been set or cleared by hardware. That is, interrupts can be generated or pending interrupts can be canceled in software.

Each of these interrupt sources can be individually enabled or disabled by setting or clearing a bit in Special Function Register IE. IE also contains a global disable bit, EA, which disables all interrupts at once.


GeneralHandle
How Interrupts are handled

The interrupt flags are sampled at S5P2 of every machine cycle. The samples are polled during the following machine cycle. If one of the flags was in a set condition at S5P2 of the preceding cycle, the polling cycle will find it and the interrupt system will generate an LCALL to the appropriate service routine, provided this hardware-generated LCALL is not blocked by any of the following conditions:

1.	An interrupt of equal or higher priority level is already in progress.

2.	The current (polling) cycle is not the final cycle in the execution of the instruction in progress.

3.	The instruction in progress is RETI or any write to the IE or IP registers.

Any of these three conditions will block the generation of the LCALL to the interrupt service routine. Condition 2 ensures that the instruction in progress will be completed before vectoring to any service routine. Condition 3 ensures that if the instruction in progress is RETI or any access to IE or IP, then at least one more instruction will be executed before any interrupt is vectored to.

The polling cycle is repeated with each machine cycle, and the values polled are the values that were present at S5P2 of the previous machine cycle. Note that if an interrupt flag is active but not being responded to for one of the above conditions, if the flag is not still active when the blocking condition is removed, the denied interrupt will not be serviced. In other words, the fact that the interrupt flag was once active but not serviced is not remembered. Every polling cycle is new.

The processor acknowledges an interrupt request by executing a hardware-generated LCALL to the appropriate servicing routine. In some cases it also clears the flag that generated the interrupt, and in other cases it doesn't. It never clears the Serial Port flag. This has to be done in the user's software. It clears an external interrupt flag (IE0 or IE1) only if it was transition-activated. The hardware-generated LCALL pushes the contents of the Program Counter onto the Stack (but it does not save the PSW) and reloads the PC with an address that depends on the source of the interrupt being vectored to. Execution proceeds from that location until the RETI instruction is encountered. The RETI instruction informs the processor that this interrupt routine is no longer in progress, then pops the top two bytes from the stack and reloads the Program Counter. Execution of the interrupted program continues from where it left off.

Note that a simple RET instruction would also have returned execution to the interrupted program, but it would have left the interrupt control system thinking an interrupt was still in progress, making future interrupts impossible.


Machine Cycles
A machine cycle consists of a sequence of 6 states, numbered S1 through S6. Each state time lasts for two oscillator periods. Thus a machine cycle takes 12 oscillator periods or 1us if the oscillator frequency is 12MHz.

Each state is divided into a Phase 1 half and a Phase 2 half. Normally two program fetches are generated during each machine cycle, even if the instruction being executed doesn't require it. If the instruction being executed doesn't need more code bytes, the CPU simply ignores the extra fetch, and the Program Counter is not incremented.

Execution of a one-cycle instruction begins during State 1 of the machine cycle, when the opcode is latched into the Instruction Register. A second fetch occurs during S4 of the same machine cycle. Execution is complete at the end of State 6 of this machine cycle.

The MOVX instructions take two machine cycles to execute. No program fetch is generated during the second cycle of a MOVX instruction. This is the only time program fetches are skipped.

The fetch/execute sequences are the same whether the Program Memory is internal or external.

If Program Memory is external, then the Program Memory read strobe PSEN\ is normally activated twice per machine cycle. If an access to external Data Memory occurs two PSEN\s are skipped, because the address and data bus are being used for the Data Memory access.

When the CPU is executing from internal Program Memory, PSEN\ is not activated, and program addresses are not emitted. However, ALE continues to be activated twice per machine cycle and so it is available as a clock output signal. Note, however, that one ALE is skipped during the execution of the MOVX instruction.


GeneralExternal
External Interrupts

The external sources can be programmed to be level-activated or transition-activated by setting or clearing bit IT1 or IT0 in Register TCON. If ITx=0, external interrupt x is triggered by a detected low at the INTx pin. If ITx=1, external interrupt x  is edge triggered. In this mode if successive samples of the INTx pin show a high in one cycle and a low in the next cycle, interrupt request flag IEx in TCON is set. Flag bit IEx then requests the interrupt.

Since the external interrupt pins are sampled once each machine cycle, an input high or low should hold for at least 12 oscillator periods to ensure sampling. If the external interrupt is transition-activated, the external source has to hold the request pin high for at least one cycle, and then hold it low for at least one cycle. This is done to ensure that the transition is seen so that interrupt request flag IEx will be set. IEx will be automatically cleared by the CPU when the service routine is called.

If the external interrupt is level-activated, the external source has to hold the request active until the requested interrupt is actually generated. Then it has to deactivate the request before the interrupt service routine is completed, or else another interrupt will be generated.


GeneralResponse
Response Time of External Interrupts

The INT0\ and INT1\ levels are inverted and latched into IE0 and IE1 at S5P2 of every machine cycle. The values are not actually polled by the circuitry until the next machine cycle. If a request is active and conditions are right for it to be acknowledged, a hardware subroutine call to the requested service routine will be the next instruction to be executed. The call itself takes two cycles. Thus a minimum of three complete machine cycles elapse between activation of an external interrupt request and the beginning of execution of the first instruction of the service routine.

A longer response time would result if the request is blocked by one of the 3 blocking conditions. If an interrupt of equal or higher priority level is already in progress, the additional wait time obviously depends on the nature of the other interrupt's service routine. If the instruction in progress is not in its final cycle, the additional wait time cannot be more the 3 cycles, since the longest instructions (MUL and DIV) are only 4 cycles long, and if the instruction in progress is RETI or an access to IE or IP, the additional wait time cannot be more than 5 cycles (a maximum of one more cycle to complete the instruction in progress, plus 4 cycles to complete the next instruction if the instruction is MUL or DIV).

Thus, in a single-interrupt system, the response time is always more than 3 cycles and less than 9 cycles.


SingleStep
Single-Step Operation

The 80C51 interrupt structure allows single-step execution with very little software overhead. An interrupt request will not be responded to while an interrupt of equal priority level is still in progress, nor will it be responded to after RETI until at least one other instruction has been executed. Thus, once an interrupt routine has been entered, it cannot be re-entered until at least one instruction of the interrupted program is executed. One way to use this feature for single-step operation is to program one of the external interrupts (e.g., INT0\) to be level activated. The service routine for the interrupt will terminate with the following code:

JNB	P3.2,$	;Wait Till INT0\ Goes High

JB	P3.2,$	;Wait Till INT0\ Goes Low

RETI	;Go Back and Execute One Instruction

Now if the INT0\ pin, which is also the P3.2 pin, is held normally low, the CPU will go right into the External Interrupt 0 routine and stay there until INT0\ is pulsed (from low to high to low). Then it will execute RETI, go back to the task program, execute one instruction, and immediately re-enter the External Interrupt 0 routine to await the next pulsing of P3.2. One step of the task program is executed each time P3.2 is pulsed.


ThirdPriority
Simulating a Third Priority Level in Software

Some applications require more than two priority levels that are provided by on-chip hardware in 80C51 devices. In these cases, relatively simple software can be written to produce the same effect as a third priority level. First, interrupts that are to have higher priority then 1 are assigned to priority 1 in the Interrupt Priority (IP) register. The service routines for priority 1 interrupts that are supposed to be interruptable by priority 2 interrupts are written to include the following code:

PUSH	IE

MOV	IE,#MASK

CALL	LABEL

*****************************

(execute service routine)

*****************************

POP	IE

RET

LABEL:	RETI

As soon as any priority interrupt is acknowledged, the Interrupt Enable (IE) register is redefined so as to disable all but priority 2 interrupts. Then a CALL to LABEL executes the RETI instruction, which clears the priority 1 interrupt-in-progress flip-flop. At this point any priority 1 interrupt that is enabled can be serviced, but only priority 2 interrupts are enabled.

POPing IE restores the original enable byte.Then a normal RET (rather than another RETI) is used to terminate the service routine. The additional software adds 10us (at 12MHz) to priority 1 interrupts.


Interrupt Priority

General Information about Priority Level Structure of Interrupts

In order to assign higher priority to an interrupt the corresponding bit in the IP register must be set to 1.

Remember that while an interrupt service is in progress, it cannot be interrupted by a lower or same level interrupt.

Priority within level:

Priority within level is only to resolve simultaneous requests of the same priority level. From high to low, interrupt sources are listed below:

IE0	highest priority

TF0

IE1

TF1

RI or TI	lowest priority


GeneralPriority
Priority Level Structure of Interrupts - General Information

Each interrupt source can also be individually programmed to one of two priority levels by setting or clearing a bit in Special Function Register IP. A low-priority interrupt can itself be interrupted by a high-priority interrupt, but not by another low-priority interrupt. A high-priority interrupt can't be interrupted by any other interrupt source.

If two requests of different priority levels are received simultaneously, the request of higher priority level is serviced. If requests of the same priority level are received simultaneously, an internal polling sequence determines which request is serviced. Thus within each priority level there is a second priority structure determined by the polling sequence. Note that the "priority within level" structure is only used to resolve simultaneous requests of the same priority level.

The IP register contains a number of unimplemented bits. IP.7, IP.6, and IP.5 are reserved in the 80C51. User software should not write 1s to these positions, since they may be used in other 8051 Family products.


Timer Set-Up

General Information about the Timer/Counters

The tables below give some values for TMOD which can be used to set up Timer 0 and Timer 1 in different modes.

It is assumed that only one timer is being used at a time. If it is desired to run Timers 0 and 1 simultaneously, in any mode, the value in TMOD for Timer 0 must be ORed with the value shown for Timer 1.

For example, if it is desired to run Timer 0 in mode 1 GATE (external control), and Timer 1 in mode 2 COUNTER, then the value that must be loaded into TMOD is 69H (09H from the table for Timer 0, ORed with 60H from the table for Timer 1).

Moreover, it is assumed that the user, at this point, is not ready to turn the timers on and will do that at a different point in the program by setting bit TRx (in TCON) to 1.

TIMER/COUNTER 0

As a Timer:

Mode	Function	TMOD(internal control)	TMOD(external control)

___________________________________________________________________

0	13-bit Timer	00h	08h

1	16-bit Timer	01h	09h

2	8-bit Auto-Reload	02h	0Ah

3	Two 8-bit Timers	03h	0Bh

___________________________________________________________________

As a Counter:

Mode	Function	TMOD(internal control)	TMOD(external control)

___________________________________________________________________

0	13-bit Counter	04h	0Ch

1	16-bit Counter	05h	0Dh

2	8-bit Auto-Reload	06h	0Eh

3	One 8-bit Counter	07h	0Fh

___________________________________________________________________

TIMER/COUNTER 1

As a Timer:

Mode	Function	TMOD(internal control)	TMOD(external control)

___________________________________________________________________

0	13-bit Timer	00h	80h

1	16-bit Timer	10h	90h

2	8-bit Auto-Reload	20h	A0h

3	Does not run	30h	B0h

___________________________________________________________________

As a Counter:

Mode	Function	TMOD(internal control)	TMOD(external control)

___________________________________________________________________

0	13-bit Counter	40h	C0h

1	16-bit Counter	50h	D0h

2	8-bit Auto-Reload	60h	E0h

3	Not available	 -	 -

___________________________________________________________________


Timer0Internal
The timer is turned ON/OFF by setting/clearing bit TR0 in the software.


Timer0External
The Timer is turned ON/OFF by the 1-to-0 transition on INT0\ (P3.2) when TR0=1 (hardware control)


Timer1Internal
The timer is turned ON/OFF by setting/clearing bit TR1 in the software.


Timer1External
The Timer is turned ON/OFF by the 1-to-0 transition on INT1\ (P3.3) when TR1=1 (hardware control).


GeneralTimer
Timer/Counters - General Information

The 80C51 has two 16-bit Timer/Counter registers: Timer 0 and Timer 1. Both can be configured to operate either as timers or event counters.

In the "Timer" function, the register is incremented every machine cycle. Thus, one can think of it as counting machine cycles. Since a machine cycle consists of 12 oscillator periods, the count rate is 1/12 of the oscillator frequency.

In the "Counter" function, the register is incremented in response to a 1-to-0 transition at its corresponding external input pin, T0 or T1. In this function, the external input is sampled during S5P2 of every machine cycle.

When the samples show a high in one cycle and low in the next cycle, the count is incremented. The new count value appears in the register during S3P1 of the cycle following the one in which the transition was detected. Since it takes 2 machine cycles (24 oscillator periods) to recognize a 1-to-0 transition, the maximum count rate is 1/24 of the oscillator frequency. There are no restrictions on the duty cycle of the external input signal, but to ensure that a given level is sampled at least once before it changes, it should be held for at least one full cycle. In addition to the "Timer" or "Counter" selection, Timer 0 and Timer 1 have four operating modes from which to select.

Timer 0 and Timer 1

The "Timer" or "Counter" function is selected by control bits C/T in the Special Function Register TMOD. These two Timer/Counters have four operating modes, which are selected by bit-pairs (M1,M0) in TMOD. Modes 0, 1, and 2 are the same for both Timers/Counters. Mode 3 is different. The four operating modes are described in the following text.

Mode 0

Putting either Timer into Mode 0 makes it look like an 8048 Timer, which is an 8-bit Counter with a divide-by-32 prescaler.

In this mode, the Timer register is cofigured as a 13-bit register. As the count rolls over from all 1s to all 0s, it sets the Timer interrupt flag TFx. The counted input is enabled to the Timer when TRx=1 and either GATE=0 or INTx\=1. (Setting GATE=1 allows the Timer to be controlled by external input INTx\, to facilitate pulse width measurements). TRx is a control bit in the Special Function Register TCON. GATE is in TMOD.

The 13-bit register consists of all 8 bits of THx and the lower 5 bits of TLx. The upper 3 bits of TLx are indeterminate and should be ignored. Setting the run flag (TRx) does not clear the registers.

Mode 0 operation is the same for the Timer 0 as for Timer 1. There are two different GATE bits, one for Timer 1 (TMOD.7) and one for Timer 0 (TMOD.3).

Mode 1

Mode 1 is the same as Mode 0, except that the Timer register is being run with all 16 bits.

Mode 2

Mode 2 configures the Timer register as an 8-bit Counter (TLx) with automatic reload. Overflow from TLx not only sets TFx, but also reloads TLx with the contents of THx, which is preset by software. The reload leaves THx unchanged.

Mode 2 operation is the same for both Timer/Counters.

Mode 3

Timer 1 in Mode 3 simply holds its count. The effect is the same as setting TR1=0.

Timer 0 in Mode 3 establishes TL0 and TH0 as two separate counters. TL0 uses the Timer 0 control bits: C/T, GATE, TR0, INT0, and TF0. TH0 is locked into a timer function (counting machine cycles) and takes over the use of TR1 and TF1 from Timer 1. Thus, TH0 now controls the "Timer 1" interrupt.

Mode 3 is provided for applications requiring an extra 8-bit timer on the counter. With Timer 0 in Mode 3, an 80C51 can look like it has three Timer/Counters. When Timer 0 is in Mode 3, Timer 1 can be turned on and off by switching it out of and into its own Mode 3, or can still be used by the serial port as a baud rate generator, or in fact, in any application not requiring an interrupt.


Serial Port Set-Up

The serial port is full duplex, meaning it can transmit and receive simultaneously. It is also receive-buffered, meaning it can commence reception of a second byte before a previously received byte has been read from the register. (However, if the first byte still hasn't been read by the time reception of the second byte is complete, one of the bytes will be lost.) The serial port receive and transmit registers are both accessed at Special Function Register SBUF. Writing to SBUF loads the transmit register, and reading SBUF accesses a physically separate receive register.

The serial port can operate in 4 modes:

Mode 0: Serial data enters and exits through RxD. TxD outputs the shift clock. 8 bits are transmitted/received (LSB first). The baud rate is fixed at 1/12 the oscillator frequency. More About Mode 0

Mode 1: 10 bits are transmitted (through TxD) or received (through RxD): a start bit (0), 8 data bits (LSB first), and a stop bit (1). On receive, the stop bit goes into RB8 in Special Function Register SCON. The baud rate is variable. More About Mode 1

Mode 2: 11 bits are transmitted (through TxD) or received (through RxD): start bit (0), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit (1). On Transmit, the 9th data bit (TB8 in SCON) can be assigned the value of 0 or 1. Or, for example, the parity bit (P, in the PSW) could be moved into TB8. On receive, the 9th data bit goes into RB8 in Special Function Register SCON, while the stop bit is ignored. The baud rate is programmable to either 1/32 or 1/64 the oscillator frequency. More About Modes 2 and 3

Mode 3: 11 bits are transmitted (through TxD) or received (through RxD): a start bit (0), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit (1). In fact, Mode 3 is the same as Mode 2 in all aspects except baud rate. The baud rate in Mode 3 is variable. More About Modes 2 and 3

Timer 1 Generated Commonly Used Baud Rates

The values for the different modes of operation of the serial port are shown in the table below:

MODE	SCON	SM2 Variation

_______________________________________

0	10H	Single Processor

1	50H	Environment

2	90H	(SM2 = 0)

3	D0H

_______________________________________

0	Not Available	Multiprocessor

1	70H	Environment

2	B0H	(SM2 = 1)

3	F0H

_______________________________________

GENERATING BAUD RATES

Serial Port in Mode 0:

Mode 0 has a fixed baud rate which is 1/12 of the oscillator frequency. To run the serial port in this mode none of the Timer/Counters need to be set up. Only the SCON register needs to be defined.

Baud Rate = Osc.Freq / 12

Serial Port in Mode 1:

Mode 1 has a variable baud rate. The baud rate is generated by Timer 1.

For this purpose, Timer 1 is used in mode 2 (Auto-Reload).

Baud Rate = (K x Osc.Freq) / (32 x 12 x [256 - (TH1)])

If SMOD = 0, then K = 1.

If SMOD = 1, then K = 2 (SMOD is in the PCON register).

Most of the time the user knows the baud rate and needs to know the reload value for TH1.

TH1 = 256 - (K x Osc.Freq) / (384 x baud rate)

TH1 must be an integer value. Rounding off TH1 to the nearest integer may not produce the desired baud rate. In this case, the user may have to choose another crystal frequency.

Since the PCON register is not bit addressable, one way to set the bit is logical ORing the PCON register (i.e., ORL PCON,#80H). The address of PCON is 87H.

Serial Port in Mode 2:

The baud rate is fixed in this mode and is 1/32 or 1/64 of the oscillator frequency, depending on the value of the SMOD bit in the PCON register.

In this mode none of the Timers are used and the clock comes from the internal phase 2 clock.

SMOD = 1, Baud Rate = 1/32 Osc.Freq.

SMOD = 0, Baud Rate = 1/64 Osc.Freq.

To set the SMOD bit: ORL PCON,#80H. The address of PCON is 87H.

Serial Port in Mode 3:

The baud rate in mode 3 is variable and sets up exactly the same as in mode 1.


SerialMode0
Serial Port Mode 0

Serial data enters and exits through RxD. TxD outputs the shift clock. 8 bits are transmitted/received: 8 data bits (LSB first). The baud rate is fixed at 1/12 the oscillator frequency.

Transmission is initiated by any instruction that uses SBUF as a destination register. The "write to SBUF" signal at S6P2 also loads a 1 into the 9th position of the transmit shift register and tells the TX Control block to commence a transmission. The internal timing is such that one full machine cycle will elapse between "write to SBUF" and activation of SEND.

SEND enables the output of the shift register to the alternate output function line of P3.0 and also enable SHIFT CLOCK to the alternate output function line of P3.1. SHIFT CLOCK is low during S3, S4, and S5 of every machine cycle, and high during S6, S1, and S2. At S6P2 of every machine cycle in which SEND is active, the contents of the transmit shift are shifted to the right one position.

As data bits shift out to the right, zeros come in from the left. When the MSB of the data byte is at the output position of the shift register, then the 1 that was initially loaded into the 9th position, is just to the left of the MSB, and all positions to the left of that contain zeros. This condition flags the TX Control block to do one last shift and then deactivate SEND and set TI. Both of these actions occur at S1P1 of the 10th machine cycle after "write to SBUF".

Reception is initiated by the condition REN=1 and RI=0. At S6P2 of the next machine cycle, the RX Control unit writes the bits 11111110 to the receive shift register, and in the next clock phase activates RECEIVE.

RECEIVE enable SHIFT CLOCK to the alternate output function line of P3.1. SHIFT CLOCK makes transitions at S3P1 and S6P1 of every machine cycle. At S6P2 of every machine cycle in which RECEIVE is active, the contents of the receive shift register are shifted to the left one position. The value that comes in from the right is the value that was sampled at the P3.0 pin at S5P2 of the same machine cycle.

As data bits come in from the right, 1s shift out to the left. When the 0 that was initially loaded into the rightmost position arrives at the leftmost position in the shift register, it flags the RX Control block to do one last shift and load SBUF. At S1P1 of the 10th machine cycle after the write to SCON that cleared RI, RECEIVE is cleared and RI is set.


SerialMode1
Serial Port Mode 1

Ten bits are transmitted (through TxD), or received (through RxD): a start bit (0), 8 data bits (LSB first), and a stop bit (1). On receive, the stop bit goes into RB8 in SCON. In the 80C51 the baud rate is determined by the Timer 1 overflow rate.

Transmission is initiated by any instruction that uses SBUF as a destination register. The "write to SBUF" signal also loads a 1 into the 9th bit position of the transmit shift register and flags the TX Control unit that a transmission is requested. Transmission actually commences at S1P1 of the machine cycle following the next rollover in the divide-by-16 counter. (Thus, the bit times are synchronized to the divide-by-16 counter, not to the "write to SBUF" signal.)

The transmission begins with activation of SEND which puts the start bit at TxD. The first shift pulse occurs one bit time after that.

As data bits shift out to the right, zeros are clocked in from the left. When the MSB of the data byte is at the output position of the shift register, then the 1 that was initially loaded into the 9th position is just to the left of the MSB, and all positions to the left of that contain zeros. This condition flags the TX Control unit to do one last shift and then deactivate SEND and set TI. This occurs at the 10th divide-by-16 rollover after "write to SBUF".

Reception is initiated by a detected 1-to-0 transition at RxD. For this purpose RxD is sampled at a rate of 16 times whatever baud rate has been established. When a transition is detected, the divide-by-16 counter is immediately reset, and 1FFH is written into the input shift register. Resetting the divide-by-16 counter aligns its rollovers with the boundaries of the incoming bit times. The 16 states of the counter divide each bit time into 16ths. At the 7th, 8th, and 9th counter states of each bit time, the bit detector samples the value of RxD. The value accepted is the value that was seen in at least 2 of the 3 samples. This is done for noise rejection. If the value accepted during the first bit time is not 0, the receive circuits are reset and the unit goes back to looking for another 1-to-0 transition. This is to provide rejection of false start bits. If the start bit proves valid, it is shifted into the input shift register, and reception of the rest of the frame will proceed.

As data bits come in from the right, 1s shift out to the left. When the start bit arrives at the leftmost position in the shift register (which in mode 1 is a 9-bit register), it flags the RX Control block to do one last shift, load SBUF and RB8, and set RI. The signal to load SBUF and RB8, and to set RI, will be generated if, and only if, the following conditions are met at the time the final shift pulse is generated:

1.	RI = 0, and

2.	Either SM2 = 0, or the received stop bit = 1.

If either of these two conditions is not met, the received frame is irretrievably lost. If both conditions are met, the stop bit goes into RB8, the 8 data bits go into SBUF, and RI is activated. At this time, whether the above conditions are met or not, the unit goes back to looking for a 1-to-0 transition in RxD.


SerialMode2&3
Serial Port Mode 2 & 3

Eleven bits are transmitted (through TxD), or received (through RxD): a start bit (0), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit (1). On transmit, the 9th data bit (TB8) can be assigned the value of 0 or 1. On receive, the 9th data bit goes into RB8 in SCON. The baud rate is programmable to either 1/32 or 1/64 the oscillator frequency in Mode 2. Mode 3 may have a variable baud rate generated from Timer 1.

Transmission is initiated by any instruction that uses SBUF as a destination register. The "write to SBUF" signal also loads TB8 into the 9th bit position of the transmit shift register, and flags the TX Control unit that a transmission is requested. Transmission commences at S1P1 of the machine cycle following the next rollover in the divide-by-16 counter. (Thus the bit times are synchronized to the divide-by-16 counter, not to the "write to SBUF" signal.)

The transmission begins with activation of SEND, which puts the start bit at TxD. One bit time later, DATA is activated, which enables the output bit of the transmit shift register to TxD. The first shift pulse occurs one bit time after that. The first shift clocks a 1 (the stop bit) into the 9th bit position of the shift register. Thereafter, only zeros are clocked in. Thus, as data bits shift out to the right, zeros are clocked in from the left. When TB8 is at the output position of the shift register, then the stop bit is just to the left of TB8, and all positions to the left of that contain zeros. This condition flags the TX Control unit to do one last shift and then deactivate SEND and set TI. This occurs at the 11th divide-by-16 rollover after "write to SBUF".

Reception is initiated by a detected 1-to-0 transition at RxD. For this purpose RxD is sampled at a rate of 16 times whatever baud rate has been established. When a transition is detected, the divide-by-16 counter is immediately reset, and 1FFH is written to the input shift register.

At the 7th, 8th, and 9th counter states of each bit time, the bit detector samples the value of RxD. The value accepted is the value that was seen in at least 2 of the 3 samples. If the value accepted during the first bit time is not 0, the receive circuits are reset and the unit goes back to looking for another 1-to-0 transition. If the start bit proves valid, it is shifted into the input shift register, and reception of the rest of the frame will proceed.

As data bits come in from the right, 1s shift out to the left. When the start bit arrives at the leftmost position in the shift register (which in Modes 2 and 3 is a 9-bit register), it flags the RX Control block to do one last shift, load SBUF and RB8, and set RI.

The signal to load SBUF and RB8, and to set RI, will be generated if, and only if, the following conditions are met at the time the final shift pulse is generated.

RI = 0, and

Either SM2 = 0 or the received 9th data bit = 1.

If either of these conditions is not met, the received frame is irretrievably lost, and RI is not set. If both conditions are met, the received 9th data bit goes into RB8, and the first 8 data bits go into SBUF. One bit time later, whetever the above conditions were met or not, the unit goes back to looking for a 1-to-0 transition at the RxD input.


MultiprocessorMode
Multiprocessor Communications: Modes 2 and 3 have a special provision for multiprocessor communications. In these modes, 9 data bits are received. The 9th one goes into RB8. Then comes a stop bit. The port can be programmed such that when the stop bit is received, the serial port interrupt will be activated only if RB8=1. This feature is enabled by setting bit SM2 in SCON. A way to use this feature in multiprocessor systems is as follows:

When the master processor wants to transmit a block of data to one of several slaves, it first sends out an address byte which identifies the target slave. An address byte differs from a data byte in that the 9th bit is 1 in an address byte and 0 in a data byte. With SM2=1, no slave will be interrupted by a data byte. An address byte, however, will interrupt all slaves, so that each slave can examine the received byte and see if it is being addressed. The addressed slave will clear its SM2 bit and preparate to receive the data bytes that will be coming. The slaves that weren't being addressed leave their SM2s set and go on about their business, ignoring the coming data bytes.

SM2 has no effect in Mode 0, and in Mode 1 can be used to check the validity of the stop bit. In a Mode 1 reception, if SM2=1, the receive interrupt will not be activated unless a valid stop bit is received.


SerialBaud
Timer 1 Generated Commonly Used Baud Rates

Timer 1

________________________

Baud Rate	Fosc	SMOD	C/T\	Mode	Reload Value

___________________________________________________________

Mode 0 Max:1.67MHz	20MHz	   X	   X	   X	   X

Mode 2 Max:625k	20MHz	   1	   X	   X	   X

Mode 1,3 Max:104.2k	20MHz	   1	   0	   2	   FFh

19.2k	11.059	   1	   0	   2	   FDh

9.6k	11.059	   0	   0	   2	   FDh

4.8k	11.059	   0	   0	   2	   FAh

2.4k	11.059	   0	   0	   2	   F4h

1.2k	11.059	   0	   0	   2	   E8h

137.5	11.986	   0	   0	   2	   1Dh

110	6MHz	   0	   0	   2	   72h

110	12MHz	   0	   0	   1	   FEEBh

___________________________________________________________


8051 SFR's

Symbol	Description	Addr.	Bit Addressable?	Reset Value

____________________________________________________________________

ACC	Accumulator	E0h	Yes (Function)	00h

B	B register	F0h	Yes (Function)	00h

DPTR	Data Pointer

   DPH	Data Pointer high	83h	00h

   DPL	Data Pointer low	82h	00h

IE	Interrupt enable	A8h	Yes (Function)	0x000000B

IP	Interrupt priority	B8h	Yes (Function)	xx000000B

P0	Port 0	80h	Yes (Function)	FFh

P1	Port 1	90h	Yes (Function)	FFh

P2	Port 2	A0h	Yes (Function)	FFh

P3	Port 3	B0h	Yes (Function)	FFh

PCON	Power control	87h	       (Function)	0xxxxxxxB

PSW	Pgm status word	D0h	Yes (Function)	00h

SBUF	Serial data buffer	99h	xxxxxxxxB

SCON	Serial controller	98h	Yes (Function)	00h

SP	Stack pointer	81h	07h

TCON	Timer control	88h	Yes (Function)

TH0	Timer high 0	8Ch	00h

TH1	Timer high 1	8Dh	00h

TL0	Timer low 0	8Ah	00h

TL1	Timer low 1	8Bh	00h

TMOD	Timer mode	89h	       (Function)	00h

____________________________________________________________________


ACCBits
MSB	LSB

E7	E6	E5	E4	E3	E2	E1	E0


BBits
MSB	LSB

F7	F6	F5	F4	F3	F2	F1	F0


IEBits
MSB	LSB

AF	AE	AD	AC	AB	AA	A9	A8

_______________________________________________________

| EA	| -	| -	| ES	| ET1	| EX1	| ET0	| EX0 	|


IPBits
MSB	LSB

BF	BE	BD	BC	BB	BA	B9	B8

_______________________________________________________

| -	| -	| -	| PS	| PT1	| PX1	| PT0	| PX0	|


P0Bits
MSB	LSB

87	86	85	84	83	82	81	80

_______________________________________________________

| AD7	| AD6	| AD5	| AD4	| AD3	| AD2	| AD1	| AD0	|


P1Bits
MSB	LSB

97	96	95	94	93	92	91	90

_______________________________________________________

| -	| -	| -	| -	| -	| -	| T2EX	| T2	|


P2Bits
MSB	LSB

A7	A6	A5	A4	A3	A2	A1	A0

_______________________________________________________

| A15	| A14	| A13	| A12	| A11	| A10	| A9	| A8	|


P3Bits
MSB	LSB

B7	B6	B5	B4	B3	B2	B1	B0

_______________________________________________________

| /RD	| /WR	| T1	| T0	| /INT1	| /INT0	| TxD	| RxD	|


PCONBits
MSB	LSB

_______________________________________________________

| SMOD| -	| -	| -	| GF1	| GF0	| PD	| IDL	|

Bits GF1, GF0, PD, and IDL of the PCON register are not implemented on the NMOS 8051/8031.


PSWBits
MSB	LSB

D7	D6	D5	D4	D3	D2	D1	D0

_______________________________________________________

| CY	| AC	| F0	| RS1	| RS0	| OV	| -	| P	|


SCONBits
MSB	LSB

9F	9E	9D	9C	9B	9A	99	98

_______________________________________________________

| SM0	| SM1	| SM2	| REN	| TB8	| RB8	| TI	| RI	|


TCONBits
MSB	LSB

8F	8E	8D	8C	8B	8A	89	88

_______________________________________________________

| TF1	| TR1	| TF0	| TR0	| IE1	| IT1	| IE0	| IT0	|


TMOD
MSB	LSB

_______________________________________________________

| GATE	| C/T\	| M1	| M0	| GATE	| C/T\	| M1	| M0	|


SFR's functions
Funstions of the SFRs

Those SFRs that have their bits assigned for various functions are listed below. A brief description of each bit is provided for quick reference.

Note that in the SFRs not all of the addresses are occupied. Unoccupied addresses are not implemented on the chip. Read accesses to these addresses will in general return random data, and write accesses will have no effect.

User software should not write 1s to these unimplemented locations, since they may be used in other 80C51 Family derivative products to invoke new features.

•	PSW: Program Status Word

•	PCON: Power Control Register

•	IE: Interrupt Enable Register

•	IP: Interrupt Priority Register

•	TCON: Timer/Counter Control Register

•	TMOD: Timer/Counter Mode Control Register

•	SCON: Serial Port Control Register

Other Special Function Registers:

•	Accumulator

•	B Register

•	Stack Pointer

•	Data Pointer

•	Ports 0 to 3

•	Serial Data Buffer

•	Timer Registers Basic to 80C51


PSWdescription
PSW: Program Status Word. Bit Addressable.

________________________________________________

| CY	| AC	| F0	| RS1	| RS0	| OV	| -	| P	|

-----------------------------------------------------------------------------

CY	PSW.7	Carry Flag

AC	PSW.6	Auxiliary Carry Flag

F0	PSW.5	Flag 0 available to the user for general purpose.

RS1	PSW.4	Register Bank selector bit 1.

RS0	PSW.3	Register Bank selector bit 0.

OV	PSW.2	Overflow Flag.

-	PSW.1	Usable as a general purpose flag.

P	PSW.0	Parity flag. Set/cleared by hardware each instruction cycle to indicate an odd/even number of '1' bits in the accumulator.

The value presented by RS0 and RS1 selects the corresponding register bank.

RS1	RS0	Register Bank	Address

------------------------------------------------------------

0	0	0	00H-07H

0	1	1	08H-0FH

1	0	2	10H-17H

1	1	3	18H-1FH


PCONdescription
PCON: Power Control Register. Not Bit Addressable.

________________________________________________

| SMOD| -	| -	| -	| GF1	| GF0	| PD	| IDL	|

-----------------------------------------------------------------------------

SMOD	Double baud rate bit. If Timer 1 is used to generate baud rate and SMOD=1, the baud rate is doubled when the Serial Port is used in modes 1, 2, or 3.

-	Not implemented, reserved for future use. (User software should not write 1s to reserved bits. These bits may be used in future 8051 products to invoke new features.)

-	Not implemented, reserved for future use. (User software should not write 1s to reserved bits. These bits may be used in future 8051 products to invoke new features.)

-	Not implemented, reserved for future use. (User software should not write 1s to reserved bits. These bits may be used in future 8051 products to invoke new features.)

GF1	General purpose flag bit.

GF0	General purpose flag bit.

PD	Power Down Bit. Setting this bit activates Power Down operation in the 80C51. (Available only in CMOS.)

IDL	Idle mode bit. Setting this bit activates Idle Mode operation in the 80C51. (Available only in CMOS.)

If 1s are written to PD and IDL at the same time, PD takes precedence.


IdleMode
An instruction that sets PCON.0 causes that to be the last instruction executed before going into the Idle mode, the internal clock signal is gated off to the CPU but not to the Interrupt, Timer, and Serial Port functions. The CPU status is preserved in its entirety; the Stack Pointer, Program Counter, Program Status Word, Accumulator, and all other registers maintain their data during Idle. The port pins hold the logical states they had at the time Idle was activated. ALE and /PSEN hold at logic high levels.

There are two ways to terminate the Idle. Activation of any enabled interrupt will cause PCON.0 to be cleared by hardware, terminating the Idle mode. The interrupt will be serviced, and following RETI, the next instruction to be executed will be the one following the instruction that put the device into Idle.

The flag bits GF0 and GF1 can be used to give an indication if an interrupt occured during normal operation or during an Idle. For example, an instruction that activates Idle can also set one or both flag bits. When an Idle is terminated by an interrupt, the interrupt service routine can examine the flag bits. The other way of terminating the Idle mode is with a hardware reset. Since the clock oscillator is still running, the hardware reset needs to be held active for only two machine cycles (24 oscillator periods) to complete the reset.

The signal at the RST pin clears the IDL bit directly and asynchronously. At this time the CPU resumes program execution from where it left off; that is, at the instruction following the one that invoked the Idle Mode. Two or three machine cycles of program execution  may take place before the internal reset algorithm takes control. On-chip hardware inhibits access to the internal RAM during this time, but access to the port pins is not inhibited, so, the insertion of 3 NOP instructions is recommended following the instruction that invokes idle mode. To eliminate the possibility of unexpected outputs at the port pins, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external Data RAM.


PowerDownMode
An instruction that sets PCON.1 causes that to be the last instruction executed before going into the Power Down mode. In the Power Down mode, the on-chip oscillator is stopped. With the clock frozen, all functions are stopped, the contents of the on-chip RAM and Special Function Registers are maintained. The port pins output the values held by their respective SFRs. The ALE and /PSEN output are held low.

The only exit from Power Down is a hardware reset. Reset redefines all the SFRs, but does not change the on-chip RAM.

In the Power Down mode of operation, Vcc can be reduced to as low as 2V. Care must be taken, however, to ensure that Vcc is not reduced before the Power Down mode is invoked, and that Vcc is restored to its normal operating level, before the Power Down mode is terminated. The reset that terminates Power Down also frees the oscillator. The reset should not be activated before Vcc is restored to its normal operating level, and must be held active long enough to allow the oscillator to restart and stabilize (normally less then 10ms).


IEdescription
IE: Interrupt Enable Register. Bit Addressable.

If the bit is 0, the corresponding interrupt is disabled. If the bit is 1, the corresponding interrupt is enabled.

________________________________________________

| EA	| -	| -	| ES	| ET1	| EX1	| ET0	| EX0	|

-----------------------------------------------------------------------------

EA	IE.7	Disables all interrupts. If EA=0, no interrupt will be acknowledged. If EA=1, each interrupt source is individually enabled or disabled by setting or clearing its enable bit.

-	IE.6	Not implemented, reserved for future use. (User software should not write 1s to reserved bits. These bits may be used in future 80C51 products to invoke new features.)

-	IE.5	Not implemented, reserved for future use. (User software should not write 1s to reserved bits. These bits may be used in future 80C51 products to invoke new features.)

ES	IE.4	Enable or disable the serial port interrupt.

ET1	IE.3	Enable or disable the Timer 1 overflow interrupt.

EX1	IE.2	Enable or disable External Interrupt 1.

ET0	IE.1	Enable or disable the Timer 0 overflow interrupt.

EX0	IE.0	Enable or disable External Interrupt 0.


IPdescription
IP: Interrupt Priority Register. Bit Addressable.

If the bit is 0, the corresponding interrupt has a lower priority and if the bit is 1, the corresponding interrupt has a higher priority.

________________________________________________

| -	| -	| -	| PS	| PT1	| PX1	| PT0	| PX0	|

-----------------------------------------------------------------------------

-	IP.7	Not implemented, reserved for future use. (User software should not write 1s to reserved bits. These bits may be used in future 80C51 products to invoke new features.)

-	IP.6	Not implemented, reserved for future use. (User software should not write 1s to reserved bits. These bits may be used in future 80C51 products to invoke new features.)

-	IP.5	Not implemented, reserved for future use. (User software should not write 1s to reserved bits. These bits may be used in future 80C51 products to invoke new features.)

PS	IP.4	Defines the Serial Port interrupt priority level.

PT1	IP.3	Defines the Timer 1 interrupt priority level.

PX1	IP.2	Defines External Interrupt 1 priority level.

PT0	IP.1	Defines the Timer 0 interrupt priority level.

PX0	IP.0	Defines the External Interrupt 0 priority level.


TCONdescription
TCON: Timer/Counter Control Register. Bit Addressable.

________________________________________________

| TF1	| TR1	| TF0	| TR0	| IE1	| IT1	| IE0	| IT0	|

-----------------------------------------------------------------------------

TF1	TCON.7	Timer 1 overflow flag. Set by hardware when the Timer/Counter 1 overflows. Cleared by hardware as processor vectors to the interrupt service routine.

TR1	TCON.6	Timer 1 run control bit. Set/cleared by software to turn Timer/Counter 1 ON/OFF.

TF0	TCON.5	Timer 0 overflow flag. Set by hardware when the Timer/Counter 0 overflows. Cleared by hardware as processor vectors to the service routine.

TR0	TCON.4	Timer 0 run control bit. Set/cleared by software to turn Timer/Counter 0 ON/OFF.

IE1	TCON.3	External Interrupt 1 edge flag. Set by hardware when External Interrupt edge is detected. Cleared by hardware when interrupt is processed.

IT1	TCON.2	Interrupt 1 type control bit. Set/cleared by software to specify falling edge/low level triggered External Interrupt.

IE0	TCON.1	External Interrupt 0 edge flag. Set by hardware when External Interrupt edge is detected. Cleared by hardware when interrupt is processed.

IT0	TCON.0	Interrupt 0 type control bit. Set/cleared by software to specify falling edge/low level triggered External Interrupt.


TMODdescription
TMOD: Timer/Counter Mode Control Register. Not Bit Addressable.

Timer 1	Timer 0

________________________________________________

| GATE| C/T| M1	| M0	| GATE| C/T| M1	| M0	|

-----------------------------------------------------------------------------

GATE	When TRx (in TCON) is set and GATE=1, Timer/CounterX will run only while INTx pin is high (hardware control). When GATE=0, Timer/CounterX will run only while TRx=1 (software control).

C/T	Timer or Counter selector. Cleared for Timer operation (input from internal system clock). Set for Counter operation (input from Tx input pin).

M1	Mode selector bit.

M0	Mode selector bit.

M1	M0	Mode	Operating Mode

-----------------------------------------------------------------------------------

0	0	0	13-bit Timer (8048 compatible)

0	1	1	16-bit Timer/Counter

1	0	2	8-bit Auto-Reload Timer/Counter

1	1	3	(Timer 0) TL0 is an 8-bit Timer/Counter controlled by the standard Timer 0 control bits. TH0 is an 8-bit Timer and is controlled by Timer 1 control bits.

1	1	3	(Timer 1) Timer/Counter 1 stopped.

-----------------------------------------------------------------------------------

Values for the Timer Set-Up


SCONdescription
SCON: Serial Port Control Register. Bit Addressable.

________________________________________________

| SM0	| SM1	| SM2	| REN	| TB8	| RB8	| TI	| RI	|

-----------------------------------------------------------------------------

SM0	SCON.7	Serial Port mode specifier.

SM1	SCON.6	Serial Port mode specifier.

SM2	SCON.5	Enables the multiprocessor communication feature in modes 2 & 3. In mode 2 or 3, if SM2 is set to 1 then RI will not be activated if the received 9th data bit (RB8) is 0. In mode 1, if SM2=1 then RI will not be activated if a valid stop bit was not received. In mode 0, SM2 should be 0.

REN	SCON.4	Set/Cleared by software to Enable/Disable reception.

TB8	SCON.3	The 9th bit that will be transmitted in modes 2 & 3. Set/Cleared by software.

RB8	SCON.2	In modes 2 & 3, is the 9th data bit that was received. In mode 1, if SM2=0, RB8 is the stop bit that was received. In mode 0, RB8 is not used.

TI	SCON.1	Transmit interrupt flag. Set by hardware at the end of the 8th bit time in mode 0, or at the beginning of the stop bit in the other modes. Must be cleared by software.

RI	SCON.0	Receive interrupt flag. Set by hardware at the end of the 8th bit time in mode 0, or halfway through the stop bit time in the other modes (except see SM2). Must be cleared by software.

SM0	SM1	Mode	Description	Baud Rate

--------------------------------------------------------------------------------------

0	0	0	Shift Register	Fosc./12

0	1	1	8-bit UART	Variable

1	0	2	9-bit UART	Fosc./64 or Fosc./32

1	1	3	9-bit UART	Variable

--------------------------------------------------------------------------------------

Values for the Serial Port Set-Up


Accumulator

ACC is the Accumulator register. The mnemonics for Accumulator-Specific instructions, however, refer to the Accumulator simply as A.


B Register

The B register is used during multiply and divide operations. For other instructions it can be treated as another scratch pad register.


Stack Pointer

The Stack Pointer register is 8 bits wide. It is incremented before data is stored during PUSH and CALL executions. While the stack may reside anywhere in on-chip RAM, the Stack Pointer is initialized to 07H after a reset. This causes the stack to begin at location 08H.


Data Pointer

The Data Pointer (DPTR) consists of a high byte (DPH) and a low byte (DPL). Its intended function is to hold a 16-bit address. It may be manipulated as a 16-bit register or as two independent 8-bit registers.


Ports 0 to 3

P0, P1, P2, and P3 are the SFR latches of Ports 0, 1, 2, and 3, respectively. Writing a one to a bit of a port SFR (P0, P1, P2, or P3) causes the corresponding port output pin to switch high. Writing a zero causes the port output pin to switch low. When used as an input, the external state of a port pin will be held in the port SFR (i.e., if the external state of a pin is low, the corresponding port SFR bit will contain a 0; if it is high, the bit will contain a 1).

Port Structures and Operation


Port Structures and Operation

All four ports in the 80C51 are bidirectional. Each consists of a latch (Special Function Registers P0 through P3), an output driver, and an input buffer.

The output drivers of Ports 0 and 2, and the input buffers of Port 0, are used in accesses to external memory. In this application, Port 0 outputs the low byte of the external memory address, time-multiplexed with the byte being written or read.

Port 2 outputs the high byte of the external memory address when the address is 16 bits wide. Otherwise, the Port 2 pins continue to emit the P2 SFR content.

All the Port 3 pins are multifunctional. They are not only port pins, but also serve the functions of various special features. The alternate functions can only be activated if the corresponding bit latch in the port SFR contains a 1. Otherwise the port pin remains at 0.

I/O Configurations

The bit latch (one bit in the port's SFR) can be represented as a Type D flip-flop, which will clock in a value from the internal bus in response to a "write to latch" signal from the CPU. The level of the port pin itself is placed on the internal bus in response to a "read pin" signal from the CPU. Some instructions that read a port activate the "read latch" signal, and others activate the "read pin" signal.

During external memory accesses, the P2 SFR remains unchanged, but the P0 SFR gets 1s written to it.

Ports 1, 2, and 3 have internal pullups, and Port 0 has open drain outputs. Each I/O line can be independently used as an input or an output. (Port 0 and 2 may not be used as general purpose I/O when being used as the ADDR/DATA BUS for external memory during normal operation.) To be used as an input, the port bit latch must contain a 1, which turns off the output driver FET. Then, for Ports 1, 2, and 3, the pin is pulled high by a weak internal pullup, and can be pulled low by an external source.

Port 0 differs in that its internal pullups are not active during normal port operation. The pullup FET in the P0 output driver is used only when the port is emitting 1s during external memory accesses. Otherwise the pullup FET is off. Consequently P0 lines that are being used as output port lines are open drain. Writing a 1 to the bit latch leaves both output FETs off, so the pin floats. In that condition it can be used as a high-impedance input.

Because Ports 1, 2, and 3 have fixed internal pullups, they are sometimes called "quasi-bidirectional" ports. When configured as inputs they pull high and will source current (IIL) when externally pulled low. Port 0, on the other hand, is considered "true" bidirectional, because when configured as an input it floats.

All the port latches in the 80C51 have 1s written to them by the reset function. If a 0 is subsequently written to a port latch, it can be reconfigured as an input by writing a 1 to it.

Writing to a Port

In the execution of an instruction that changes the value in a port latch, the new value arrives at the latch during S6P2 of the final cycle of the instruction. However, port latches are in fact sampled by their output buffers only during Phase 1 of an clock period. (During Phase 2 the output buffer holds the value it saw during the previous Phase 1). Consequently, the new value in the port latch won't actually appear at  the output pin until the next Phase 1, which will be at S1P1 of the next machine cycle.

If the change requires a 0-to-1 transition in Port 1, 2, or 3, an additional pullup is turned on during S1P1 and S1P2 of the cycle in which the transition occurs. This is done to increase the transition speed. The extra pullup can source about 100 times the current that the normal pullup can. It should be noted that the internal pullups are field-effect transistors, not linear resistors.

In the NMOS 8051 part, the fixed part of the pullup is a depletion mode transistor with the gate wired to the source. The transistor will allow the pin to source about 0.25mA when shorted to ground. In parallel with the fixed pullup is an enhancement mode transistor which is activated during S1 whenever the port bit does a 0-to-1 transition. During this interval, if the port pin is shorted to ground, this extra transistor will allow the pin to source an additional 30mA.

In the CMOS 80C51, the pullup consists of three pFETs.

Port Loading and Interfacing

The output buffers of Ports 1, 2, and 3 can each drive 4 LS TTL inputs. These ports on NMOS versions can be driven in a normal manner by a TTL or NMOS circuit. Both NMOS and CMOS pins can be driven by open-collector and open-drain outputs, but note that 0-to-1 transitions will not be fast.

In the NMOS device, if the pin is driven by an open-collector output, a 0-to-1 transition will have to be driven by the relatively weak depletion mode FET. In the CMOS device, an input 0 turns off pullup pFET3, leaving only the very weak pullup pFET2 to drive the transition.

Port 0 output buffers can each drive 8 LS TTL inputs. They do, however, require external pullups to drive NMOS inputs, except when being used as the ADDRESS/DATA bus for external memory.

Read-Modify-Write Feature

Some instructions that read a port read the latch and others read the pin. Which ones do which? The instructions that read the latch rather than the pin are the ones that read a value, possibly change it, and then rewrite it to the latch. These are called "read-modify-write" instructions. The instructions listed below are read-modify-write instructions. When the destination operand is a port, or a port bit, these instructions read the latch rather than the pin:

ANL	(logical AND, e.g., ANL P1,A)

ORL	(logical OR, e.g., ORL P2,A)

XRL	(logical EX-OR, e.g., XRL P3,A)

JBC	(jump if bit=1 and clear bit, e.g., JBC P1.1,LABEL)

CPL	(complement bit, e.g., CPL P3.0)

INC	(increment, e.g., INC P2)

DEC	(decrement, e.g., DEC P2)

DJNZ	(decrement and jump if not zero, e.g., DJNZ P3,LABEL)

MOV PX.Y,C	(move carry bit to bit Y of Port X)

CLR PX.Y	(clear bit Y of Port X)

SETB PX.Y	(set bit Y of Port X)

It is not obvious that the last three instructions in this list are read-modify-write instructions, but they are. They read the port byte, all 8 bits, modify the addressed bit, then write the new byte back to the latch.

The reason that read-modify-write instructions are directed to the latch rather than the pin is to avoid a possible misinterpretation of the voltage level at the pin. For example, a port bit might be used to drive the base of a transistor. When a 1 is written to the bit, the transistor is turned on. If the CPU then reads the same port bit at the pin rather than the latch, it will read the base voltage of the transistor and interpret it as a 0. Reading the latch rather than the pin will return the correct value of 1.


Serial Data Buffer

The Serial Buffer is actually two separate registers, a transmit buffer and a receive buffer. When data is moved to SBUF, it goes to the transmit buffer and is held for serial transmission. (Moving a byte to SBUF is what initiates the transmission.) When data is moved from SBUF, it comes from the receive buffer.


Timer Registers Basic to 80C51

Register pairs (TH0, TL0), and (TH1, TL1) are the 16-bit Counting registers for Timer/Counters 0 and 1, respectively.


PinDescriptions
80C51 Pin Descriptions

ALE/PROG: (#30) Address Latch Enable output pulse for latching the low byte of the address during accesses to external memory. ALE is emitted at a constant rate of 1/6 of the oscillator frequency, for external timing or clocking purposes, even when there are no accesses to external memory. (However, one ALE pulse is skipped during each access to external Data Memory.) This pin is also the program pulse input (PROG) during EPROM programming.

PSEN\: (#29) Program Store Enable is the read strobe to external Program Memory. When the device is executing out of external Program Memory, PSEN\ is activated twice each machine cycle (except that two PSEN\ activations are skipped during accesses to external Data Memory). PSEN\ is not activated when the device is executing out of internal Program Memory.

EA\ /Vpp:  (#31) When EA\ is held high the CPU executes out of internal Program Memory (unless the Program Counter exceeds 0FFFh in the 80C51). Holding EA\ low forces the CPU to execute out of external memory regardless of the Program Counter value. In the 80C31, EA\ must be externally wired low. In the EPROM devices, this pin also receives the programming supply voltage (Vpp) during EPROM programming.

XTAL1: (#19) Input to the inverting oscillator amplifier.

XTAL2: (#18) Output from the inverting oscillator amplifier.

Port 0: (#39-#32) Port 0 is an 8-bit open drain bidirectional port. As an open drain output port, it can sink eight LS TTL loads. Port 0 pins that have 1s written to them float, and in that state will function as high impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external memory. In this application it uses strong internal pullups when emitting 1s. Port 0 emits code bytes during program verification. In this application, external pullups are required. More About the Ports

Port 1: (#1-#8) Port 1 is an 8-bit bidirectional I/O port with internal pullups. Port 1 pins that have 1s written to them are pulled high by the internal pullups, and in that state can be used as inputs. As inputs, port 1 pins that are externally being pulled low will source current because of the internal pullups. More About the Ports

Port 2: (#21-#28) Port 2 is an 8-bit bidirectional I/O port with internal pullups. Port 2 emits the high-order address byte during accesses to external memory that use 16-bit addresses. In this application, it uses the strong internal pullups when emitting 1s. More About the Ports

Port 3: (#10-#17) Port 3 is an 8-bit bidirectional I/O port with internal pullups. It also serves the functions of various special features of the 80C51 Family as follows:

Port Pin	Pin #	Alternate Function

----------------------------------------------------------------------------------------------

P3.0	10	RxD (serial input port)

P3.1	11	TxD (serial output port)

P3.2	12	INT0\ (external interrupt 0)

P3.3	13	INT1\ (external interrupt 1)

P3.4	14	T0 (timer 0 external input)

P3.5	15	T1 (timer 1 external input)

P3.6	16	WR\ (external data memory write strobe)

P3.7	17	RD\ (external data memory read strobe)

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More About the Ports

RST: (#9) Reset. A high on this pin for two machine cycles while the oscillator is running, resets the device. An internal diffused resistor to Vss permits a power-on reset using only an external capacitor to Vcc.

Vcc: (#40) Supply Voltage

Vss: (#20) Circuit ground potential


On-Chip Oscillator
The On-Chip Oscillator

NMOS Version

The on-chip oscillator circuitry for the NMOS members of the 80C51 family is a single stage linear inverter, intended for use as a crystal-controlled, positive reactance oscillator. In this application the crystal is operated in its fundamental response mode as an inductive reactance in parallel resonance with capacitance external to the crystal.

The crystal specifications and capacitance values are not critical. 30pF can be used in these positions at any frequency with good quality crystals. A ceramic resonator can be used in place of the crystal in cost-sensitive applications. When a ceramic resonator is used, the external capacitors are normally selected to be of somewhat higher values, typically, 47pF. The manufacturer of the ceramic resonator should be consulted for recommendation on the values of these capacitors.

To drive the NMOS parts with an external clock source, apply the external clock signal to XTAL2, and ground XTAL1. A pullup resistor may be used (to increase noise margin), but is optional if VOH of the driving gate exceeds the VIH minimum specification of XTAL.

CMOS Version

The on-chip oscillator circuitry for the 80C51 consists of a single stage linear inverter intended for use as a crystal-controlled, positive reactance oscillator in the same manner as the NMOS parts. However, there are some important differences.

One difference is that the 80C51 is able to turn off its oscillator under software control (by writing a 1 to the PD bit in PCON).

Another difference is that, in the 80C51, the internal clocking circuitry is driven by the signal at XTAL1, whereas in the NMOS versions it is by the signal at XTAL2.

The oscillator can be used with the same external components as the NMOS versions. Typically, the external capacitors are 30pF when the feedback element is a quartz crystal, and 47pF when a ceramic resonator is used.

When a crystal is used at frequencies above 25MHz, the external capacitors should be in the range of 20pF to 25pF.

To drive the CMOS parts with an external clock source, apply the external clock signal to XTAL1, and leave XTAL2 float.

The reason for this change from the way the NMOS part is driven is, that in the NMOS devices the internal timing circuits are driven by the signal at XTAL2, while in the CMOS devices they are driven by the signal at XTAL1.


XTAL specifications
VIH (Input High Voltage) for 80C31/80C51/87C51, except XTAL1 and RST, is between 0.2Vcc+1 V and Vcc+0.5 V

VIH (Input High Voltage) to XTAL1 and RST for 80C31/80C51/87C51 is between 0.7Vcc+0.1 V and Vcc+0.5 V


ONCEmode
On-circuit Emulation Mode

The ONCE ("on-circuit emulation") mode facilitates testing and debugging of systems using the device without the device having to be removed from the circuit. The ONCE mode is invoked by:

1.	Pull ALE low while the device is in reset and PSEN\ is high;

2.	Hold ALE low as RST is deactivated.

While the device is in the ONCE mode, the Port 0 pins go into a float state, and the other port pins and ALE and PSEN\ are weakly pulled high. The oscillator circuit remains active. While the device is in this mode, an emulator or test CPU can be used to drive the circuit. Normal operation is restored after a normal reset is applied.