Study of SYNCHRONISATION
TYPES OF SYNCHRONISATION
Zener Clamped Synchronisation:
This is the sinplest type of Synchronisation circuit.it utilizes the inherent charactristics of UJT to Synchronise the triggering circuit.the UJT has an intrinsic stand off ratio of efficiency .if the emitter voltage of UJT is efficiency times the supply voltage the UJT triggered & emitter is practically short circiuted, until the emitter base diode is reversed biased, & emittr is open circiuted, when the AC Synchronisation supply is applied to zener it clamps the voltage.in this way, it may be noted that there is no capacitor filter connected to the supply,if the instantenious voltage is less than zener voltage, the supply voltage will break the rectified sine wave pulse.this include the clip of supply to zener voltage at the zero crossing of the sine wave. The capacitor charging is starting at zero crossing & when it reaches efficiency v every time it will discharge the capacitor in to a pulse & gate will be applied a pulse. However, only the first pulse will trigger the thyristor when it reaches the end of the half cycles, the supply voltage drops to zero & hence efficiency v will also be low which discharge what ever charge be on the capacitor.
Now, the capacitor is in the dischage from, as it crosses the very first cycle.this is repeated in every half cyce.if the Phase Bridge is used it is necessary to synchronise each triggering circuit seperately with respective supply to thyristor. This demands a seperate triggering circuit to trigger all these to rise thyristor with Synchronised supply deri9ved from the phase, which supplies the thyristor.
Advantages: 1.no extra components are required.
2.inherent simplicity & compactness.
Limitations: 1.gate power has got low power & hence not suitable for SCR's larger than 35 amp.rating.
Positive Supply Capacitor Discharge Synchronisation:
The use of UJT relaxation oscillator is easy to Synchronise as it discharges the capacitor when supply voltage falls down. The limit to power supply voltage & maxi.value of pulse power acll for importanr triggering circuit.
When other thyristor circuit are used, itis necessary to discharge the capacitor by the transistor at zero crossing. The circuits are classified according to Synchronisation supply.
(1) Positive supply capacitor discharge Synchronisation.
(2) Negative supply capacitor discharge Synchronisation.
The fig. Shows a positive supply capacitor discharge positive supply capacitor discharge Synchronisation.a transistor is connected across the capacitor with a current limiting resistor'R'. The base bias to turn 'ON'the transistor Q1 is provided by resistor.another transistor Q2 controls the base bias of Q1 & is supplied by a potential devider Rb1 & Rb2 from untilted & rectified positive Synchronisation supply.
When the Synchronising supply voltage is more than Vbe sat.a X-devision ratio 'x' the transistor Q2 will conduct the surface 'on' the base driveto the transistor Q1is shunted by Q2. The Vcb sat voltage of Q2 is less than Vbe reqd.& transistor Q1will be reqd. base bias. At the end of the half cycle, the supply decrease & transistor Q2 does not get base drive that switches off the transistor Q2. The transistro Q1 now gets base current through 'R'will be 'ON' the capacitor wil be discharged through RC & transistor Q. A shown the sine wave input voltage exceeds the xVb sat.limit the transistor Q2 turns 'ON'& the same cycle is repeated. As the circuit uses two-transistor s for the Synchronisation it is costly.