V Girish

NC – 6 Kumaon Hostel,

IIT Delhi, Hauz Khas

New Delhi - 110016

Email - girish_vgl AT yahoo.com

 

Tel.      91-11-26596917(Res.)

91-11-26596103(VDTT Office)

91-11-26596197(VDTT Lab)

 

 

SKILL SET

·         Physical Design Tools

o        Cadence ICFB Design Suite

o        Tanner Tools

o        Synopsys Design Compiler

·         Circuit Simulators

o        SPECTRE

o        Tanner SPICE

·         Optimization packages - LINDOAPI

·         Programming languages – C, C++, MATLAB, VHDL

·         Platforms - WINDOWS, LINUX, SOLARIS

 

ACADEMIC DETAILS

• Currently doing M Tech in Integrated Electronics and Circuits

Indian Institute of Technology, Delhi

CGPA of 9.824 upto 2^nd semester

 

• B Tech in Electronics and Communication Engineering

College of Engineering, Trivandrum (University of Kerala)

Passing Year: 2003, Marks: 84.12%

 

• Senior Secondary School Certificate

Bhavans’ K.D.K. Vidya Mandir, Renukoot, U.P. (CBSE)

Passing Year: 1999, Marks: 85.2%

 

• Secondary School Certificate

Bhavans’ K.D.K. Vidya Mandir, Renukoot, U.P. (CBSE)

Passing Year: 1997, Marks: 78.6%

 

ACHIEVEMENTS

·         Currently holding the 1^st position in M Tech after two semesters

·         1^st rank in B Tech from University of Kerala

·         Submitted paper for review in VLSI Conference 2005

·         C Subramanian Award for Excellence in Character by Bharatiya Vidya Bhavan.

·         Qualified National Mathematics Olympiad thrice.

 

PROJECTS COMPLETED

1.      GENESIS – A Global Optimizer based RTL-to-GDS VLSI Physical Synthesis Tool (IIT Delhi)

§         Developed a complete package for standard cell and macrocell placement, global and detailed routing supporting standard interfaces like LEF, CIF, Verilog

§         Used C along with LEDA, a data structure package

§         Formulated and implemented global router

§         Development model with a modular structure, integrating third party software package – the global optimizer LINDOAPI

§         Adopted project management techniques like CVS code repository

§         Worked in a team of 6 members

§         Submitted a paper in the 18th VLSI Design Conference

2.      Design of nibble addressable area optimized SRAM (IIT Delhi)

·         Designed poly resistor 4T SRAM cell, decoding logic and the sense amplifiers.

·         The architecture of the decoding logic is made of minimal area by running an optimization formulation to get the number of bits at each level of decoding.

3.      Analog to Digital Converter Design using Support Vector Machines (IIT Delhi)

·         A new design methodology for ADCs using Support Vector Machines and nonlinear kernel

·         Precise way of design using optimization strategies of SVM with the kernel obtained from actual simulations

4.       Encryption Methods using Nonlinear Stream Ciphers (B Tech Project)

·         Study of existing nonlinear stream cipher called Geffe generator identifying its defects

·         Proposal of a modified scheme, which withstands the cryptanalyst attack to a better extent. This scheme was verified in MATLAB

·         Proposed encryption method was supplied to VSSC Trivandrum for use in future programmes

INTERESTS

·         Mixed Signal Circuit Design

·         CAD of VLSI

 

EXTRA CURRICULAR ACTIVITIES

·         Listening to Music and watching movies

·         Traveling to new places

·         Playing games - Indoor and Outdoor

 

REFERENCE

1. Dr. Jayadeva,

Associate Professor,

Dept of Electrical Engineering,

IIT Delhi

Ph. 011 26591087

[email protected]

 

2. Dr. M Jagadesh Kumar,

Associate Professor,

Dept of Electrical Engineering,

IIT Delhi

Ph. 011 26591087

[email protected]

 

3. Mr. David John,

Staff CAD Engineer,

Cypress Semiconductors, Bangalore

Ph. 9818447853

[email protected]