x86 Assembly

x86 assembly language is the assembly language for the x86 class of processors, which includes Intel's Pentium series and AMD's Athlon series.

x86 Instruction Set Architecture

The x86 processor and instruction set design is CISC; however, in the latter half of the 1990s the internal architecture moved towards being more of a RISC or VLIW design. Most modern x86 processors translate their instructions to one or more RISC-like "micro-ops" before they execute them, allowing the substeps of complex instructions to be executed in parallel in a superscalar fashion, rather than just being able to execute instructions in parallel as the original Pentium could do. This behaviour is, however, invisible to the assembly programmer.

The modern x86 instruction set is really a series of extensions of instruction sets that began with the Intel 8008 microprocessor. Nearly full binary backward compatibility is actually present between the Intel 8086 chip through to the modern Pentium 4, Intel Core, Athlon 64, Opteron, etc. processors. (There are certain unusual exceptions, such as the counted shift instructions, corrections to the original PUSHA instruction, some orphaned Intel 80286 semantics, the dropped LOADALL instruction, and the Pentium 4 giving up on precise FPU operation counts.) Each successive instruction extension has been either simply directly added, or accompanied by adding execution modes to the processor.

The Various Kinds of Instructions

In general, the modern x86 instruction set is variable length and alignment independent (encoded as little endian, as is all data in the x86 architecture), combined general (most integer instructions can use any combination of GPRs) and implicit register usage (MUL and DIV use an implicit D:A dual output register combination and floating point instructions always use st(0) as one its parameters), two operand (that is to say, the first register is usually used for both input and output), supports various complex addressing modes (including immediate addressing, offset addressing, and scaled index addressing), contains special support for atomic instuctions (XCHG, CMPXCHG(8B), XADD, and integer instructions which combine with the LOCK prefix), includes floating point (to a stack of registers) and integer instructions, produces conditional flags implicitly (through most integer ALU instruction) and explicitly (via the CMP instruction) and SIMD instructions (instructions which perform parallel simultaneous single instructions on many operands encoded in adjacent cells of wider registers).

The Stack

The x86 processor also comes with a built-in execution stack mechanism. The CALL/RET and the INT/IRET instructions use the properly set up stack to save and restore call-return points. Instructions like ENTER/LEAVE, or other direct manipulations of the stack register (ESP) can be used for saving local data in the stack. The instruction architecture also includes PUSH/POP instructions for direct usage of the stack for integer and address quantities. As it is part of the instruction architecture, this simplifies ABI specifications with respect to "call stack" software support mechanisms as compared with RISC architectures which must be more explicit about call stack details. The stack is a very important part of the architecture that is always active.