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Memory design of 8 Mb using Loadless
CMOS Four-Transistor SRAM Cell in a 0.25-um Logic Technology
This design doesn’t use any load for maintaining the cell node
charge at vdd, rather here the charging the node is done by the
access transistor. This loadless cell design works properly at
0.18 u technology, but due to software limitation, we have made
this loadless SRAM design using 0.25 u technology. This loadless
design uses 1.8 V power supply as Vdd.
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