|
Design of High
Speed Double Edge Triggered D-FF
Double edge triggered (DET) flip- flops are bistable flip-flop
circuits in which data is latched at either edge of the clock
signal. Such flip flops permits the rate of data processing to be
preserved, while using lower clock frequency. So, power consumption
in DETFF based circuits may be reduced. From the design simulation,
maximum frequency obtained is found to be 50 MHz and the average
power dissipation to be 67.6 uW.
| 
