/ VerilogA for pll, vco, veriloga
// Author: Fuding Ge

`include "constants.h"
`include "discipline.h"

module vco_va1(vin, out);
input vin; output out; electrical vin, out;

parameter real vmin=0;
parameter real vmax=vmin+1 from (vmin:inf);
parameter real fmin=1 from (vmin:inf);
parameter real fmax=2*fmin from (fmin:inf);
parameter real vlo=-1, vhi=1;
parameter real tt=0.01/fmax from (0:inf);
parameter real jitter=0 from [0:0.25/fmax);
parameter real ttol=1u/fmax from (0:1/fmax);

real freq, phase, dt;
integer n, seed;

analog begin

@(initial_step) seed=-556;

// compute frequency from input voltage
freq=(V(vin)-vmin)*(fmax-fmin)/(vmax-vmin)+fmin;


//bound the frequency
if (freq>fmax) freq=fmax;
if (freq<fmin) freq=fmin;

// add the phase noise
freq = freq/(1+dt*freq);

//phase is the integral of the freq modulo 2pi
phase=2*`M_PI*idtmod(freq, 0.0, 1.0, -0.5);

//update jitter twice per period
@(cross(phase+`M_PI/2,+1, ttol) or
  cross(phase-`M_PI/2,+1, ttol)) begin
dt=1.414*jitter*$dist_normal(seed, 0, 1);
n=(phase >= -`M_PI/2) && (phase < `M_PI/2);
end
 

V(out) <+ transition(n?vhi:vlo, 0, tt);

end
endmodule