/////////////////////////////////////////// 
//VerilogA for pll, pfd_cp, veriloga    ///
// Author: Fuding Ge, fudingge@yahoo.com //
//////////////////////////////////////////

// In this version I let the current of the charge
// pump to be 10uA with parameter iout.
// You change iout according to you charge pump current


`include "constants.h"
`include "discipline.h"

module pfd_cp (fref, fb, out);

input fref, fb;   //fref and fb are the reference and feedback clock
output out;       // out is the current out

electrical fref, fb, out;

parameter real iout=10u;
// charge pump current

parameter real tt=200p from (0:inf);
parameter real td=1p from (0:inf);
parameter real jitter=200p from (0:td/5);
parameter real ttol=1p from (0:td/5);
parameter integer dir=[-1,1] exclude 0;


integer state, seed;
real dt;

analog begin

@(initial_step) seed=716;
@(cross(V(fref), dir, ttol)) begin
 if (state >-1) state=state-1;
 dt=0.707*jitter*$dist_normal(seed, 0,1);
                 //$dist_normal(seed, 0,1) is Gassian Distribution
 end

@(cross(V(fb), dir, ttol)) begin
 if (state <1) state=state+1;
 dt=0.707*jitter*$dist_normal(seed, 0,1);
 end

I(out) <+ transition (iout*state, td+dt, tt);

end
 
endmodule