// VerilogA for pll, DIV_va, veriloga

`include "constants.h"
`include "discipline.h"

module DIV_va (in,out);
input in; output out; electrical in, out;

parameter real vlo=0, vhi=2.5;
parameter integer ratio=25 from [2:inf);

parameter integer dir=1 from [-1:1] exclude 0;
		//dir=1 for positive edge trigger
		//dir=-1 for negative edge trigger

parameter real tt=100p from (0:inf);
parameter real td=10p from (0:inf);
parameter real ttol=1p from (0:td/5);

integer count,n;
real dt;

analog begin

		//Phase /frequency detector state machine
	@(cross (V(in)-(vhi+vlo)/2, dir, ttol)) begin
		count = count+1;
		if (count >= ratio)
			count=0;
		n=(2*count >= ratio);

	end

V(out) <+ transition(n? vhi: vlo, td, tt);

end
endmodule