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Introduction

For CMOS circuitry, there are two type os power dissipation, one is static power dissipation due to leakage current or other curren drawn continuously from the power supply, including the quiescent current in the analog circuits. Another is dynamic dissipation due to switching transient current and charging and discharging of load capacitances. For a conventional CMOS digital circuit, dynamic power sissipation is the dominent one, while this may not be the case in analog circuit.

There are three major sources of power dissipation in digital CMOS circuits,  which are summarized in the following equation:

The first term is the dynamic power dissipation which we will discuss in detail later.

The second term is due to the direct-path short circuit current I_sc, which arises when both the NMOS and PMOS transistor are sumultaneously active, conducting current directly from supply to ground. For an inverter without load, assuming the input signal rising time t_r and falling time t_f are equal and is t_rf, the shot circuit power dissipation is [Weste1993]:

The third term is the process technology dependent, arises from current due to reverse bias leakage between diffusion region and the substrate, and subthreshold conduction. Tradtionally, this leakage current is not a problem, but for recent application, circuitry usually has a "power-down" mode, in this mode, leakage may be a problem. The dominant term is the dynamic term for a well-designed circuits.

For a digital circuitry, its dynamic power consumption P_dy is:

Here the parameter a is switching activity factor, C_L is its capacitive output load, more specifically, it is the capacitance being recharged during a transition.  f_clk is the clock frequency, V_s is the output swing range (normally equal to V_dd ), and V_dd is the power supply voltage. Reducing anyone of them can benefit the power consumption ofthe circuitry. Actually the stategy to reduce power consumption is based on this equation. Nowmatter what the way it is, the goal of low power techniques at circuit level is to reduce the values of these parameters. In the following sections, we will discuss various way to achieve this goal.

Power reduction at the system topology level
There are a number of options from the system topology level for the circuit designer to choose when implementing a certain function. Among them are static versus dynamic logic, pass-gate versus conventional CMOS logic styles, and synchronous versus a synchronous timing.
 
 

Power reduction inside the circuit level
Transistor and gate sizing

Logic equivalent pin ordering
See the following two-inputs NAND gate. Input pins A and B are logically equivalent, but the do not have identical circuit characteristics, which means they have different delay or power consumption.  Such property can be exploited for low power design.

For the following gate, assume A is at logic high and B switches from logic low to logic high. Initially, both CL and CL1 are charged to VDD. After the switch, both of them switches to ground. Consider another symmetric situation, first B is high and A switches from low to high. Before switch, CL is charged to VDD but CL1 is at ground level because B is high. Thus the switch only leads to the discharge of CL. In this way less current pass through the lower pull-down transistor, and less power dissipation.  Note that in this case input A also has less propagation delay than input B.

From this discussion, we can generally speak, in order to save power, the less frequently switching signal should apply to the transistor more close to the power supply line. For NAND type configuration, this means less switching signal applys to the NMOS close to ground, while for NOR type configuration,it should apply to PMOS closer to VDD. In other words, in CMOS combinational gates, an input transistion involving transistors closer to the output results in better delay and power dissipation. However, in the actual circuit, other factors such as parasitic capacitance, resistance, transistor sizes and input signal may contribute to pin charactristics.
 
 

Network restructuring and reorginazation

Special latches and Flip-flops
 
 
 
 
 
 
 
 
 
 
 
 

Reference

[Chandrakasan, 1995] Anantha P. Chandrakasan, and Robert Brodersen, "Low power Digital CMOS Design",
Kluwer Academic, Boston, MA, 1995

[Rabaey, 1996] Jan M. Rabaey, and Massoud Pedram, editors, "Low Power design Methodologies",
Kluwer Academic, Boston, MA, 1996

[Sanchez-Sinencio, 1998] Edgar Sanchez-Sinencio, and Andreas G. Andreou, "Low-Voltage/Low-Power Integrated Circuits and System: Low-Voltage Mixed-Signal Circuits", IEEE Press, New York, 1998

[Weste, 1993] Neil H.E. Weste, and Kamran Eshraghian, "Principle of CMOS VLSI design, a system perspective", 2nd Edition, Addison-Wesley, 1993,

[Yeap, 1998] Gary Yeap, "Practical Low Power Digital VLSI Design," Kluwer Academic, Boston, MA, 1998
 
 

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