///////////////////////////////////////////////
// VerilogA for digadc, dac_8bit, veriloga
// Fuding Ge
/////////////////////////////////////////////


`include "constants.h"
`include "discipline.h"

//module dac_8bit;
module dac_8bit(vd7, vd6, vd5, vd4, vd3, vd2, vd1, vd0, vout);
input vd7, vd6, vd5, vd4, vd3, vd2, vd1, vd0;
output vout;
electrical vd7, vd6, vd5, vd4, vd3, vd2, vd1, vd0, vout;
parameter real vref  = 1.6 from [0:inf);
//parameter real trise = 0 ;
//parameter real tfall = 0 ;
//parameter real tdel  = 0 ;
parameter real vtrans  = 2.5;

    real out_scaled; // output scaled as fraction of 256

    analog begin
		out_scaled = 0;
		out_scaled = out_scaled + ((V(vd7) > vtrans) ? 128 : 0);
		out_scaled = out_scaled + ((V(vd6) > vtrans) ? 64 : 0);
		out_scaled = out_scaled + ((V(vd5) > vtrans) ? 32 : 0);
		out_scaled = out_scaled + ((V(vd4) > vtrans) ? 16 : 0);
		out_scaled = out_scaled + ((V(vd3) > vtrans) ? 8 : 0);
		out_scaled = out_scaled + ((V(vd2) > vtrans) ? 4 : 0);
		out_scaled = out_scaled + ((V(vd1) > vtrans) ? 2 : 0);
		out_scaled = out_scaled + ((V(vd0) > vtrans) ? 1 : 0);
		V(vout) <+  vref*out_scaled/256+0.6;
    end
endmodule