Standard IRQ, I/O Address, And DMA Assignments
IRQ's
Interrupt requests
are a signal sent by a component of the computer to the
processor informing the processor that there is a critical
task that must be taken can of. It's like the siren and
lights on a police car; when they're turned on, everyone moves
out of the way. IRQ's allow equipment direct access to
the processor, and their actions come under the command of the
interrupt controller.
The interrupt
controller is a chip on the motherboard or an integrated part
of the chipset. (depending on the model and age of the
motherboard) It is designed to receive and verify IRQ
requests from the components and pass that information along
to the processor.
There are actually
two interrupt controllers on every motherboard. It has
been this way since the 286 computers were released.
They each control 8 interrupt requests, with IRQ 2 set aside
for linking the two controllers together. That means
that there are 15 available IRQ request lines on every
motherboard, plus 1 set aside to link the two
controllers.
IRQ
Conflicts
In the early days of
computers, the biggest menace to technicians were conflicting
IRQ's. IRQ conflicts occur when two or more devices
attempt to use the same IRQ at the same time. This
confuses the processor, and it generally sends the information
to the wrong device. This can cause one device, both
devices, or the whole computer to stop working.
It is possible for 2
devices to share an IRQ channel. The stipulation is that
they can not access the IRQ at the same time. This was a
common problem in some modems, as they were linked to the same
IRQ as some early mice. This meant your mouse would work
fine until you dialed you modem, at which the modem would
fail, the mouse would stop working, and/or you'd get a "Blue
Screen of Death". (A Blue Screen Of Death" is technical
slang for the blue screen that occurs when a major system
fault occurs. It is also called a Nuke Screen, a Bomb
Screen, and more generally The Blue Screen")
Standard IRQ
Assignments
IRQ# |
Standard Device |
Description |
0 |
System
Timer |
Used For
System Timer |
1 |
Keyboard
Controller |
Used For
Keyboard Controller |
2 |
Cascade Link
To IRQ #s 8-15 |
In order to
allow dual-interrupt controllers, IRQ2 is linked to
IRQ9. If IRQ2 is used, IRQ9 can not be used, or
all IRQ's above 7 will stop working. This link is
called interrupt cascading. |
3 |
COM2 +
COM4 |
Default
interrupt for COM2 and COM4, as well as the default for
many modems. |
4 |
COM1 +
COM3 |
Default
Interrupt for COM1 and COM3, and generally is the serial
port used by serial mice. |
5 |
Sound
Card/Network Interface Cards |
Although most
older sound cards used IRQ5, NICs, LPT2, and USB
hosts are known to use this interrupt. |
6 |
Floppy Disk
Controller |
Used for
floppy disk controller |
7 |
LPT1 |
Standard
Assignment for #1 Printer Port |
8 |
Real-Time
Clock |
Used for the
real-time clock, which tracks real-world time as opposed
to computer time. |
9 |
None |
Generally
available, but can be used for NICs and other
equipment. If IRQ2 is used, this must remain
open. |
10 |
None |
Generally
available, although more and more sound cards are taking
advantage of this IRQ. |
11 |
SCSI
adapters/Video Cards |
Often used by
SCSI adapters, video cards, and even some older sound
cards with IDE channels on them. |
12 |
PS/2 Mouse
Connector |
If the
motherboard has a PS/2 mouse connection, this IRQ is
reserved for that usage. Otherwise, it is
available. |
13 |
Math
Coprocessor |
Used by the
math coprocessor. Although the math coprocessor is
generally built into the processor, it still requires an
interrupt to function. |
14 |
Primary IDE
Adapter |
Used by the
primary IDE adapter. |
15 |
Secondary IDE
Adapter |
Used by the
secondary IDE adapter, and in single-channel IDE systems
is not used at all. |
I/O
Addresses
As opposed to IRQs,
I/O addresses can not be shared by devices. I/O
addresses are addresses in memory that are assigned for
specific devices to use when exchanging information with the
rest of the devices and components in the
computer.
An I/O address is
more accurately described as a range of memory
locations. The range can vary from 1 byte to 32 bytes,
but must be a 1, 2, 4, 8, 16, or 32 byte length. You
probably won't be asked the byte length or the ending address,
and most questions will deal with the beginning address of the
memory location.
I/O addresses are
written in hexadecimal notation (i.e. 2F8h) The h
indicates that the address is in hexadecimal notion, and has
no value in the number system. It also isn't necessarily
important to decipher the value of the memory location.
When a device has
data it wants to share, it sends that data to it's I/O
address. For example, a sound card requires information
to be processed, so it sends it to it's I/O address. The
CPU knows the data will be at this location, so it can process
the data when necessary. The process of completing
input/output operations through I/O addressing is called
Memory Mapping, or memory-mapped I/O.
Standard I/O
Addresses
I/O Address |
Standard
Assigned Component |
000h |
DMA Controller - Channels 0-3 |
020h |
IRQ Interrupt Controller - 0-7 |
060h |
Keyboard |
0F8h |
Math Coprocessor |
130h |
SCSI Adapter |
170h |
Secondary IDE Controller |
1F0h |
Primary IDE Controller |
200h |
Game Port |
220h |
Sound Card |
278h |
LTP2 |
2E8h |
COM4 |
2F8h |
COM2 |
300h |
Network Interface Cards |
3B0h Or 3C0h |
VGA Adapter |
378h |
LTP1 |
3E8h |
COM3 |
3F0h |
Floppy Disk Controller |
3F8h |
COM1 |
Direct Memory
Access (DMA)
As with I/O
addresses, DMA channels are assigned to a single device and
ONLY a single device. DMA channels allow devices to
bypass the CPU when transferring data to memory. This
allows the device to transfer the data faster than if it had
to pass through the CPU, but can slow down the system if the
CPU has to wait for the data to be completely
transferred. (In most cases, the faster transfer more
than makes up for the CPU loss.)
Each set of 4 DMA
channels has it's own DMA controller. the
dual-controller DMA system originated with the 286 computers,
and continues to this day. As with IRQ's, DMA channel #4
is cascaded with the primary DMA controller in order to link
the two controllers together.
DMA Standard
Assignments
DMA Channel |
Standard Assignment |
0 |
DRAM
Refresh |
1 |
Available |
2 |
Floppy
Controller |
3 |
Available |
4 |
Cascade link
between dual-DMA controllers. |
5 |
Available |
6 |
Available |
7 |
Available |
Logical
Names
COM and LPT ports are
both given logical names as well as their IRQ and I/O address
assignments. When you see COM1, you know it will be
referring to IRQ4 and I/O address 3F8-3FFh. This is done
to allow software to communicate through the logical name as
opposed to the physical properties. Try to remember the
COM and LPT ports physical properties.
In order to see the
physical properties at work in your computer, click on
Start->Settings->Control Panel and double-click on the
System icon. Look in the device manager, and click on
the appropriate radio button. (In Win2K, click on view
and hit the appropriate menu item) Although these
physical properties may vary by your computer, the basics will
be the same. Try to remember the standard assignments.
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