Duration : 6days
Specs Given :
Design a processor with the
following specifications:
The following instructions have
to be implemented:
„ Mov dst, src -- dst <= src
„ Inc dst, src -- dst <= src +
1
„ Dec dst, src -- dst <= src -
1
„ Add src -- src <= src + A
„ Sub src -- src <= src - A
„ SL dst, src -- dst <= shift
left src
„ SR dst, src -- dst <= shift
right src
„ CMP src -- set Z flag if src = A
„ Mov A, immediate -- A <=
immediate data
„ JMP immediate_offset -- jump to
PC + imm_offset
„ JZ immediate_offset -- jump to
PC + imm_offset if Z=1
„ JMP -- jump to address pointed
by [CD]
„ Load dst -- dst <= memory
contents at
-- address [CD]
„ Store src -- memory at [CD]
<= src
Src, dst can be either A, B, C,
D or X. PC is the program counter. [CD]
represents the contents of
register C and D after concatenation. D is the least
significant byte.
X is visible at the periphery as
"X In" and "X Out" as I/O ports. When anything is
assigned to X, it will appear at
"X Out". When X is read, the contents at "X In" will
be used.
Immediate data or immediate
offset is provided as part of the instruction.
A, B, C, D and X are 8 bits
wide.
Z flag is set whenever the
result of any operation is zero.
Assume that the program memory
and the data memory have synchronous
writes and asynchronous reads.
Write operation: On a clock edge
when the WR is asserted the data on the data
bus is written into the location
pointed by address.
Read operation: When the RD is
asserted, the contents of the location pointed by
address will be presented at the
data bus by the memory. When RD is de-asserted the memory will stop driving the
bus.
For the sake of simplicity,
assume that both the memories are fast enough to
complete the read and write
operations in one clock.
Study the instruction set
carefully. Design instruction opcodes such that
implementation requires minimum
hardware delays. Choose an optimum
instruction size.
You are allowed to use standard
building blocks like multiplexers, adders,
decoders, flip-flops, etc. For
the remaining you have to do a gate level design.
For combinational blocks with 4
or less inputs, you may just mention the
equation. No combinational logic
minimization is expected.
You may skip or modify certain
instructions to improve performance. But you
have to give proper
justification for that. Implementation of the call instruction is
optional. For this you may
assume an internal stack memory. You are free to add
more instructions.
PROCESSOR
Block
Diagram:
Pin
Description
:
The
input/output ports to the processor are
|
Sr No. |
Name |
Description |
Direction |
Remark |
|
1. |
clk |
Clock |
In |
|
|
2. |
reset |
Reset |
In |
|
|
3. |
xin[7:0] |
Parallel data input in to the processor |
In |
|
|
4. |
qx[7:0] |
Parallel data output from the processor |
Out |
|
|
5. |
prgmem[15:0] |
Program counter value output to the program memory |
Out |
Pins
connected to program memory |
|
6. |
instadd[10:0] |
Instruction in to the processor from data memory |
In |
|
|
7. |
cd[15:0] |
Address to the data memory |
Out |
Pins
connected to data memory |
|
8. |
data_dmem |
Data from and to the data memory |
Inout |
|
|
9. |
rd |
Signal to data memory to tell it to send data of
desired address on the data_dmem line |
out |
|
|
10. |
wr |
Signal to data memory to tell it to read data on
the data_dmem line |
Out |
Block
Description:
The
processor essentially contains 6 blocks.
1.
ALU
– arithmetic and logic unit.
2.
Mux
to input data into the alu.
3.
Register
Bank – containing 5 registers A,B,C,D and out-port register.
4.
Block
to decode when and in which register the data is to be put.
5.
Program
counter block.
6.
Logic
to produce rd and wr signal for the data memory.
o
Prg counter
o
ALU
The
data path between these blocks is shown in figure above. The description of
each block is shown below.
ARITHMETIC
and LOGIC UNIT
This block can be further divided
into blocks as-
1.
Addition,
subtraction, Increment and decrement block.
2.
Shift
block, and
3.
Zero
flag
Add/sub block.
The
block has feature of adding data from the source register and register a and
storing it in the required register. The features of increment and decrement
are also present in the block. There carry from the adder is neglected. The
compare function is also carried is this block only. The source is subtracted
from the register A and if the result is zero the flag is set.
Shift Block
The
data is shifted in this block with the help of a structure similar to the
barrel shifter.
And Block
The
data from the src is and-ed with the data in register A.
Zero Flag
Whenever the data going out of the alu is zero the flag is set. This is the only flip/flop in the entire block. On call the value of the z flag is stored in a register present in the program counter block. This value is restored on return command.
Decoding
of data to ALU
The data from the five registers A, B, C, D and xin are taken as input and the output of the block is called src(given as value of src to the alu block). The block is enabled only when the alu is supposed to operate or the data is to be moved from one register to the other or data is to be transferred to the data memory. If none of the condition mentioned is present, i.e. on block disable, the data output from the block is ‘00000000’.
Register
Bank
It has five registers A, B, C, D and X. the input logic is present in the register bank itself while the load pin of the registers is controlled by another block. The input to the register is of 8 bit and is either from the des output of the alu or from the data memory to facilitate Load command. The common input is connected to all the registers and is loaded as per the input to the load pins. The output is provided to the decoding logic mentioned above.
Program Register Block
This block contains three 16 bit registers.
1.The first one is the program counter used to give the location point to the program memory.
2. The second register is used to store the value of the program counter when the call is there. Since there is only one register to store the value of the program counter nested calls are not allowed.
3.The third register is of stack-pointer and is used for Push and Pop statement.
It also has a register to store the value of zero flag whenever the is a call.
Destination Decoder block:
The inputs to this block is instruction and the
outputs depending on the instruction are the load pin of all the internal
registers. The outputs are called as load A, load B, load C, load D and load X
for registors A,B,C,D and Xout respectively. The pins attain a high value when
the descode of the particular register is met and the instruction demands data
to be written.
Rd
, wr logic for data memory.
This is the simplest of all blocks
and has only a few comparators to tell when the read and write is to be
performed.
Test
Strategy:
In order to test the processor various programs are written involving different conditions and as many instructions from the instruction set possible.
1.
First
the program is fed into the program memory using a test bench. As long as the
data is being written to the data memory the processor is in the reset state.
a)
when
writing the data into the program memory the memory is first reset filling all
memory positions with zero’s.
b)
next
the data is written at every clock into the memory elements.
2.
As
soon as the complete data is written into the memory the reset for the processor
is made high so that is can start functioning.
3.
now
the processor starts reading the instructions from the memory from location
‘0000’. If the program starts from some other location then an appropriate jump
should be given to that location.
The programs used for used were
-
comparision
of 2 matrix elements using subroutine
-
swapping
of data in a reg with data in a without use of a third register
Note: The
program is written in a textio in hex code to facilitate the user. The data to
xin is also provided using another textio.
Critical conditions:
All the instructions are to be checked out in the test bench along
with the conditions involving repetitive statements. Certain conditions like
statements involving the data memory are checked with special care. These
statements are repetitive PUSH and POP statements, CALL statement.
This is tried out in the
program written for the comparision of two matrix. A matrix is said to be equal
to another only if all the elements of the matrix are equal.
The processor does not
support nested call statements while nested jumps are allowed. The return is
possible by RET and RZ that is unconditional and conditional return statements.
RESULT
In all conditions checked for the processor is found
working properly.
Instruction set
|
Instruction |
Instruction word |
||||||||||||
|
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|||
|
|
|
Operand |
contol |
destination |
source |
||||||||
|
ADD |
1 |
1 |
0 |
0 |
0 |
D |
D |
D |
S |
S |
S |
||
|
SUB |
1 |
1 |
0 |
0 |
1 |
D |
D |
D |
S |
S |
S |
||
|
INC |
1 |
1 |
0 |
1 |
0 |
D |
D |
D |
S |
S |
S |
||
|
DEC |
1 |
1 |
0 |
1 |
1 |
D |
D |
D |
S |
S |
S |
||
|
SL |
1 |
1 |
1 |
0 |
0 |
D |
D |
D |
S |
S |
S |
||
|
SR |
1 |
1 |
1 |
0 |
1 |
D |
D |
D |
S |
S |
S |
||
|
AND |
1 |
1 |
1 |
1 |
0 |
D |
D |
D |
S |
S |
S |
||
|
MOV |
1 |
1 |
1 |
1 |
1 |
D |
D |
D |
S |
S |
S |
||
|
CMP |
1 |
1 |
0 |
0 |
1 |
1 |
1 |
1 |
S |
S |
S |
||
|
LOAD |
1 |
0 |
0 |
1 |
0 |
D |
D |
D |
1 |
1 |
1 |
||
|
STR |
1 |
0 |
0 |
1 |
1 |
1 |
1 |
1 |
S |
S |
S |
||
|
MOV A,imm |
1 |
0 |
1 |
Data |
|||||||||
|
JMP |
0 |
0 |
0 |
Offset |
|||||||||
|
JZ |
0 |
0 |
1 |
Offset |
|||||||||
|
CALL |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
||
|
JUMP |
0 |
1 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
||
|
|
|
|
|
|
|
|
|
|
|
|
|
||
|
RET |
0 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
||
|
RZ |
0 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
||
|
PUSH |
0 |
1 |
0 |
0 |
1 |
1 |
1 |
1 |
S |
S |
S |
||
|
POP |
0 |
1 |
0 |
1 |
1 |
D |
D |
D |
1 |
1 |
1 |
||
|
HLT |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
||
|
NOP |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
||
X =
000
A =
001
B =
010
C =
011
D =
100
NOTE:1. All
instructions are executed in a single cycle.
2.
Nested
calls are not allowed.
3. Push of X and Pop to X are not allowed.
4. The first bit of the offset in jump instruction gives the direction of jump. ‘1’ denotes forward jump and ‘0’ denotes backward jump.
Op-code chart
|
Function |
Add |
Sub |
Inc |
Dec |
Sl |
Sr |
Mov |
AND |
|
XßX+A |
600 |
640 |
680 |
6C0 |
700 |
740 |
7C0 |
780 |
|
XßA+A |
601 |
641 |
681 |
6C1 |
701 |
741 |
7C1 |
781 |
|
XßB+A |
602 |
642 |
682 |
6C2 |
702 |
742 |
7C2 |
782 |
|
XßC+A |
603 |
643 |
683 |
6C3 |
703 |
743 |
7C3 |
783 |
|
XßD+A |
604 |
644 |
684 |
6C4 |
704 |
744 |
7C4 |
784 |
|
AßX+A |
608 |
648 |
688 |
6C8 |
708 |
748 |
7C8 |
788 |
|
AßA+A |
609 |
649 |
689 |
6C9 |
709 |
749 |
7C9 |
789 |
|
AßB+A |
60A |
64A |
68A |
6CA |
70A |
74A |
7CA |
78A |
|
AßC+A |
60B |
64B |
68B |
6CB |
70B |
74B |
7CB |
78B |
|
AßD+A |
60C |
64C |
68C |
6CC |
70C |
74C |
7CC |
78C |
|
BßX+A |
610 |
650 |
690 |
6D0 |
710 |
750 |
7D0 |
790 |
|
BßA+A |
611 |
651 |
691 |
6D1 |
711 |
751 |
7D1 |
791 |
|
BßB+A |
612 |
652 |
692 |
6D2 |
712 |
752 |
7D2 |
792 |
|
BßC+A |
613 |
653 |
693 |
6D3 |
713 |
753 |
7D3 |
793 |
|
BßD+A |
614 |
654 |
694 |
6D4 |
714 |
754 |
7D4 |
794 |
|
CßX+A |
618 |
658 |
698 |
6D8 |
718 |
758 |
7D8 |
798 |
|
CßA+A |
619 |
659 |
699 |
6D9 |
719 |
759 |
7D9 |
799 |
|
CßB+A |
61A |
65A |
69A |
6DA |
71A |
75A |
7DA |
79A |
|
CßC+A |
61B |
65B |
69B |
6DB |
71B |
75B |
7DB |
79B |
|
CßD+A |
61C |
65C |
69C |
6DC |
71C |
75C |
7DC |
79C |
|
DßX+A |
620 |
660 |
6A0 |
6D0 |
720 |
760 |
7D0 |
7A0 |
|
DßA+A |
621 |
661 |
6A1 |
6D1 |
721 |
761 |
7D1 |
7A1 |
|
DßB+A |
622 |
662 |
6A2 |
6D2 |
722 |
762 |
7D2 |
7A2 |
|
DßC+A |
623 |
663 |
6A3 |
6D3 |
723 |
763 |
7D3 |
7A3 |
|
DßD+A |
624 |
664 |
6A4 |
6D4 |
724 |
764 |
7D4 |
7A4 |
|
Mnemonics |
Op-code |
Functions |
|
CMP
X |
678 |
|
|
CMP
A |
679 |
|
|
CMP
B |
67A |
|
|
CMP
C |
67B |
|
|
CMP
D |
67C |
|
|
MOV
A,imm |
500-5FF |
Aßimm |
|
Load
X |
487
|
Xß[CD] |
|
Load
A |
48F |
Aß[CD] |
|
Load
B |
497
|
Bß[CD] |
|
Load
C |
49F |
Cß[CD] |
|
Load
D |
4A7 |
Dß[CD] |
|
Store
X |
4F8 |
[CD]ßX |
|
Store
A |
4F9 |
[CD]ßA |
|
Store
B |
4FA |
[CD]ßB |
|
Store
C |
4FB |
[CD]ßC |
|
Store
D |
4FC |
[CD]ßD |
|
JMP |
001-0FF |
Jump
--offset 8 bit -- |
|
JZ |
101-1FF |
Jump
on zero--offset 8 bit -- |
|
JUMP |
280 |
Jump
to[CD] |
|
CALL |
200-23F |
|
|
RET |
300-33F |
|
|
RZ |
380-3BF |
|
|
PUSH
A |
279 |
|
|
PUSH
B |
27A |
|
|
PUSH
C |
27B |
|
|
PUSH
D |
27C |
|
|
POP
A |
2CF |
|
|
POP
B |
2D7 |
|
|
POP
C |
2DF |
|
|
POP
D |
2E7 |
|
|
HLT
|
000,080,100,180 |
Halt
|
Additional
features:
à 2 more registers can be
added without increasing the instruction length.
For vhdl
code mail @ [email protected]