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Instruction
Set
Here is the Z80 style instruction set I created.
There is nothing new or any dual word instructions. The same old PIC
mnemonics with new names and register,target
format reversed to target,register format.
There is not a separate opcode for literal operations. The argument
of a command without destination is treated as literal. For example:
ld 12h
;this loads the literal 12h to A
ld 04h,a ;this loads the content
of A to file register 04h
This way one has to remember only one opcode for moving bytes around.
This way the total number of opcodes one is supposed to remember is
reduced to 27.
freg : file register
A : Accumulator (working register W)
| Instruction |
Operation |
Microchip equivalent |
| Load Group |
| LD A,freg |
Load freg
to A |
MOVF freg,W |
| LD F,freg
|
Load freg
to f (to itself) |
MOVF freg,F |
| LD freg,A |
Load A to
frag |
MOVWF freg |
| LD literal |
Load literal
to A |
MOVLW literal |
| Exchange Group |
| SWAP A,freg |
Swap nibbles
in freg, and load to A |
SWAPF freg,W |
| SWAP F,freg |
Swap nibbles
in freg, and load to f (to itself) |
SWAPF freg,F |
| Arithmetic and Logical Group |
| ADD A,freg |
Add A to freg,
and store the result in A |
ADDWF freg,W |
| ADD F,freg
|
Add A to freg,
and store the result in freg |
ADDWF freg,F |
| ADD literal |
Add literal
to A |
ADDLW literal |
| SUB
A,freg |
Subtract
A from freg, and store the result in A |
SUBWF
freg,W |
| SUB F,freg |
Subtract A
from freg, and store the result in freg |
SUBWF freg,F |
| SUB literal |
Subtract literal
from A |
SUBLW literal |
| OR A,freg |
Inclusive
OR A with freg, and store the result in A |
IORWF freg,W |
| OR F,freg |
Inclusive
OR A with freg, and store the result in freg |
IORWF freg,F |
| OR literal |
Inclusive
OR A with literal |
IORLW literal |
| XOR A,freg |
Exclusive
OR A with freg, and store the result in A |
XORWF freg,W |
| XOR F,freg |
Exclusive
OR A with freg, and store the result in freg |
XORWF freg,F |
| XOR literal |
Exclusive
OR A with literal |
XORLW literal |
| AND A,freg |
AND A with
freg, and store the result in A |
ANDWF freg,W |
| AND F,freg
|
AND A with
freg, and store the result in freg |
ANDWF freg,F |
| AND literal |
AND A with
literal |
ANDLW literal |
| NEG A,freg |
Complement
freg and store the result in A |
COMF freg,W |
| NEG F,freg |
Complement
freg and store the result in freg |
COMF freg,F |
| DEC
A,freg |
Decrease
freg and store the result in A |
DECF
freg,W |
| DEC F,freg |
Decrease freg
and store the result in freg |
DECF freg,F |
| INC A,freg |
Increase freg
and store the result in A |
INCF freg,W |
| INC F,freg |
Increase freg
and store the result in freg |
INCF freg,F |
| Call Return, and Flow Control
Group |
| CALL Address |
Call subroutine
at address |
CALL Address |
| RET |
Return from
subroutine |
RETURN |
| RETI |
Return from
interrupt |
RETFIE |
| RETLW |
Return with
literal in A |
RETLW |
| DECSZ A,freg |
Decrement
freg, Skip if 0 ,and store the result in A |
DECFSZ A,freg |
| DECSZ F,freg |
Decrement
freg, Skip if 0 ,and store the result in freg |
DECFSZ F,freg
|
| INCSZ A,freg |
Increment
freg, Skip if 0 ,and store the result in A |
INCFSZ freg,W |
| INCSZ F,freg |
Increment
freg, Skip if 0 ,and store the result in freg |
INCFSZ freg,F |
| BITSC freg,bit |
Bit Test freg,
Skip if Clear |
BTFSC freg,bit |
| BITSS freg,bit
|
Bit Test freg,
Skip if Set |
BTFSS freg,bit |
| JP Address |
Jump to Address |
GOTO Address |
| Bit Manipulation Group |
| RES freg,bit |
Clear bit
of freg |
BCF freg,bit |
| SET freg,bit |
Set bit of
freg |
BSF freg,bit |
| Rotate and Shift Group |
| RR A,freg |
Rotate Right
freg through Carry,and store the result in A |
RRF freg,W |
| RR F,freg |
Rotate Right
freg through Carry,and store the result in freg |
RRF freg,F |
| RL A,freg |
Rotate Left
freg through Carry,and store the result in A |
RLF freg,W |
| RL F,freg |
Rotate Left
freg through Carry,and store the result in freg |
RLF freg,F |
| General Purpose Arithmetic and
CPU Control Group |
| CLR freg |
Clear freg |
CLRF freg |
| CLRA |
Clear A |
CLRW |
| CLRWDT |
Clear Watchdog
Timer |
CLRWDT |
| SLEEP |
Go into standby
mode |
SLEEP |
| NOP |
No operation |
NOP |
There are some instructions that are not available
in the table above. For example, when a register is moved into itself
after some operation the instruction can be written like this:
ADD self,15h
LD self,05h
RR self,1Bh
Also it is possible to write JMP
instead of JP, or DSZ instead of DECSZ and so on...
These are defined in the table for TASM but not in my Frogbit program.
Thats why I did no include them here.
Using TASM or Frogbit you can create a totally diffrerent instruction
set if you wish.
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