DAVID NOEL BABBAGE II
                                           [email protected]

                                                     (408) 391-2953
___________________________________________________________________

Skills

Working within both small and large company cultures, I have exhibited a high

    level of motivation and have proven to be an integral part of their successes. I have

    worked in design teams ranging in size from 3 to15 people, while effectively utilizing

    various EDA Tools of the industry. Passionate on improving the ASIC methodology

    and being involved in many new products, I am looking for a position to expand my

    ASIC design, verification, and methodology experience.

 

Patents Pending

·        MPEG4 Decoder Post Processing

 

Work Experience
   MediaQ, Santa Clara, CA.                                                     8/99 to present

ASIC Design Engineer

·        Lead the Design Methodology Group

·        Architecture, design, and verification (C model data file matching) of a MPEG4

Decoder Post Processing Module

·        Designed and verified the MPEG4 Encoder modules Run Length Encoder

and Reconstruction

·        Modified, verified, and validated a Graphics Controller and Flat Panel Interface

·        Integrated, modified, and verified a Java Hardware Accelerator core (Nazomi’s

JSTAR) with an ARM 922T System on a chip

·        Modified and verified a USB Host IP

·        Designed and verified a SOC Interrupt Controller

·        Designed, verified, and validated a DMA Transfer Module for a SOC and a

PCI / Strong ARM interface

·        Integrated and verified an Ethernet MAC IP

·        Designed and verified a PCI Master / Strong ARM DMA block

·        Worked on architecture for integrating CAN and MOST interfaces

 

Lockheed Martin, Sunnyvale, CA.                                        3/97 to 8/99

    ASIC Design Engineer

·        Designed over 50% of the 180K gate Communication Interface ASIC and

several modules for monitor FPGA in VHDL

·        Generic test bench for chip level testing

·        Compiled multiple RTL and Gate level designs into the Quickturn Emulator

·        Generated functional, RAM, ATPG, and Burnin vectors for the foundry

·        Synthesis scripts targeting Honeywell HX2000 library

·        Card/Board testing

·        ASIC Lead supporting SW Development and Card/Box testing

·        Quickturn Mercury Beta Testing

 

  Intel Corp, Santa Clara, CA.                                                 7/96 to 1/97
    Graduate Rotation Engineer with rotations in Design and Test Technology Quality &
    Reliability. In DTQR, I spent the rotation working on the Unit and Flow Testing of
    RV tools and designing some Perl scripts and testing them. In TTQR, I spent the
    rotation defining the Cert. plan for Scan and the Cert. plan for a Scan DRC.

 

  Detroit Edison, Monroe, MI.                                                Summer 1995
    Worked as a summer student in the Instrumentation and Controls Group in Plant
    Engineering at Fermi II (Nuclear Power Plant).

 

Education
  Stanford University, Palo Alto, CA                                       Spring 1999
    Non Degree Option student. Courses: Computer Architecture and Organization.

 

  The University of Michigan, Ann Arbor, MI.                      1992-1996
    B.S. in Electrical Engineering, Cum Laude. Design content included the building of
    an 16-bit RISC microprocessor chip and designing an Electric Car fueled by a H2
    Fuel Cell. Also gained experience fabricating and testing various devices in the
    University's clean room. Relevant Classes in VLSI Design, Semiconductor Device
    Theory, Solid State Device Lab, Properties of Transistors, Intro to Optics, Digital
    and Analog Electronics.

 

Related Skills
    Synopsys tools: VCS, Virsim, dc_shell, and Primetime; Modeltech’s Analyzer and
    Simulator; Undertow; Quickturn; Quickbench; Synplicity; Actel designer; Mentor

    Graphics tools: IC station, DA, Accusim, Quicksim, DLS, Schematic Editor; Opus;

    RV DRC; Scan DRC; HDL languages VHDL and Verilog; Computer Languages

    include Fortran, Matlab, C Shell, ARM Assembly, and Perl.

 

Activities and Interests
 HKN: Electrical/Computer Engineering Honor and Service Society
 U of M Marching Band                                    Former Democratic Precinct Delegate
 Son's of the American Legion Squadron 409   U of M Dean's List
 Assist with installations and sales of Home Theater Products for my family’s business.

 

References upon request