This paper also contains simple explanations in proving the equations involved for computing the multiplication inverse in GF(256) using simple math. Also a worked example by hand is also provided so that the reader will get a better understanding about how the SubByte operation is computed. Besides that, a test circuit for testing the S-Box is also built so that the hardware architecture discussed in the paper is tested and its functionality can be verified. The test circuit implementation is done on a XESS XSA-200 board which houses the Spartan II XCS200-5 FPGA.
For more details about this FPGA project, you are welcomed to download the PDF file of this paper. I've also provided the VHDL source codes and the project files of the test circuit below. Also in the project file is the VHDL source codes for the combinational logic based S-Box. The VHDL source codes are compiled using Xilinx ISE 8.1. :)
PDF File: Practical_Implementation_of Rijndael_S-Box_Using_Combinational_Logic.pdf
Xilinx ISE Project Files: SBox_Test_Circuit.zip
The above files can also be acquired from the Design Examples of the XESS website at this URL:
http://www.xess.com/ho03000.html
