However, so far little attention has been placed on interfacing programmable logic device such as a CPLD or FPGA to the HD44780. Therefore, here I present a simple method of interfacing using delay elements and a FSM. The procedure to devise the hardware and FSM is presented in a step by step method as written in the PDF documentation below. Also, a test circuit is built in order to verify that the hardware and FSM configured within the FPGA is functional. The test circuit is implemented on a XESS XSA-200 board which houses the Spartan II XCS200-5 FPGA.
For those who are interested in this FPGA project, you are welcomed to download the PDF documentation and the VHDL source code below. The VHDL source code is compiled using Xilinx ISE 8.1. :)
PDF File: FPGA_Interfacing_of_HD44780_Based_LCD_Using_Delayed_FSM.pdf
Xilinx ISE Project Files: Test_LCD_HD44780.zip
The above files can also be acquired from the Design Examples of the XESS website at this URL:
http://www.xess.com/ho03000.html
