sysinfo/macemu.txt an "accurate" Macintosh reference for Mac OS emulation formatted for 80-char. window see terms.txt for terminology If you still don't get the text here then you need to read up if you want to emulate the Mac. === i - Contents 1 - Emulation 1.1 - Considerations 1.2 - Fast page table method 2 - Addressing 2.1 - Address space 2.2 - Virtual Memory 2.3 - Video 2.4 - Sound 3 - Central Processing Unit 3.1 - Processor types 3.2 - Debugging and correct CPU emulation 3.3 - Caching 3.4 - 68060 and unused instructions 4 - Floating Point Unit 5 - Timer 5.1 - Timing types 5.2 - Interrupts === 1.1 - Emulation considerations The emulator should handle SIGENV exceptions, most of them emulated as Bus Errors, returning to normal afterward. Non-paging emulation code would be faster, but others slower (SIGENV for all h/w reads and writes), and also requires native page mapping--in assembly, and difficult. The rest of this text will use basic code considerations only when it comes to emulation. Hardware support, as the ROM expects, should be implemented, not matter how slow it may be. Only after that should you add an option for faster methods by modifying the ROM in memory. == 1.2 - Fast page table method Address space emulation would use an upper 20-bit page table, partly operated by the virtual [Paged]MMU: (Native) NULL entry = h/w code (only case). - unimplemented case: generate a Bus Error exception. Non-NULL: normal read/write space, including RAM, ROM, VRAM. 24-bit addressing would simply mirror pages based on the top 8 bits. Remember: capability of read-only paging means two tables should be used. In relative address mode on the native machine (i.e., Intel), the lowest space is reserved for the emulator, so NULL checks would also protect from reads and writes of the emulator's space. === 2.1 - Address space RAM space in Classic occupies lines 0-3 (1GB maximum) there are no special considerations other than proper paging ROM space (locked NRO) Classic: lines 2/4 (002xxxxx/004xxxxx in 24-bit) Quadra ROM is 1MB, 408xxxxx later systems map ROM space to line-F I/O line-5/00F addresses include VIA (timer), Sound Chip, SCSI, IDE, FDD Apple deliberately left 68F1xxxx unimplemented. Used by Even Better Bus Error to Bus Error if a program jumps to or uses nil. See the LowMemEqu.a interface and legacy PDF files for more addresses. == 2.2 - Virtual Memory A PMMU (or virtual) is required. The real exception Vector table is set up in an alternate location so Bus Errors can be handled first, normally to swap a mapped page, HDD write old, read new and continue. The Mac OS omits "Virtual Memory" in the Memory control panel if there are no drives w. enough space, or there's some kind of failure in MMU detection. Basilisk II (UAE) is able to fool the OS, where restarting w. VM-on does nothing (e.g., I set 48MB, but after restart still shows 32MB). == 2.3 - Video VRAM: locked page space at the final address space Valkyrie write implementations (Fx9...) (many non-VRAM address reads are irrelevant; some of these bytes go directly to status storage) DirectX and/or other video buffering methods support BE 15 bpp, so on that end no manual drawing is necessary. == 2.4 - Sound Classic: 11127 3/11 Hz, 8 bit mono mirror, no recording (may bomb) Sound Chip: 22254 6/11 Hz, 8 bit stereo writes, mono mirror reads (safe) Later: 44.1KHz, 16 bit stereo writes, stereo reads Modern (64-bit): 48/96KHz support, 32-bit floating-point single Sound Chip at line-5, post-increment per read/write, 1024 samples per buffer Left/right sample mirrors: x000-x3FF, x400-x7FF Offset zero should be used; some offsets do not reflect sample in/out. Status, Control: x800-xBFF, xC00-xFFF Wait/fill bit(s) delays reads/writes (may be 1 bit each) until a buffer is full (an interrupt may be triggered). Audio gain sets the recording amplitude. === 3.1 CPU This file does not offer a thorough CPU reference see ../downloads/ for the 68K assembly timer, containing additional info 68000 series (Motorola) - Classic CODE/PEF, discontinued bef. 68060 68000/68010: 24-bit only, no FPU or MMU 68020/68030: 24/32-bit modes, 68881/68882 matching FPU, 685xx MMU 68040: 32-bit only, FPU/MMU built-in 68LC040 is the "Low Cost" version--no FPU; 68EC040 has neither FPU nor MMU PowerPC (PPC) series (IBM/Apple) - Classic PEF/Carbon/OS X 601...603[e]/604[e]: 32-bit, implemented for 64-bit prototype 7xx (G3/G4/G5): 32/64-bit while some don't offer an FPU, the MMU is expected to be built-in Intel series - Carbon (emulated PPC)/OS X Core-Duo/Quad: 32/64-bit Neither 68K nor PPC have a bit #0 for the Program Counter; an Illegal Address exception will occur if a program attempts a jump to an address w. this bit on. == 3.2 - Debugging and correct CPU emulation Under pre-OS X, if you can't even get MacsBug 6.5.2 to run, checking CPU emulation may take longer in time, as you won't be able to step through instructions as normal. Weird/special behavior for some instructions: NEGX (or modern equivalent) never sets the Zero flag; it may only be cleared. Pre-68040 division on Overflow also sets the Negative flag. 68EC040 (no FPU/MMU) implementations requires the FP exception frame (evaluate addresses only), and MOVE16 instruction. Some co-processor stuff was partly nixed (fewer implementations are necessary from here). MOVE16: 16-byte boundary copy; four longs, all aligned, BE-irrelevant. Both Ax are updated blindly in post-i mode; one inc. reflected on same. Codes: F600(p,xA), F608(xA,p), F610(r,xA), F618(xA,r), F620(p,x1p0). == 3.3 - CPU caching 68020+ implementations call for some code cache considerations, but the '020 CPU only has a tiny cache for tiny loops (making flushing usually unnecessary. The 68030 has as much as 256 bytes joint cache. Upon that, the 68LC040 has 4KB data/code cache each, and only requires PMMU and code cache inst. basics (esp. for JIT compilation) -- CPUSH/CINV(L[ine]/P[age]/A[all]). == 3.4 The 68060 and unused instructions The last of the series was never made compatible w. the Mac, so this territory is only relevant to those eager to code this CPU anyway. There are a few 68060 instructions not available on the 68040: mcF5200: HALT 2564+FFFF, PULSE 4ACC+FFFF cpu32: LPSTOP(low-power stop) F800/01C0+FFFF(#w) mc68060-only: PLPAW F588+FFF8;PLPAR F5C8+FFF8 Only the 68020 carries two "module" instructions, CALLM and RTM. These instructions work with the PMMU in such a complex manner for form recognition that it was wise for Motorola to drop them, '030+. They use a stored state, and let the user decide how big the module is on the stack, but in a byte code instead of a word with LINK. Codes: CALLM 06C0+FFC0(#b,e), RTM 06C0+FF80(e). For patent tech. specs, relating to these two instructions and the PMMU, see sumobrainsolutions.com or FreePatentsOnline.com for <4763244-PMMU.txt>. === 4.1 - FPU Since the advent of SoftwareFPU, emulated FPU operations needn't be emulated, unless for speed. The Mac provides unimplemented FPU support for the 68040 FPU, as the complex instructions (e.g., FSIN and FEXP1) and constants were left out in the MC68040. I wrote my own FPU emulator years ago, but I broke XDBt trying to change the used data registers (didn't use equates as I should've). See sysinfo/fp68k.txt for more info and some Standard Apple Numeric Environment (SANE) implementations. === 5.1 - Timer The Microseconds trap pieces together values set in low-memory variables set at interrupt time; interrupts are disabled for this. The TickCount reads a variable incremented by the system-installed Vertical Blank (VBL) 60Hz timer. == 5.2 - Timed Interrupts Time Tasks run on milliseconds (to half-millisecond accuracy) or microseconds (passed as a negative to the insertion trap). Both VBLs and Time Tasks are timed interrupts that are set for execution when their decremented time has hit zero. Tasks to be called again are reinserted; constant-length timed tasks would basically reinsert themselves. Tasks at zero are called ASAP when its associated interrupt (in status register mask) is not disabled.