
  Assembling wms7_08.asm
0001                                ;
0002                                ; Written by Dallas E. Overturf 12-9-92
0003                                ;
0004                                ; Copyright December 1992 by Dallas E. Overturf.
0005                                ;
0006                                ; Questions Comments etc... On this program should be directed to the
0007                                ; author at the following address (If you wish a reply please send a SASE)
0008                                ;
0009                                ; Dallas E. Overturf
0010                                ; 267 Main St
0011                                ; Ashland, MA 01721 (USA)
0012                                ;
0013                                ; e-mail:  d_overturf@yahoo.com
0014                                ;
0015                                ;
0016                                ;		Memory Map for Williams Level 3-7 MPU
0017                                ;		(Includes all PIAs on mpu and driver)
0018                                ;
0019                                ;			ADDRESS
0020                                ;Device	| 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0021                                ;==============================================================================
0022                                ;IC19	|     0  0  0       0 1 x x x x x x x x	 5101	100-1FF Level 3-7 CMOS
0023                                ;------------------------------------------------------------------------------
0024                                ;IC13	|     0  0            0 0 x x x x x x x	 6810	00-7F Level 3-6 ram
0025                                ;------------------------------------------------------------------------------
0026                                ;IC13	|     0  0  1       x x x x x x x x x x	 2114	1000-13FF Level 7 ram
0027                                ;------------------------------------------------------------------------------
0028                                ;IC16	|     0  0            0 1 x x x x x x x	 6810	00-7F Level 3-6 ram
0029                                ;------------------------------------------------------------------------------
0030                                ;IC16	|     0  0  1       x x x x x x x x x x	 2114	1000-13FF Level 7 ram
0031                                ;------------------------------------------------------------------------------
0032                                ;PIA 1  |     0  1     1                    x x         2800-2803 Displays
0033                                ;------------------------------------------------------------------------------
0034                                ;PIA 2  |     0  1  1                       x x         3000-3003 switches
0035                                ;------------------------------------------------------------------------------
0036                                ;PIA 3  |     0  1        1                 x x         2400-2403 lamps
0037                                ;------------------------------------------------------------------------------
0038                                ;PIA 4  |     0  1          1               x x         2200-2203 solenoids
0039                                ;------------------------------------------------------------------------------
0040                                ;PIA 5  |     0  1            1             x x         2100-2103 L7 snd/commas
0041                                ;------------------------------------------------------------------------------
0042                                ;ic17_L7      1  1  1  x  x x x x x x x x x x x	 IC17 L7 7000-7FFF Program upper addresses.
0043                                ;------------------------------------------------------------------------------
0044                                ;ic17_L36     1  1  1  1  x x x x x x x x x x x  IC17 L346 7800-7FFF Program upper addresses.
0045                                ;------------------------------------------------------------------------------
0046                                ;ic20   |     1  1  1  x  x x x x x x x x x x x	 IC20	6800-6FFF Program.
0047                                ;------------------------------------------------------------------------------
0048                                ;ic14	|     1  1  0  0  x x x x x x x x x x x  IC14 	6000-67FF Program.
0049                                ;------------------------------------------------------------------------------
0050                                ;=============================================================================
0051                                
0052                                ;Our Test prom code goes into IC17.burn into address 7800-7FFF.  
0053                                
0054                                ;=============================================================================
0055                                ;Notes:  An 'x' indicates used for addressing, Nothing indicates don't care;
0056                                ; a '1' or a '0' indicates TRUE or FALSE address line state to enable the part.
0057                                ;CMOS map shown will work for levels 3-7; and is combined via commonalities
0058                                ;between 3-6 and 7.  Looking at just 3-6 or 7 you won't see this unless you
0059                                ;look at both.
0060                                ; 
0061                                ;
0062                                ; This code will do a pretty thorough test of the Williams MPU Level 7
0063                                ; memory/bus; it also loops on errors.  This should be a
0064                                ; reasonably sufficient check of the board prior to booting with actual
0065                                ; Williams Rom.  If this program completes without error then the tests
0066                                ; in the actual Williams Game Rom should be sufficient to find other
0067                                ; problems which are not likely to be memory/bus related such as 
0068                                ; stuck switch, display, and solenoid problems.
0069                                ; What this test will not do:
0070                                ;
0071                                ; 1.  	This test will not run with shorted data lines and will likely not
0072                                ; 	run with shorted address lines.  It can easily be used to identify
0073                                ;	most shorted address and/or data lines with the help of a logic
0074                                ;	analyzer and this listing.
0075                                ;
0076                                ; 2.	Contrary to Williams statements; that the mpu will pass selftest
0077                                ;	with the driver board disconnected; you MAY need the driver board 
0078                                ;	plugged in to run this test or the Williams Self Tests.  The
0079                                ;	reasoning behind this is as follows:
0080                                ;	Looking at a Williams Level 6 MPU you will find two unused locations
0081                                ;	at the bottom of the board near the driver board connector.  These
0082                                ;	two locations used to be at one time (according to the schematics
0083                                ;	part list) 4.7k pullups.  I have had MPUs fail the Williams
0084                                ;	self test on the 5101 ram with the driver disconnected but run
0085                                ;	with it connected.  This would imply that the driver is having
0086                                ;	an effect on the mpu; likely pulling up the address and data lines
0087                                ;	that these pullups once went to.  I have in fact partially proven
0088                                ;	this by adding in pullups on just the data lines to a board that
0089                                ;	was otherwise known good.  The board got past the 5101 check at
0090                                ;	that point and was partially able to strobe digits.  
0091                                ;	That was all the proof I needed and all I offer.  Beware and use a
0092                                ;	known good driver board when checking an mpu once the mpu has been
0093                                ;	partially checked out by itself and especially if it fails with
0094                                ;	a CMOS ram failure indication.  Note:  I have never seen this test
0095                                ;	prom fail the cmos test without the driver plugged in; only the
0096                                ;	Williams self tests so far.  It is possible that their self tests
0097                                ;	relied on the lines being pulled up; where we mask out unused lines
0098                                ;	when reading from the 5101 CMOS RAM. 
0099                                ;
0100                                ;
0101                                ; 3.	This test is most effective when used with a logic analyzer
0102                                ;	such as an HP 1630G or some other such analyzer.  With an analyzer
0103                                ;	and this listing it should be possible to see what bits are shorted
0104                                ;	in the case of a short.  With just a scope that will be difficult to
0105                                ;	see; though opens will be detectable provided the program prom 
0106                                ;	address	and data lines are intact to the mpu, the clock to the
0107                                ;	microprocessor is running, reset has been release and various other
0108                                ;	signals to/from the microprocessor are functioning.  The first thing
0109                                ;	to check if the program does not run is to check that as reset
0110                                ;	goes away from the microprocessor, that the processor does a fetch
0111                                ;	from address FFFE and FFFF and that the data comming out is in fact
0112                                ;	a 7800.  The 7800 is the starting address of this program.  The user
0113                                ;	should be able to follow the program from there and watch
0114                                ;	the microprocessor fetch and execute if necessary by tracing on
0115                                ;	selected points in the program till you find where the program goes
0116                                ;	into hyperspace.
0117                                ;
0118                                ;	Note:  All findable errors report in by writing at least once to the
0119                                ;		reset_vector of the microprocessor, address FFFE.  Error
0120                                ;		loops are setup to continue the program if the error goes
0121                                ;		away and the loop gets good data.  Thus a flakey problem is
0122                                ;		best caught using an analyzer and tracing on a write to
0123                                ;		address FFFE.
0124                                ;
0125                                ;		Note that error loops may or may not continually write to 
0126                                ;		the error_check_in address (FFFE).  All errors found will
0127                                ;		write to the error_check_in address at least once.  
0128                                ;		Thus when using	a logic analyzer, it is recommended that
0129                                ;		you look for error_check_in starting from power up, so that
0130                                ;		there is no chance that you miss it by already being in
0131                                ;		an error loop that does not repeat error_check_in.
0132                                ;
0133                                ;	Flash Card
0134                                ;
0135                                ;flash #1.  ram data bits are unique.
0136                                ;flash #2.  ram data bits unique in old space.
0137                                ;flash #3.  ram addresses are unique.
0138                                ;flash #4.  ram unique from cmos.
0139                                ;flash #5.  cmos data test passed.
0140                                ;flash #6.  cmos address test passed.
0141                                ;flash #7.  pia 1 on the mpu passed.
0142                                ;flash #8.  pia 5 on the mpu passed.
0143                                ;
0144                                ;
0145                                ;
0146                                ; Modification history
0147                                ;
0148                                ; 06-15-93	DEO Rev 4 readying for initial release.
0149                                ;		note:  do we want to add error action??
0150                                ;
0151                                ;		05-26-96 By DEO:  Fix a problem added in upgrading
0152                                ;		pia testing I believe.  pia_loop3 should not have
0153                                ;		done a comare just prior to the last bne before rts.
0154                                ;		The expected data was 0 the ldab will set the CCs and
0155                                ;		that is all that is needed.  We had a cba and were comparing
0156                                ;		AA or 55 to 0 which of course will always fail!
0157                                
0158                                ;
0159                                ;
0160                                ; End Modification history
0161                                ;
0162                                ;
0163                                ; Notes:
0164                                ;
0165                                ;	1.  ram also exists in other address ranges.  Of possible
0166                                ;		interest:	from 00-7F(old 6810 space)
0167                                ;				and 200-3FF(full level 7 access)
0168                                ;
0169                                ;	2.  Cmos exists from 100-1FF.  Note that the Level 7 schematics
0170                                ;		at least in Firepower II are INCORRECT!  They show
0171                                ;		address A7 on pin 5 of IC31.  IC31 pin 5 is in fact A9.
0172                                ;
0173                                ;
0174                                ;
0175                                
0176 0000                           old_ram_min	equ	$00	;Old ram space level 3,4,6. 00 also is 1000.
0177 007f                           old_ram_max	equ	$7F	;Old ram space level 3,4,6. 7F also is 107F.
0178 1000                           ram_min		equ	$1000	;ram consists of two 2114 1K X 4 RAM (ic13),
0179 13ff                           ram_max		equ	$13FF	;(ic13) tied together to form a 1K X 8 RAM.
0180 7000                           ic17_strt	equ	$7000	;Program upper addresses. All we really need.
0181 7800                           ic17_old_strt	equ	$7800	;Keep to 2K and put L3-6 and L-7 in one 2532.
0182 7fff                           ic17_end	equ	$7FFF	;Program upper addresses. All we really need.
0183 6800                           ic20_strt	equ	$6800	;Program.
0184 6fff                           ic20_end	equ	$6FFF	;Program.
0185 6000                           ic14_strt	equ	$6000	;Program.
0186 67ff                           ic14_end	equ	$67FF	;Program.
0187 0100                           cmos_min	equ	$100	;low addr for 5101.
0188 01ff                           cmos_max	equ	$1FF	;high addr for 5101.  See Notes above!
0189 2803                           pia1_mask	equ	$2803 	;mask for pia1. Displays/LED
0190 2800                           pia1_sel	equ	$2800 	;Enable for pia1. Display/LED
0191 3003                           pia2_mask	equ	$3003 	;mask for pia2. Switch Matrix.
0192 3000                           pia2_sel	equ	$3000 	;Enable for pia2. Switch Matrix.
0193 2403                           pia3_mask	equ	$2403 	;mask for pia3.  Lamps.
0194 2400                           pia3_sel	equ	$2400 	;Enable for pia3. Lamps.
0195 2203                           pia4_mask	equ	$2203 	;mask for pia4.  Solenoids.
0196 2200                           pia4_sel	equ	$2200	;Enable for pia4. Solenoids.
0197 2103                           pia5_mask	equ	$2103 	;mask for pia4.  Sound and Commas.
0198 2100                           pia5_sel	equ	$2100	;Enable for pia4. Sound and Commas.
0199 0000                           pia_reg_a_sel	equ	$00  ;Register A slections in PIA.  For DDRA and PRA
0200 0001                           cra_sel		equ	$01  ;control register A.
0201 0000                           pra_sel		equ	$00  ;For Peripheral Registrer A.
0202 0000                           ddra_sel	equ	$00  ;For DDRA.
0203 0002                           pia_reg_b_sel	equ	$02  ;Register B slections in PIA.  For DDRB and PRB
0204 0003                           crb_sel		equ	$03  ;control register B.
0205 0002                           prb_sel		equ	$02  ;For Peripheral Registrer B.
0206 0002                           ddrb_sel	equ	$02  ;For DDRA.
0207 0000                           pia_ddr_reg	equ	%00000000 ; access data direction reg access.
0208 0004                           pia_out_reg	equ	%00000100 ; access output reg access.
0209 0038                           led_on		equ	$38	;should turn on LED.  Sets CRA-2,3,4,5.
0210 0030                           led_off		equ	$30	;should turn off LED.
0211 0080                           led_bits	equ	$80	;led bits are PA4-PA7 set in ddra to use pra.
0212 0030                           led_bits_on	equ	$30	;led bits; PA4, PA5 set to light; set in pra.
0213 0000                           led_bits_off	equ	$00	;led bits; PA4, PA5 reset to clear; set in pra.
0214 fff8                           irq_vector	equ	$FFF8	; FFF8,FFF9  IRQ interrupt.
0215 fffa                           swi_vector	equ	$FFFA	; FFFA,FFFB SWI	interrupt.
0216 fffc                           nmi_vector	equ	$FFFC	; FFFC,FFFD NMI CLEAR SWITCH (SW 33).
0217 fffe                           reset_vector	equ	$FFFE	; FFFE,FFFF RESET vector for 68xx processors.
0218 0000                           loop_val	equ	$0	; see error_action settings, or flash_error.
0219 0001                           restart_val	equ	$1	; see error_action settings, or flash_error.
0220 0002                           halt_val	equ	$2	; see error_action settings, or flash_error.
0221 0004                           revision_val	equ	$4	; Revision.
0222                                
0223                                ;
0224                                ; THE FOLLOWING LOCATIONS ARE RESERVED IN THE 6810 AS PROGRAM VARIABLES
0225                                ; THEY MAY NOT BE ACCESSED UNTIL AFTER WE HAVE DECIDED THE 6810 IS OK.
0226                                ;
0227                                
0228                                ; Set stack in new level 7 Ram address space so that we may test
0229                                ; out old space using the stack.
0230                                ; We will address stack in the 12FF range as that is what we
0231                                ; have tested.  The top of the RAM may be used for Variables as needed.
0232                                ; once the RAM has been qualified.
0233                                
0234 11ff                           stack_strt	equ	ram_min+ram_max/2	;stack is 11FF-1000.
0235                                
0236                                ; Variable region exists from addr $1200 to addr $13FF.
0237 1200                           var_1		equ	$1200	; two bytes for first variable in call
0238 1202                           var_2		equ	$1202	; two bytes for second variable in call
0239 1204                           var_3		equ	$1204	; two bytes for third variable in call
0240 1206                           x_place		equ	$1206	; two bytes for allowing push of x.
0241 1208                           temp		equ	$1208	; two bytes used for local temp storage.
0242                                
0243                                ; define  some important space for address uniqness testing of 6810 RAM.
0244 1000                           temp_0		equ	ram_min		; two bytes of space at at ram_min.
0245                                
0246                                ;=============================================================================
0247                                
0248 7800                           	org 	ic17_old_strt	;start of program.
0249                                
0250                                ;	Note:  "error_action" is intended to always be at u6_strt
0251                                ;	for convenience and is the first byte of u6. 
0252                                ;	The second byte is revision val  The next few bytes or so are
0253                                ;	my id string followed by my copyright notice.
0254                                
0255                                error_action:
0256 7800 00                        	fcb	#loop_val	;set to restart_val; will cause 5 flashes on
0257                                				;error and then restart the test.  Set to 
0258                                				;loop_val; will loop on error.  If the error
0259                                				;goes away, the test will continue.  Set to
0260                                				;halt_val; will effectively halt the test.
0261                                				;See description of error_action.
0262                                
0263 7801 04                        	fcb	#revision_val	;Put rev in rom also in case we want to know.
0264                                
0265                                ;		Now put in my copyright notice.
0266                                
0267 7802 20 43 4f 50 59 52         	fcc	" COPYRIGHT DECEMBER 1992 BY DALLAS E. OVERTURF "
          49 47 48 54 20 44
          45 43 45 4d 42 45
          52 20 31 39 39 32
          20 42 59 20 44 41
          4c 4c 41 53 20 45
          2e 20 4f 56 45 52
          54 55 52 46 20
0268 7831 20 4d 59 20 57 49         	fcc	" MY WILLIAMS 7 TEST PROM "
          4c 4c 49 41 4d 53
          20 37 20 54 45 53
          54 20 50 52 4f 4d
          20
0269                                
0270                                ;	A Non Maskable Interrupt (switch 33) will restart at show_revision.
0271                                
0272                                show_revision:
0273                                
0274 784a c6 04                     	ldab	#revision_val	;b now has revision.
0275 784c ce 78 52                  	ldx	#revision_ret	;x has return address.
0276 784f 7e 7c 13                  	jmp	sflash_sp_svc	;
0277                                revision_ret:
0278 7852 86 02                     	ldaa	#2		;two times will be a very long wait.
0279                                revision_lp:
0280 7854 ce 7d 00                  	ldx	#32000		;long wait.
0281                                rev_x_lp:
0282 7857 09                        	dex			;dec wait count
0283 7858 26 fd                     	bne	rev_x_lp	;
0284 785a 4a                        	deca			;dec loop count.
0285 785b 26 f7                     	bne	#revision_lp	;branch if not done or fall through to start.
0286                                
0287                                start:
0288                                
0289                                	;1st write and or read some data and address patterns to see
0290                                	;that the bus is ok on the analyzer.
0291                                
0292 785d ce 00 00                  	ldx	#$0000		;An address to write to write to. = 0000.
0293 7860 86 00                     	ldaa	#$0		;some data to write= 00.
0294 7862 a7 00                     	staa	0,x		;unchecked data only to look at bus.
0295 7864 43                        	coma			;some data to write= FF.
0296 7865 a7 00                     	staa	0,x		;unchecked data only to look at bus.
0297 7867 86 55                     	ldaa	#$55		;some data to write= 55.
0298 7869 a7 00                     	staa	0,x		;unchecked data only to look at bus.
0299 786b 43                        	coma			;some data to write= AA.
0300 786c a7 00                     	staa	0,x		;unchecked data only to look at bus.
0301 786e ce 00 00                  	ldx	#$0000		;address pattern to read from.
0302 7871 a6 00                     	ldaa	0,x		;read address, don't care about data.
0303 7873 ce ff ff                  	ldx	#$FFFF		;address pattern to read from.
0304 7876 a6 00                     	ldaa	0,x		;read address, don't care about data.
0305 7878 ce 55 55                  	ldx 	#$5555		;address pattern to read from.
0306 787b a6 00                     	ldaa	0,x		;read address, don't care about data.
0307 787d ce aa aa                  	ldx 	#$AAAA		;address pattern to read from.
0308 7880 a6 00                     	ldaa	0,x		;read address, don't care about data.
0309                                
0310                                
0311                                
0312                                ;	The LED is ON, when the board is reset, for about 1/2 - 1 second.
0313                                ;	That is not to be confused with the first flash.
0314                                ;	Turn it off so we know we successfully entered our code.
0315                                ;	Successfull entry into prom will show two short flashes 
0316                                ;	not counting the flash for reset.  If there is any question of 
0317                                ;	the number of flashes, the diagnostic pushbutton on the mpu
0318                                ;	(lower of the two buttons) may be depressed to cause a non-maskable
0319                                ;	interrupt at any time to restart the program.  Since there is no
0320                                ;	reset the only flashes seen at that point should be real.
0321                                
0322                                
0323 7882 c6 01                     	ldab	#$1		;Flash routines expect a count in b.
0324 7884 ce 78 a4                  	ldx	#start_return	;x now has return address.
0325 7887 35                        	txs			;sp now has return address.
0326 7888 7e 7b f6                  	jmp	#flash_sp_ofent	;go turn off the light.
0327                                
0328                                ; 	Now we will do our 2 short flashes to show we have entered the code.
0329                                
0330                                pass:
0331                                
0332 788b ce 78 93                  	ldx	#pass_return	;x has return address.
0333 788e c6 02                     	ldab	#2		;flash count.  Double quick blink so we know
0334 7890 7e 7c 13                  	jmp	sflash_sp_svc	;we are in code and where start is on a pass.
0335                                pass_return:
0336                                
0337                                
0338                                
0339                                
0340                                ;	We init data in the CMOS ram to make sure that it will interfere
0341                                ;	with ram_testing if by chance it is not unique. Thus if
0342                                ;	bus is corrupted during ram testing; the user may
0343                                ;	remove the cmos ram to see if the diagnostic will get past that
0344                                ;	point.  If so the cmos enable circuitry should be check out.
0345                                
0346 7893 ce 01 00                  	ldx	#cmos_min	;setup to init cmos.
0347 7896 86 00                     	ldaa	#$0		;
0348                                cmos_init:
0349 7898 84 0f                     	anda	#$0f		;CMOS uses low 4 bits of data. Mask out unused.
0350 789a a7 00                     	staa	0,x		;write to cmos.  If cmos bad we find out later.
0351 789c 8b 03                     	adda	#$3		;this will cause bits to vary so odd even addr
0352                                				;sees all bits set and cleared.
0353 789e 08                        	inx			;next addr.
0354 789f 8c 02 00                  	cpx	#cmos_max+1	;check range.
0355 78a2 26 f4                     	bne	#cmos_init	;branch if not done; else fall through.
0356                                
0357                                ;=============================================================================
0358                                
0359                                start_return:
0360                                
0361 78a4 c6 02                     	ldab	#$02		;Two flashes on entry.
0362 78a6 ce 78 ad                  	ldx	#start_return1	;x now has return address.
0363 78a9 35                        	txs			;sp now has return address.
0364 78aa 7e 7c 13                  	jmp	#sflash_sp_svc	;Do flashes.
0365                                start_return1:
0366                                
0367                                
0368                                ; The first real test starts here.
0369                                
0370 78ad ce 10 00                  	ldx	#ram_min		; Start addr of RAM.
0371 78b0 86 00                     	ldaa	#$0
0372                                ram_data:
0373                                ;	ram_data attempts to check that each cell can hold any
0374                                ;	data pattern in the 6810.  address has not been qualified yet.
0375                                
0376                                
0377 78b2 ce 10 00                  	ldx	#ram_min
0378                                
0379                                ram_d_nextadr:
0380 78b5 86 00                     	ldaa	#$0		;aa will be expected data
0381                                				;start at zero so this must get zero on a read
0382 78b7 20 0b                     	bra	#ram_d_datlp	;
0383                                
0384                                ram_d_errlp:
0385 78b9 7f ff fe                  	clr	#reset_vector	;failure check in.  Write to read only space.
0386 78bc f6 78 00                  	ldab	error_action	;sets CCs.
0387 78bf 27 03                     	beq	#ram_d_datlp	;no flash error.
0388 78c1 7e 7b af                  	jmp	flash_error	;
0389                                
0390                                ram_d_datlp:
0391 78c4 a7 00                     	staa	0,x		;write to the 6810.
0392 78c6 e6 00                     	ldab	0,x		;read actual data from the 6810.
0393 78c8 11                        	cba			;compare a and b accumulators.
0394 78c9 26 ee                     	bne	#ram_d_errlp	;loop on the error till it clears.
0395 78cb 4c                        	inca			;increment a.
0396 78cc 26 f6                     	bne	#ram_d_datlp	;data is 00-FF on FF we roll to 00 indicating
0397                                				;we have checked all data on current address.
0398 78ce 08                        	inx			;inc x to next addr.
0399 78cf 8c 14 00                  	cpx	#ram_max+1	;if past max addr then we are done.
0400 78d2 26 e1                     	bne	#ram_d_nextadr	;not done; do next address, or fall through.
0401                                
0402 78d4 c6 01                     	ldab	#$1		;flash #1.  ram data bits are unique.
0403                                
0404 78d6 ce 78 dc                  	ldx	#ram_d_return	;x now has return address.
0405 78d9 7e 7b d6                  	jmp	#flash_sp_svc	;go flash.
0406                                ram_d_return:			;return here.
0407                                
0408                                ;=============================================================================
0409                                ;	This test tests that the RAM is accessable in old
0410                                ;	6810 RAM space.  This only matters if the board is
0411                                ;	to be downgraded to run MPU level 3,4,6 Code.
0412                                ;	If the ram_data test passed and this oram_data test
0413                                ;	fails, the error is most likely found at IC31 or IC32.
0414                                ;	See Notes Above on Schematic ERROR for IC31 pin 5.
0415                                ;	Old ram addresses are 00-7f.  This test is far from perfect
0416                                ;	but is a basic check the board can be downgraded.
0417                                ;	A board that works as a level 7 but failing a downgrade
0418                                ;	IC31 and IC32 and their inputs are suspect.
0419                                
0420                                
0421 78dc ce 00 00                  	ldx	#old_ram_min		; Start addr of RAM.
0422 78df 86 00                     	ldaa	#$0
0423                                oram_data:
0424                                ;	oram_data attempts to check that each cell can hold any
0425                                ;	data pattern in the 6810.  address has not been qualified yet.
0426                                
0427                                
0428 78e1 ce 00 00                  	ldx	#old_ram_min
0429                                
0430                                oram_d_nextadr:
0431 78e4 86 00                     	ldaa	#$0		;aa will be expected data
0432                                				;start at zero so this must get zero on a read
0433 78e6 20 0b                     	bra	#oram_d_datlp	;
0434                                
0435                                oram_d_errlp:
0436 78e8 7f ff fe                  	clr	#reset_vector	;failure check in.  Write to read only space.
0437 78eb f6 78 00                  	ldab	error_action	;sets CCs.
0438 78ee 27 03                     	beq	#oram_d_datlp	;no flash error.
0439 78f0 7e 7b af                  	jmp	flash_error	;
0440                                
0441                                oram_d_datlp:
0442 78f3 a7 00                     	staa	0,x		;write to the 6810.
0443 78f5 e6 00                     	ldab	0,x		;read actual data from the 6810.
0444 78f7 11                        	cba			;compare a and b accumulators.
0445 78f8 26 ee                     	bne	#oram_d_errlp	;loop on the error till it clears.
0446 78fa 4c                        	inca			;increment a.
0447 78fb 26 f6                     	bne	#oram_d_datlp	;data is 00-FF on FF we roll to 00 indicating
0448                                				;we have checked all data on current address.
0449 78fd 08                        	inx			;inc x to next addr.
0450 78fe 8c 00 80                  	cpx	#old_ram_max+1	;if past max addr then we are done.
0451 7901 26 e1                     	bne	#oram_d_nextadr	;not done; do next address, or fall through.
0452                                
0453 7903 c6 01                     	ldab	#$1		;flash #2.  ram data bits unique in old space.
0454                                
0455 7905 ce 79 0b                  	ldx	#oram_d_return	;x now has return address.
0456 7908 7e 7b d6                  	jmp	#flash_sp_svc	;go flash.
0457                                oram_d_return:			;return here.
0458                                
0459                                ;=============================================================================
0460                                
0461                                ;	This test will verify that locations zero and one in ram are unique
0462                                ;	from all other locations in ram.  Thus we will have identified two
0463                                ;	bytes of memory that can be used as stack space or temp storage in
0464                                ;	the full ram address uniqueness test which is an address equal data
0465                                ;	test.
0466                                ;	By using all data patterns we verify that there is no data line(s)
0467                                ;	shorted to an address line which would later confuse things for the
0468                                ;	four addresses in question.  Probably most address uniqueness problems
0469                                ;	will be caught here; however we will do adress equal data test later
0470                                ;	to be very safe.  Note:  Between this test and the ram_data_test; we
0471                                ;	really should not see data shorted to an address.
0472                                
0473                                
0474 790b 4f                        	clra		;aa holds pattern to write. Do all patterns. 00-FF.
0475                                ram_au0_part:
0476 790c ce 10 02                  	ldx	#ram_min+2
0477 790f 20 0b                     	bra	#ram_au0_loop
0478                                
0479                                ram_au0_err:
0480 7911 7f ff fe                  	clr	#reset_vector	;failure check in.  Write to read only space.
0481 7914 f6 78 00                  	ldab	error_action	;sets CCs.
0482 7917 27 03                     	beq	#ram_au0_loop	;no flash error.
0483 7919 7e 7b af                  	jmp	flash_error	;
0484                                
0485                                ram_au0_loop:
0486 791c 5f                        	clrb			;to clear temp locs. We need some temp space.
0487 791d f7 10 00                  	stab	ram_min		;temp loc 0.  Part of temp_0.  Used for
0488 7920 f7 10 01                  	stab	ram_min+1	;temp loc 1.  Part of temp_0.  Future storage.
0489 7923 a7 00                     	staa	0,x		;write test data to all other ram locations.
0490 7925 f6 10 00                  	ldab	ram_min		;temp loc 0.  This will set CCs.
0491 7928 26 e7                     	bne	ram_au0_err	;loop on error.
0492 792a f6 10 01                  	ldab	ram_min+1	;temp loc 1.  This will set CCs.
0493 792d 26 e2                     	bne	ram_au0_err	;loop on error.
0494 792f 4c                        	inca			;inc aa to next data pattern.
0495 7930 27 02                     	beq	#ram_au0_ckdone
0496 7932 20 e8                     	bra	#ram_au0_loop	;Do next data pattern.
0497                                
0498                                ram_au0_ckdone:
0499 7934 8c 13 ff                  	cpx	#ram_max	; check if really done.
0500 7937 27 04                     	beq	ram_au0_done	; yes we are really done.
0501 7939 08                        	inx	
0502 793a 4f                        	clra			; Start pattern at 00 again.
0503 793b 20 df                     	bra	#ram_au0_loop	;not done continue looping.
0504                                
0505                                ram_au0_done:
0506                                ;	ram Address Equal Data test.  Final adress uniqness test of ram.
0507                                ;	It is not expected that this test will ever likely fail except
0508                                ;	in the case of a bad 6810.  However this test has a scope loop
0509                                ;	in case strange circumstances are encountered and we fail due
0510                                ;	to something other than a bad 6810.
0511                                ;	The scope loop is only a repetative read of the failed location.
0512                                ;	Since the data should equal the address, then using a 2 channel
0513                                ;	scope it should be easy to look at the address being read; and
0514                                ;	what the data comming out is.  The data comming out will most
0515                                ;	likely not equal the address by a single bit.  That bit will
0516                                ;	most likely be the address bit that is bad going into the
0517                                ;	6810; assuming that the 6810 is known good, the address line
0518                                ;	in question should be checked for shorts to surronding signals.
0519                                
0520                                ram_aed_test:
0521 793d 86 ff                     	ldaa	#ram_max&$0FF
0522 793f ce 13 ff                  	ldx	#ram_max
0523                                
0524                                ram_aed_dec:
0525 7942 a7 00                     	staa	0,x		;write pattern to address.
0526 7944 4a                        	deca			;next pattern.
0527 7945 09                        	dex			;next address.
0528 7946 8c 10 01                  	cpx	#temp_0+1	;leave our two byte space alone!
0529 7949 26 f7                     	bne	ram_aed_dec	;done if equal else continue.
0530                                
0531                                ;	ram should now be completely address equal data less first two locs.
0532                                
0533 794b 86 02                     	ldaa	#temp_0+2	;get initial value in a register.
0534 794d ce 10 02                  	ldx	#temp_0+2	;get start address from temp storage.
0535                                
0536                                ram_aed_inc:
0537 7950 e6 00                     	ldab	0,x		;read 1st address.
0538 7952 11                        	cba			;compare expected in a, to actual in b.
0539 7953 26 0a                     	bne	ram_find_loc	;Try to find the conflict for a scope loop.
0540 7955 4c                        	inca			;next pattern.
0541 7956 08                        	inx			;next address.
0542 7957 8c 14 00                  	cpx	#ram_max+1	;done when we reach ram_max.
0543 795a 26 f4                     	bne	ram_aed_inc	;continue if not done or fall through and pass.
0544                                
0545                                ;	ram should now be completely address equal data, less first two locs.
0546                                
0547 795c 7e 79 de                  	jmp	ram_aed_passed	;no error, we passed.
0548                                
0549                                ;	On entry x is the location in error found as follows:
0550                                ;	The routine prior to this is expected to write data from max to
0551                                ;	min addresses and then do the check from min to max so that 
0552                                ;	temp_0 - 1 will be the highest address needed to find the error.
0553                                ;	If this policy is not adhered to then this routine's ability to
0554                                ;	localize the error will be compromised.
0555                                ;	Note:  Temp_0 occupies the first two bytes of ram thus it MUST BE
0556                                ;	gauranteed to to be uniqe to ram prior to using this routine.
0557                                
0558                                ram_find_loc:
0559 795f 4f                        	clra			;
0560 7960 a7 00                     	staa	0,x		;clear error location.
0561 7962 ff 10 00                  	stx	temp_0		;store away error loc for now.
0562 7965 86 aa                     	ldaa	#$AA		;Compliment of first pattern.  We do two.
0563                                
0564                                ram_au_nxt_dat:
0565 7967 43                        	coma			;compliment so 1st pattern will be 55.
0566 7968 ce 10 02                  	ldx	#temp_0+2	;initial loc we write to.
0567                                
0568                                ram_au_nxt_adr:
0569 796b a7 00                     	staa	0,x		;write to location then check error loc.
0570 796d 35                        	txs			;store x in sp for now.
0571 796e fe 10 00                  	ldx	temp_0		;get error loc into x.
0572 7971 e6 00                     	ldab	0,x		;check it.  This will set CCs.
0573 7973 30                        	tsx			;restore x from sp. This will not change CCs.
0574 7974 26 17                     	bne	ram_aed_found	;we will now go and try to loop on the error.
0575 7976 08                        	inx			;next address.  If x temp_0, we wrote up
0576 7977 bc 10 00                  	cpx	temp_0		;to temp_0 - 1 and cannot find the error.
0577 797a 2d ef                     	blt	ram_au_nxt_adr	;continue to next addr.
0578 797c 81 aa                     	cmpa	#$AA		;if AA then we are done.
0579 797e 26 e7                     	bne	ram_au_nxt_dat	;if only 55 then we need to do AA still.
0580 7980 20 1e                     	bra	ram_aed_unot	;We should never exit this routine unless
0581                                				;we could not find error for some reason.
0582                                				;there for we branch, flash and restart.
0583                                
0584                                ;	ram_f_loop expects the bad address in temp_0 and conflict addr in x.
0585                                ;	data written to find error will be in aa still.  aa has the data.
0586                                
0587                                ram_aed_floop:
0588 7982 7f ff fe                  	clr	#reset_vector	;failure check in.  Write to read only space.
0589 7985 f6 78 00                  	ldab	error_action	;sets CCs.
0590 7988 27 03                     	beq	#ram_aed_found	;no flash error.
0591 798a 7e 7b af                  	jmp	flash_error	;
0592                                
0593                                ram_aed_found:
0594 798d 35                        	txs			;hold x in sp.  Note x is unchanged.
0595 798e 5f                        	clrb			;
0596 798f fe 10 00                  	ldx	temp_0		;x has error loc.
0597 7992 e7 00                     	stab	0,x		;clear error loc.
0598 7994 30                        	tsx			;restore x.
0599 7995 a7 00                     	staa	0,x		;write to x, we expect to overwrite error loc.
0600 7997 35                        	txs			;hold x in sp.
0601 7998 fe 10 00                  	ldx	temp_0		;x has error loc.
0602 799b e6 00                     	ldab	0,x		;this will set CCs.
0603 799d 30                        	tsx			;restore x from sp.  This does not affect CCs.
0604 799e 26 e2                     	bne	ram_aed_floop	;if not equal we are seeing the error.
0605                                
0606                                ram_aed_unot:
0607                                
0608 79a0 c6 03                     	ldab	#$3		;setup to flash three times so we know
0609                                				;we lost the error.  We will restart.
0610                                
0611                                ram_zflash:
0612                                ;	attempt to flash the light. n times based on contents of ab.
0613                                
0614 79a2 ce 28 00                  	ldx	#pia1_sel	;x has pia1 enable base addr.  addr of pia1
0615 79a5 86 38                     	ldaa	#pia_ddr_reg+led_on	;set to select ddra, cra 3,4,5 set.
0616 79a7 a7 01                     	staa	cra_sel,x	;ddra is now selected, cra 3,4,5 now set.
0617 79a9 86 80                     	ldaa	#led_bits	;set bits 4 and 5 for led select in ddr.
0618 79ab a7 00                     	staa	ddra_sel,x	;setup mask in ddra.
0619 79ad 86 04                     	ldaa	#pia_out_reg	;bits for CRA to access PRA.
0620 79af a7 01                     	staa	cra_sel,x	;set CRA.
0621 79b1 86 30                     	ldaa	#led_bits_on	;try to light Both LEDs.
0622 79b3 a7 00                     	staa	pra_sel,x	;set bits in PRA.
0623 79b5 86 3c                     	ldaa	#pia_out_reg+led_on	;Should be 3C.
0624 79b7 a7 01                     	staa	cra_sel,x	;do it.  Should now be accessing outreg.
0625 79b9 a7 01                     	staa	cra_sel,x	;do it.  Twice to be sure. CA2 should be high.
0626                                
0627 79bb ce 27 10                  	ldx	#10000		;LED On count.
0628                                
0629                                ram_zflash_on:
0630                                
0631 79be 09                        	dex			; should decrement x by 1.
0632 79bf 26 fd                     	bne	#ram_zflash_on	; keep on for LED on count. 
0633                                
0634                                ;	setup to turn off now to complete flash.
0635                                
0636 79c1 ce 28 00                  	ldx	#pia1_sel	;x has pia1 enable base addr.  addr of pia1
0637 79c4 86 30                     	ldaa	#pia_ddr_reg+led_off	;set to select ddra, cra 2,3,4 set.
0638 79c6 a7 01                     	staa	cra_sel,x	;ddra is now selected, cra 2,3,4 now set.
0639 79c8 86 34                     	ldaa	#pia_out_reg+led_off	;Should be 34.
0640 79ca a7 01                     	staa	cra_sel,x	;do it.  Should now be accessing outreg.
0641 79cc a7 01                     	staa	cra_sel,x	;do it.  Twice to be sure. CA2 should be high.
0642 79ce 86 00                     	ldaa	#led_bits_off	;to reset pa4 pa5 and turn off LEDs.
0643 79d0 a7 00                     	staa	pra_sel,x	;PA4 AND PA5 SHOULD HAVE GONE LOW. LEDs OFF.
0644                                
0645 79d2 ce 27 10                  	ldx	#10000		;LED Off count.
0646                                
0647                                ram_zflash_off:
0648 79d5 09                        	dex			; should decrement x by 1.
0649 79d6 26 fd                     	bne	#ram_zflash_off	; keep off for LED off count. 
0650 79d8 5a                        	decb
0651 79d9 26 c7                     	bne	#ram_zflash	; go till done flashing; then fall through.
0652                                
0653 79db 7e 78 5d                  	jmp	start		;we will restart from scratch.
0654                                
0655                                
0656                                ;	The next test expects that ram has addr equal data pattern in it.
0657                                ;	make it so.
0658                                
0659                                ram_aed_passed:
0660 79de 86 00                     	ldaa	#$0
0661 79e0 ce 00 00                  	ldx	#$0
0662                                ram_set_loop:
0663 79e3 a7 00                     	staa	0,x
0664 79e5 08                        	inx			;next address.
0665 79e6 4c                        	inca			;next pattern.
0666 79e7 81 00                     	cmpa	#ram_max+1	;if equal then we are done.
0667 79e9 26 f8                     	bne	#ram_set_loop	;go write pattern.
0668                                
0669                                ;	ram should now be completely address equal data.
0670                                
0671 79eb c6 01                     	ldab	#$1		;flash #3.  ram addresses are unique.
0672                                				;we don't call flash svc yet till we check
0673                                				;that the ram is unique from other devices.
0674                                				;such as the 5101 CMOS ram.
0675 79ed ce 79 f3                  	ldx	#ram_aed_return	;x now has return address.
0676 79f0 7e 7b d6                  	jmp	#flash_sp_svc	;go flash.
0677                                ram_aed_return:
0678                                
0679                                ;=============================================================================
0680                                
0681                                ;	Verify that writing to cmos does not write to ram.
0682                                
0683                                ramcmos_uniq:
0684 79f3 ce 10 00                  	ldx	#ram_min	; start of ram.
0685 79f6 86 00                     	ldaa	#$0		; zero to clear.
0686                                
0687                                ramcmos_clr:			; setup ram data to known 00 is simplest.
0688 79f8 a7 00                     	staa	0,x		; clear ram.
0689 79fa 08                        	inx
0690 79fb 8c 14 00                  	cpx	#ram_max+1	; check if done.
0691 79fe 26 f8                     	bne	#ramcmos_clr	; continue or fall through.
0692 7a00 8e 01 ff                  	lds	#cmos_max	; high addr of device we are checking against.
0693                                				; sp grows from high to low.
0694                                ramcmos_lp:
0695 7a03 86 ff                     	ldaa	#$FF		; Any pattern besides zero will do here.
0696 7a05 36                        	psha			; This will write a byte to cmos.
0697 7a06 30                        	tsx			; x now has a copy of sp+1. sp is unchanged.
0698 7a07 8c 01 00                  	cpx	#cmos_min	; because got sp+1 this is a straight cmpare.
0699 7a0a 27 24                     	beq	#ramcmos_pass	; if done then pass.
0700                                
0701                                ramcmos_chk:
0702 7a0c ce 10 00                  	ldx	#ram_min	; Setup to check out ram.  All addrs SB 00.
0703                                
0704                                ramcmos_chklp:
0705 7a0f e6 00                     	ldab	0,x		; read device location.  This will set CCs.
0706 7a11 26 08                     	bne	#ramcmos_err	; if not zero goto error routine.
0707                                
0708                                ramcmos_reent:			; if error goes away in errloop then re-enter.
0709 7a13 08                        	inx			; inc x.
0710 7a14 8c 14 00                  	cpx	#ram_max+1	; check if done.
0711 7a17 26 f6                     	bne	#ramcmos_chklp	; loop if not done
0712 7a19 20 e8                     	bra	#ramcmos_lp	; current did not overwrite, next cmos address.
0713                                
0714                                ramcmos_err:
0715 7a1b 7f ff fe                  	clr	#reset_vector	;failure check in.  Write to read only space.
0716 7a1e f6 78 00                  	ldab	error_action	;sets CCs.
0717 7a21 27 03                     	beq	#ramcmos_errlp	;no flash error.
0718 7a23 7e 7b af                  	jmp	flash_error	;
0719                                
0720                                ramcmos_errlp:
0721 7a26 6f 00                     	clr	0,x		; clear overwritten location.
0722 7a28 34                        	des			; sp will always be fail addr+1. fix it.
0723 7a29 36                        	psha			; write to suspect location.
0724 7a2a e6 00                     	ldab	0,x		; check for failure.  This sets CCs.
0725 7a2c 26 f8                     	bne	#ramcmos_errlp	; continue to loop on error if failing.
0726 7a2e 20 e3                     	bra	#ramcmos_reent	; failure not solid;continue.
0727                                
0728                                ramcmos_pass:
0729                                
0730 7a30 c6 01                     	ldab	#$1		;flash #4.  ram unique from cmos.
0731 7a32 ce 7a 38                  	ldx	#ramcmos_return	;x now has return address.
0732 7a35 7e 7b d6                  	jmp	#flash_sp_svc	;go flash.
0733                                ramcmos_return:
0734                                
0735                                ;=============================================================================
0736                                
0737 7a38 8e 11 ff                  	lds	#stack_strt	;initialize stack pointer; stack is ready.
0738                                
0739                                ; This is the start of called routines; Ie the stack must be ready.
0740                                
0741                                
0742                                ;=============================================================================
0743                                
0744 7a3b bd 7a 70                  	jsr	cmos_data_test	;go test cmos data.
0745 7a3e c6 01                     	ldab	#$01		;setup for one flash.
0746 7a40 bd 7c 50                  	jsr	flash_svc	;flash #5.  cmos data test passed.
0747                                
0748 7a43 bd 7a 9c                  	jsr	cmos_addr_test	;go test cmos addressing.
0749 7a46 c6 01                     	ldab	#$01		;setup for one flash.
0750 7a48 bd 7c 50                  	jsr	flash_svc	;flash #6.  cmos address test passed.
0751                                
0752 7a4b ce 28 00                  	ldx	#pia1_sel	;setup to test the pia 1 on the mpu.
0753 7a4e ff 12 00                  	stx	var_1		;var_1 now has pia base address.
0754 7a51 bd 7b 4c                  	jsr	pia_test	;go do the test.
0755 7a54 c6 01                     	ldab	#$01		;setup for one flash.
0756 7a56 bd 7c 50                  	jsr	flash_svc	;flash #7.  pia 1 on the mpu passed.
0757                                
0758 7a59 ce 21 00                  	ldx	#pia5_sel	;setup to test the pia 5 on the mpu.
0759 7a5c ff 12 00                  	stx	var_1		;var_1 now has pia base address.
0760 7a5f bd 7b 4c                  	jsr	pia_test	;go do the test.
0761 7a62 c6 01                     	ldab	#$01		;setup for one flash.
0762 7a64 bd 7c 50                  	jsr	flash_svc	;flash #8.  pia 5 on the mpu passed.
0763                                
0764                                
0765                                
0766 7a67 ce 75 30                  	ldx	#30000
0767                                
0768                                delay:		;delay flashing for a moment before next pass of tests.
0769                                
0770 7a6a 09                        	dex			; should decrement x by 1.
0771 7a6b 26 fd                     	bne	#delay		; delay between passes.
0772 7a6d 7e 78 5d                  	jmp	start		; goto start.
0773                                
0774                                
0775                                ;=============================================================================
0776                                
0777                                
0778                                	; This is start of cmos testing of both data and addressing.
0779                                	; Because the 5101 CMOS Ram is only 4 bits wide; we take some
0780                                	; great pains to see to it that we find conflicting addresses
0781                                	; in the address uniqueness test for this part for a scope loop.
0782                                	; the pain however is well worth the gain for using a scope or
0783                                	; especially an analyzer.
0784                                	;
0785                                	; Note:  The CMOS is assumed to be a unique device at this point as
0786                                	; it has not interfered with any other test.  It most likely
0787                                	; would have messed up some other device test were it not unique.
0788                                
0789                                cmos_data_test:
0790                                
0791                                ;	cmos_data attempts to check that each cell can hold any
0792                                ;	data pattern in the 5101.  address has not been qualified yet.
0793                                
0794                                
0795 7a70 ce 01 00                  	ldx	#cmos_min
0796                                
0797                                cmos_d_nextadr:
0798 7a73 86 00                     	ldaa	#$0		;aa will be expected data
0799 7a75 c6 ff                     	ldab	#$ff		;ab will be actual. Init to anything else; we
0800                                				;start at zero so this must get zero on a read
0801 7a77 20 0b                     	bra	cmos_d_datloop	
0802                                
0803                                cmos_d_errloop:
0804 7a79 7f ff fe                  	clr	#reset_vector	;failure check in.  Write to read only space.
0805 7a7c f6 78 00                  	ldab	error_action	;sets CCs.
0806 7a7f 27 03                     	beq	#cmos_d_datloop	;no flash error.
0807 7a81 7e 7b af                  	jmp	flash_error	;
0808                                
0809                                cmos_d_datloop:
0810 7a84 84 0f                     	anda	#$0f		;5101 is only 4 bits wide.  Mask unused bits.
0811 7a86 a7 00                     	staa	0,x		;write to the 5101.
0812 7a88 e6 00                     	ldab	0,x		;read from the 5101.
0813 7a8a c4 0f                     	andb	#$0f		;5101 is only 4 bits wide.  Mask unused bits.
0814 7a8c 11                        	cba			;compare a and b accumulators.
0815 7a8d 26 ea                     	bne	#cmos_d_errloop	;loop on the error till it clears.
0816 7a8f 8b 01                     	adda	#$01		;inca on MSB side, lsb 4 bits stay zero.
0817 7a91 84 0f                     	anda	#$0f		;just to be sure.
0818 7a93 26 ef                     	bne	#cmos_d_datloop	;data is 00-FF on FF we roll to 00 indicating
0819                                				;we have checked all data on current address.
0820 7a95 08                        	inx			;inc x to next addr.
0821 7a96 8c 02 00                  	cpx	#cmos_max+1	;if past max addr then we are done.
0822 7a99 26 d8                     	bne	#cmos_d_nextadr	;not done; do next address.
0823                                
0824 7a9b 39                        	rts			;return to caller.
0825                                
0826                                ;===========================================================================
0827                                
0828                                cmos_addr_test:
0829 7a9c ce 01 00                  	ldx	#cmos_min		;5101 starting address
0830 7a9f 86 00                     	ldaa	#$0		;aa will be expected data
0831 7aa1 b7 12 00                  	staa	var_1		;Clear variable located in 6810 used for uniq.
0832 7aa4 c6 ff                     	ldab	#$ff		;ab will be actual. Init to anything else; we
0833                                				;start at zero so this must get zero on a read
0834 7aa6 20 0b                     	bra	#cmos_a_datloop
0835                                
0836                                cmos_a_errloop:
0837 7aa8 7f ff fe                  	clr	#reset_vector	;failure check in.  Write to read only space.
0838 7aab f6 78 00                  	ldab	error_action	;sets CCs.
0839 7aae 27 03                     	beq	#cmos_a_datloop	;no flash error.
0840 7ab0 7e 7b af                  	jmp	flash_error	;
0841                                
0842                                cmos_a_datloop:
0843 7ab3 bb 12 00                  	adda	var_1		;A+M->A var_1 allows us to do uniqueness.
0844 7ab6 84 0f                     	anda	#$0f		;5101 is only 4 bits wide.  Mask unused bits.
0845 7ab8 a7 00                     	staa	0,x		;write to the 5101.
0846 7aba e6 00                     	ldab	0,x		;read/verify data.
0847 7abc c4 0f                     	andb	#$0f		;5101 is only 4 bits wide.  Mask unused bits.
0848 7abe 11                        	cba			;compare a and b accumulators.
0849 7abf 26 e7                     	bne	#cmos_a_errloop	;loop on the error till it clears.
0850 7ac1 8b 01                     	adda	#$01		;inca. msb, already has the uniq cnt offset.
0851 7ac3 84 0f                     	anda	#$0f		;5101 is only 4 bits wide.  Mask unused bits.
0852 7ac5 26 0a                     	bne 	cmos_continue	;on 0 we will increment var_1.
0853 7ac7 f6 12 00                  	ldab	var_1		;get current cnt in b.
0854 7aca cb 01                     	addb	#$01		;inc b (really cnt) used to provide addr uniq.
0855 7acc c4 0f                     	andb	#$0f		;5101 is only 4 bits wide.  Mask unused bits.
0856 7ace f7 12 00                  	stab	var_1		;put new count back in cnt.
0857                                cmos_continue:
0858 7ad1 08                        	inx			;inc x to next addr.
0859 7ad2 8c 02 00                  	cpx	#cmos_max+1	;if past max addr then we are done.
0860 7ad5 26 dc                     	bne	#cmos_a_datloop	;not done; do next address.
0861                                
0862                                cmos_addr_uniq:
0863                                
0864                                cmos_uclr:
0865 7ad7 ce 01 00                  	ldx	#cmos_min		;Start addr of 5101.
0866 7ada 86 00                     	ldaa	#$0
0867                                
0868                                cmos_uclr_addr:
0869 7adc a7 00                     	staa	0,x		;clear 5101.
0870 7ade 08                        	inx			;inc x to next addr.
0871 7adf 8c 02 00                  	cpx	#cmos_max+1	;if past max addr then we are done.
0872 7ae2 26 f8                     	bne	#cmos_uclr_addr	;not done.
0873                                
0874 7ae4 ce 01 00                  	ldx	#cmos_min
0875 7ae7 86 0f                     	ldaa	#$0f		;pattern to write to 5101.
0876                                
0877                                cmos_uloop:
0878 7ae9 e6 00                     	ldab	0,x		;check before writing.
0879 7aeb c4 0f                     	andb	#$0f		;mask out unused bits.
0880 7aed c1 00                     	cmpb	#$0		;verify loc is zero.	
0881 7aef 26 09                     	bne	cmos_uerror	;go try to loop on error.
0882 7af1 a7 00                     	staa	0,x		;loc was zero; write pattern to loc.
0883 7af3 08                        	inx			;next loc.
0884 7af4 8c 02 00                  	cpx	#cmos_max+1	;check if done.
0885 7af7 26 f0                     	bne	cmos_uloop	;not done.
0886                                
0887 7af9 39                        	rts			;return to caller.
0888                                
0889                                cmos_uerror:
0890 7afa ff 12 00                  	stx	var_1		;loc that was in error.
0891 7afd 6f 00                     	clr	0,x		;clear error loc.
0892 7aff ce 01 00                  	ldx	#cmos_min	;setup to find location that overwrote
0893                                				;the location just stored in var_1.
0894 7b02 86 0f                     	ldaa	#$0f		;reload a with same data.
0895                                
0896                                cmos_find_loc:
0897                                
0898 7b04 a7 00                     	staa	0,x
0899 7b06 35                        	txs			;hold x in sp for a moment.
0900 7b07 fe 12 00                  	ldx	var_1		;now get fail addr to check.
0901 7b0a e6 00                     	ldab	0,x		;
0902 7b0c 30                        	tsx			;put x held in sp back into x.
0903 7b0d c4 0f                     	andb	#$0f		;mask out unused bits.
0904 7b0f ff 12 02                  	stx	var_2		;Addr in var_2 confilicts with addr in var_1.
0905 7b12 c1 00                     	cmpb	#$0		;check error loc was still zero.  If not,
0906 7b14 26 13                     	bne	cmos_uerr_loop	;then try again.
0907 7b16 08                        	inx			;try next loc.
0908 7b17 bc 12 00                  	cpx	var_1		;don't need to go past addr in var_1.
0909 7b1a 27 1d                     	beq	cmos_unot	;did not find bad address.	
0910                                
0911 7b1c 86 0f                     	ldaa	#$0f		;to be safe.
0912                                
0913                                cmos_uerr_lloop:
0914 7b1e 7f ff fe                  	clr	#reset_vector	;failure check in.  Write to read only space.
0915 7b21 f6 78 00                  	ldab	error_action	;sets CCs.
0916 7b24 27 03                     	beq	#cmos_uerr_loop	;no flash error.
0917 7b26 7e 7b af                  	jmp	flash_error	;
0918                                
0919                                cmos_uerr_loop:
0920                                		
0921 7b29 6f 00                     	clr	0,x		;clear the addr in var_2.
0922 7b2b fe 12 00                  	ldx	var_1		;address that destroyed data in loc var_2.
0923 7b2e a7 00                     	staa	0,x		;write to var_1 should wipe data in var_2 addr.
0924 7b30 fe 12 02                  	ldx	var_2		;check we destroyed data var_2 addr.
0925 7b33 e6 00                     	ldab	0,x		;read.
0926 7b35 c4 0f                     	andb	#$0f		;mask unused.
0927 7b37 26 e5                     	bne	cmos_uerr_lloop	;stay in as long as we are failing.
0928                                
0929                                cmos_unot:
0930 7b39 c6 03                     	ldab	#$3
0931 7b3b bd 7c a8                  	jsr	sflash_svc	;Flash 3 short so we know that the error was 
0932 7b3e 7e 78 5d                  	jmp	start		;not located, we will re-start the test.
0933                                
0934                                ;===========================================================================
0935                                
0936                                	; pia_test is a called routine.
0937                                	; var_1 on entry contains the base enable addr for the pia to test.
0938                                	; On error this call will loop on the error. On Pass it will return.
0939                                	; to the caller (depending on the setting of error_action).
0940                                
0941                                pia_test_err:
0942 7b41 7f ff fe                  	clr	#reset_vector	;failure check in.  Write to read only space.
0943 7b44 f6 78 00                  	ldab	error_action	;sets CCs.
0944 7b47 27 03                     	beq	#pia_test	;no flash error.
0945 7b49 7e 7b af                  	jmp	flash_error	;
0946                                
0947                                pia_test:
0948 7b4c fe 12 00                  	ldx	var_1		;x has pia enable base addr.
0949 7b4f 86 00                     	ldaa	#pia_ddr_reg	;access ddr reg.
0950 7b51 a7 01                     	staa	cra_sel,x	;set ddr access.  PIA is now setup.
0951 7b53 4f                        	clra			;
0952 7b54 a7 02                     	staa	pia_reg_b_sel,x	;should clear ddrb reg.
0953 7b56 86 aa                     	ldaa	#$AA		;test pattern.
0954 7b58 a7 00                     	staa	pia_reg_a_sel,x	;should write to ddra reg.
0955 7b5a e6 00                     	ldab	pia_reg_a_sel,x	;should read from ddra reg.
0956 7b5c 11                        	cba			;compare expected in A to actual in B.
0957 7b5d 26 e2                     	bne	#pia_test_err	;loop on error.
0958                                
0959 7b5f 4f                        	clra			;clear a reg to verify ddrb was unique in pia.
0960 7b60 e6 02                     	ldab	pia_reg_b_sel,x	;ddrb should still be clear if unique.
0961 7b62 11                        	cba			;compare expected in A to actual in B.
0962 7b63 26 dc                     	bne	#pia_test_err	;loop on error.  Not unique.
0963 7b65 20 0b                     	bra	#pia_loop1	;continue test.
0964                                
0965                                pia_loop1_err:
0966 7b67 7f ff fe                  	clr	#reset_vector	;failure check in.  Write to read only space.
0967 7b6a f6 78 00                  	ldab	error_action	;sets CCs.
0968 7b6d 27 03                     	beq	#pia_loop1	;no flash error.
0969 7b6f 7e 7b af                  	jmp	flash_error	;
0970                                
0971                                pia_loop1:
0972 7b72 86 55                     	ldaa	#$55		;test pattern.
0973 7b74 a7 00                     	staa	pia_reg_a_sel,x	;should write to ddra reg.
0974 7b76 e6 00                     	ldab	pia_reg_a_sel,x	;should read from ddra reg.
0975 7b78 11                        	cba			;compare expected in A to actual in B.
0976 7b79 26 ec                     	bne	#pia_loop1_err	;loop on error.
0977 7b7b 20 0b                     	bra	#pia_loop2	;continue test.
0978                                
0979                                pia_loop2_err:
0980 7b7d 7f ff fe                  	clr	#reset_vector	;failure check in.  Write to read only space.
0981 7b80 f6 78 00                  	ldab	error_action	;sets CCs.
0982 7b83 27 03                     	beq	#pia_loop2	;no flash error.
0983 7b85 7e 7b af                  	jmp	flash_error	;
0984                                
0985                                pia_loop2:			;start checking ddrb reg.
0986 7b88 4f                        	clra			;
0987 7b89 a7 00                     	staa	pia_reg_a_sel,x	;clear ddra for uniqueness check.
0988 7b8b 86 55                     	ldaa	#$55		;test pattern.
0989 7b8d a7 02                     	staa	pia_reg_b_sel,x	;should write to ddrb reg.
0990 7b8f e6 02                     	ldab	pia_reg_b_sel,x	;should read from ddrb reg.
0991 7b91 11                        	cba			;compare expected in A to actual in B.
0992 7b92 26 e9                     	bne	#pia_loop2_err	;loop on error.
0993 7b94 20 0b                     	bra	#pia_loop3	;continue testing.
0994                                
0995                                pia_loop3_err:
0996 7b96 7f ff fe                  	clr	#reset_vector	;failure check in.  Write to read only space.
0997 7b99 f6 78 00                  	ldab	error_action	;sets CCs.
0998 7b9c 27 03                     	beq	#pia_loop3	;no flash error.
0999 7b9e 7e 7b af                  	jmp	flash_error	;
1000                                
1001                                pia_loop3:	
1002 7ba1 86 aa                     	ldaa	#$AA		;test pattern.
1003 7ba3 a7 02                     	staa	pia_reg_b_sel,x	;should write to ddrb reg.
1004 7ba5 e6 02                     	ldab	pia_reg_b_sel,x	;should read from ddrb reg.
1005 7ba7 11                        	cba			;compare expected in A to actual in B.
1006 7ba8 26 ec                     	bne	#pia_loop3_err	;loop on error.
1007 7baa e6 00                     	ldab	pia_reg_a_sel,x	;ddra should still be clear. Sets CCs.
1008 7bac 26 cf                     	bne	#pia_loop2_err	;we loop back to 2 to see all writes in loop.
1009                                				;This error sets LED on??
1010 7bae 39                        	rts			;If here we passed.  Return to caller.
1011                                
1012                                
1013                                ;===========================================================================
1014                                
1015                                ;=============================================================================
1016                                ;
1017                                ;	Service type routines are below such as flashing the LEDs.
1018                                ;
1019                                ;=============================================================================
1020                                
1021                                ;===========================================================================
1022                                
1023                                	; flash_error.
1024                                	; This will set the b register to 5 flashes and jmp to
1025                                	; sflash_sp_svc.  This routine does not return, it restarts.
1026                                
1027                                
1028                                flash_error:			;we do not plan to return so we do much.
1029                                				;and the heck with the stack.  It matters not.
1030 7baf ce 4e 20                  	ldx	#20000		;delay so we can tell the difference.
1031                                				;when looping.
1032                                flash_err_delay:
1033 7bb2 09                        	dex
1034 7bb3 26 fd                     	bne	#flash_err_delay ; Delay to see flashes clearly.
1035                                
1036 7bb5 c6 05                     	ldab	#$5		;b now holds the number of times to flash.
1037 7bb7 ce 7b bd                  	ldx	#flash_err_ret	;x has return address.
1038 7bba 7e 7c 13                  	jmp	sflash_sp_svc	;Go flash the light 5 short times.
1039                                				;sflash_sp returns to caller in x.
1040                                flash_err_ret:
1041 7bbd b6 78 00                  	ldaa	error_action	;Find out what to do here.
1042 7bc0 81 00                     	cmpa	#loop_val	;
1043 7bc2 27 08                     	beq	#flash_error_rst	;go restart tests ie: loop.
1044 7bc4 81 02                     	cmpa	#halt_val	;
1045 7bc6 27 07                     	beq	#halt_loop	;effectively halt the testing.
1046 7bc8 81 01                     	cmpa	#restart_val	;
1047 7bca 27 00                     	beq	#flash_error_rst	;go restart tests.
1048                                				;any other value will currently restart also,
1049                                				;but is not guaranteed to do so in later
1050                                				;revisions.
1051                                flash_error_rst:
1052 7bcc 7e 78 5d                  	jmp	start		;flash complete, now restart from scratch.
1053                                
1054                                ;===========================================================================
1055                                
1056                                	;This loop does nothing and is an infinite loop on itself
1057                                	;as there is no halt instruction for the 6800.
1058                                
1059                                halt_loop:
1060 7bcf 7f ff fe                  	clr	#reset_vector	;failure check in.  Write to read only space.
1061                                halt_lp:
1062 7bd2 01                        	nop
1063 7bd3 01                        	nop
1064 7bd4 20 fc                     	bra	#halt_lp	;loop on nothing to simulate a halted program.
1065                                
1066                                
1067                                ;===========================================================================
1068                                
1069                                
1070                                
1071                                ;===========================================================================
1072                                
1073                                flash_sp_svc:
1074                                ;	Attempt to flash the light n times based on contents of ab.
1075                                ;
1076                                ;	On entry x has return address.  We need to store it into the
1077                                ;	sp and then we can restore it.  This routine does not use
1078                                ;	any stack space nor does it push or pull anything to or from
1079                                ;	the stack.  The SP itself is utilized as a holding register.
1080                                ;	This routine may not change the x register prior to the txs
1081                                ;	instruction and may not subsequently change the sp register.
1082                                
1083 7bd6 35                        	txs			; x is holding the return address, save in sp.
1084                                
1085                                flash_sp_lp:
1086                                
1087 7bd7 ce 28 00                  	ldx	#pia1_sel	;x has pia1 enable base addr.  addr of pia1
1088 7bda 86 38                     	ldaa	#pia_ddr_reg+led_on	;set to select ddra, cra 3,4,5 set.
1089 7bdc a7 01                     	staa	cra_sel,x	;ddra is now selected, cra 3,4,5 now set.
1090 7bde 86 80                     	ldaa	#led_bits	;set bits 4 and 5 for led select in ddr.
1091 7be0 a7 00                     	staa	ddra_sel,x	;setup mask in ddra.
1092 7be2 86 04                     	ldaa	#pia_out_reg	;bits for CRA to access PRA.
1093 7be4 a7 01                     	staa	cra_sel,x	;set CRA.
1094 7be6 86 30                     	ldaa	#led_bits_on	;try to light Both LEDs.
1095 7be8 a7 00                     	staa	pra_sel,x	;set bits in PRA.
1096 7bea 86 3c                     	ldaa	#pia_out_reg+led_on	;Should be 3C.
1097 7bec a7 01                     	staa	cra_sel,x	;do it.  Should now be accessing outreg.
1098 7bee a7 01                     	staa	cra_sel,x	;do it.  Twice to be sure. CA2 should be high.
1099                                
1100 7bf0 ce 75 30                  	ldx	#30000		;LED On count.
1101                                
1102                                flash_sp_on:
1103                                
1104 7bf3 09                        	dex			; should decrement x by 1.
1105 7bf4 26 fd                     	bne	#flash_sp_on	; keep on for LED on count. 
1106                                
1107                                ;	setup to turn off now to complete flash.
1108                                
1109                                flash_sp_ofent:			;flash_sp_ofent expects return addr in sp.
1110 7bf6 ce 28 00                  	ldx	#pia1_sel	;x has pia1 enable base addr.  addr of pia1
1111 7bf9 86 30                     	ldaa	#pia_ddr_reg+led_off	;set to select ddra, cra 2,3,4 set.
1112 7bfb a7 01                     	staa	cra_sel,x	;ddra is now selected, cra 2,3,4 now set.
1113 7bfd 86 34                     	ldaa	#pia_out_reg+led_off	;Should be 34.
1114 7bff a7 01                     	staa	cra_sel,x	;do it.  Should now be accessing outreg.
1115 7c01 a7 01                     	staa	cra_sel,x	;do it.  Twice to be sure. CA2 should be high.
1116 7c03 86 00                     	ldaa	#led_bits_off	;to reset pa4 pa5 and turn off LEDs.
1117 7c05 a7 00                     	staa	pra_sel,x	;PA4 AND PA5 SHOULD HAVE GONE LOW. LEDs OFF.
1118                                
1119 7c07 ce 75 30                  	ldx	#30000		;LED Off count.
1120                                
1121                                flash_sp_off:
1122 7c0a 09                        	dex			; should decrement x by 1.
1123 7c0b 26 fd                     	bne	#flash_sp_off	; keep off for LED off count. 
1124 7c0d 5a                        	decb
1125 7c0e 26 c7                     	bne	#flash_sp_lp	; go till done flashing.
1126                                
1127 7c10 30                        	tsx			; restore return address from the sp.
1128 7c11 6e 00                     	jmp	0,x		; return to caller.
1129                                
1130                                ;===========================================================================
1131                                
1132                                sflash_sp_svc:
1133                                ;	Attempt to flash the light n times based on contents of ab.
1134                                ;
1135                                ;	On entry x has return address.  We need to store it into the
1136                                ;	sp and then we can restore it.  This routine does not use
1137                                ;	any stack space nor does it push or pull anything to or from
1138                                ;	the stack.  The SP itself is utilized as a holding register.
1139                                ;	This routine may not change the x register prior to the txs
1140                                ;	instruction and may not subsequently change the sp register.
1141                                
1142 7c13 35                        	txs			; x is holding the return address, save in sp.
1143                                
1144                                sflash_sp_lp:
1145                                
1146 7c14 ce 28 00                  	ldx	#pia1_sel	;x has pia1 enable base addr.  addr of pia1
1147 7c17 86 38                     	ldaa	#pia_ddr_reg+led_on	;set to select ddra, cra 3,4,5 set.
1148 7c19 a7 01                     	staa	cra_sel,x	;ddra is now selected, cra 3,4,5 now set.
1149 7c1b 86 80                     	ldaa	#led_bits	;set bits 4 and 5 for led select in ddr.
1150 7c1d a7 00                     	staa	ddra_sel,x	;setup mask in ddra.
1151 7c1f 86 04                     	ldaa	#pia_out_reg	;bits for CRA to access PRA.
1152 7c21 a7 01                     	staa	cra_sel,x	;set CRA.
1153 7c23 86 30                     	ldaa	#led_bits_on	;try to light Both LEDs.
1154 7c25 a7 00                     	staa	pra_sel,x	;set bits in PRA.
1155 7c27 86 3c                     	ldaa	#pia_out_reg+led_on	;Should be 3C.
1156 7c29 a7 01                     	staa	cra_sel,x	;do it.  Should now be accessing outreg.
1157 7c2b a7 01                     	staa	cra_sel,x	;do it.  Twice to be sure. CA2 should be high.
1158                                
1159 7c2d ce 27 10                  	ldx	#10000		;LED On count.
1160                                
1161                                sflash_sp_on:
1162                                
1163 7c30 09                        	dex			; should decrement x by 1.
1164 7c31 26 fd                     	bne	#sflash_sp_on	; keep on for LED on count. 
1165                                
1166                                ;	setup to turn off now to complete flash.
1167                                
1168                                sflash_sp_ofent:		;sflash_sp_ofent expects return addr in sp.
1169 7c33 ce 28 00                  	ldx	#pia1_sel	;x has pia1 enable base addr.  addr of pia1
1170 7c36 86 30                     	ldaa	#pia_ddr_reg+led_off	;set to select ddra, cra 2,3,4 set.
1171 7c38 a7 01                     	staa	cra_sel,x	;ddra is now selected, cra 2,3,4 now set.
1172 7c3a 86 34                     	ldaa	#pia_out_reg+led_off	;Should be 34.
1173 7c3c a7 01                     	staa	cra_sel,x	;do it.  Should now be accessing outreg.
1174 7c3e a7 01                     	staa	cra_sel,x	;do it.  Twice to be sure. CA2 should be high.
1175 7c40 86 00                     	ldaa	#led_bits_off	;to reset pa4 pa5 and turn off LEDs.
1176 7c42 a7 00                     	staa	pra_sel,x	;PA4 AND PA5 SHOULD HAVE GONE LOW. LEDs OFF.
1177                                
1178 7c44 ce 27 10                  	ldx	#10000		;LED Off count.
1179                                
1180                                sflash_sp_off:
1181 7c47 09                        	dex			; should decrement x by 1.
1182 7c48 26 fd                     	bne	#sflash_sp_off	; keep off for LED off count. 
1183 7c4a 5a                        	decb
1184 7c4b 26 c7                     	bne	#sflash_sp_lp	; go till done flashing.
1185                                
1186 7c4d 30                        	tsx			; restore return address from the sp.
1187 7c4e 6e 00                     	jmp	0,x		; return to caller.
1188                                
1189                                ;===========================================================================
1190                                
1191                                flash_svc:
1192                                ;	attempt to flash the light. n times based on contents of b register.
1193                                
1194                                
1195 7c50 f7 12 08                  	stab	temp		;b has count need to hold b reg temporarily.
1196 7c53 36                        	psha			; 
1197 7c54 ff 12 06                  	stx	x_place		; setup to push x also.
1198 7c57 b6 12 06                  	ldaa	x_place		;
1199 7c5a f6 12 07                  	ldab	x_place+1	;
1200 7c5d 36                        	psha			; x high onto stack
1201 7c5e 37                        	pshb			; x low onto stack
1202 7c5f f6 12 08                  	ldab	temp		; b should now have the flash count again.
1203                                
1204                                flash_svc_lp:
1205 7c62 ce 28 00                  	ldx	#pia1_sel	;x has pia1 enable base addr.  addr of pia1
1206 7c65 86 38                     	ldaa	#pia_ddr_reg+led_on	;set to select ddra, cra 3,4,5 set.
1207 7c67 a7 01                     	staa	cra_sel,x	;ddra is now selected, cra 3,4,5 now set.
1208 7c69 86 80                     	ldaa	#led_bits	;set bits 4 and 5 for led select in ddr.
1209 7c6b a7 00                     	staa	ddra_sel,x	;setup mask in ddra.
1210 7c6d 86 04                     	ldaa	#pia_out_reg	;bits for CRA to access PRA.
1211 7c6f a7 01                     	staa	cra_sel,x	;set CRA.
1212 7c71 86 30                     	ldaa	#led_bits_on	;try to light Both LEDs.
1213 7c73 a7 00                     	staa	pra_sel,x	;set bits in PRA.
1214 7c75 86 3c                     	ldaa	#pia_out_reg+led_on	;Should be 3C.
1215 7c77 a7 01                     	staa	cra_sel,x	;do it.  Should now be accessing outreg.
1216 7c79 a7 01                     	staa	cra_sel,x	;do it.  Twice to be sure. CA2 should be high.
1217                                
1218 7c7b ce 75 30                  	ldx	#30000		;LED On count.
1219                                
1220                                flash_on:
1221                                
1222 7c7e 09                        	dex			; should decrement x by 1.
1223 7c7f 26 fd                     	bne	#flash_on	; keep on for LED on count. 
1224                                
1225                                ;	setup to turn off now to complete flash.
1226                                
1227 7c81 ce 28 00                  	ldx	#pia1_sel	;x has pia1 enable base addr.  addr of pia1
1228 7c84 86 30                     	ldaa	#pia_ddr_reg+led_off	;set to select ddra, cra 2,3,4 set.
1229 7c86 a7 01                     	staa	cra_sel,x	;ddra is now selected, cra 2,3,4 now set.
1230 7c88 86 34                     	ldaa	#pia_out_reg+led_off	;Should be 34.
1231 7c8a a7 01                     	staa	cra_sel,x	;do it.  Should now be accessing outreg.
1232 7c8c a7 01                     	staa	cra_sel,x	;do it.  Twice to be sure. CA2 should be high.
1233 7c8e 86 00                     	ldaa	#led_bits_off	;to reset pa4 pa5 and turn off LEDs.
1234 7c90 a7 00                     	staa	pra_sel,x	;PA4 AND PA5 SHOULD HAVE GONE LOW. LEDs OFF.
1235                                
1236 7c92 ce 75 30                  	ldx	#30000		;LED Off count.
1237                                
1238                                flash_off:
1239 7c95 09                        	dex			; should decrement x by 1.
1240 7c96 26 fd                     	bne	#flash_off	; keep off for LED off count. 
1241 7c98 5a                        	decb
1242 7c99 26 c7                     	bne	#flash_svc_lp	; go till done flashing.
1243                                
1244 7c9b 33                        	pulb			;restoring x.
1245 7c9c 32                        	pula			;restoring x.
1246 7c9d f7 12 07                  	stab	x_place+1	;restoring x.
1247 7ca0 b7 12 06                  	staa	x_place		;restoring x.
1248 7ca3 fe 12 06                  	ldx	x_place		;x is now restored.
1249 7ca6 32                        	pula			;restore a.
1250 7ca7 39                        	rts			; return to caller.
1251                                
1252                                ;===========================================================================
1253                                
1254                                sflash_svc:
1255                                ;	attempt to flash the light. n times based on contents of b register.
1256                                
1257                                
1258 7ca8 f7 12 08                  	stab	temp		;b has count need to hold b reg temporarily.
1259 7cab 36                        	psha			; 
1260 7cac ff 12 06                  	stx	x_place		; setup to push x also.
1261 7caf b6 12 06                  	ldaa	x_place		; 
1262 7cb2 f6 12 07                  	ldab	x_place+1	;
1263 7cb5 36                        	psha			; x high onto stack
1264 7cb6 37                        	pshb			; x low onto stack
1265 7cb7 f6 12 08                  	ldab	temp		; b should now have the flash count again.
1266                                
1267                                sflash_svc_lp:
1268 7cba ce 28 00                  	ldx	#pia1_sel	;x has pia1 enable base addr.  addr of pia1
1269 7cbd 86 38                     	ldaa	#pia_ddr_reg+led_on	;set to select ddra, cra 3,4,5 set.
1270 7cbf a7 01                     	staa	cra_sel,x	;ddra is now selected, cra 3,4,5 now set.
1271 7cc1 86 80                     	ldaa	#led_bits	;set bits 4 and 5 for led select in ddr.
1272 7cc3 a7 00                     	staa	ddra_sel,x	;setup mask in ddra.
1273 7cc5 86 04                     	ldaa	#pia_out_reg	;bits for CRA to access PRA.
1274 7cc7 a7 01                     	staa	cra_sel,x	;set CRA.
1275 7cc9 86 30                     	ldaa	#led_bits_on	;try to light Both LEDs.
1276 7ccb a7 00                     	staa	pra_sel,x	;set bits in PRA.
1277 7ccd 86 3c                     	ldaa	#pia_out_reg+led_on	;Should be 3C.
1278 7ccf a7 01                     	staa	cra_sel,x	;do it.  Should now be accessing outreg.
1279 7cd1 a7 01                     	staa	cra_sel,x	;do it.  Twice to be sure. CA2 should be high.
1280                                
1281 7cd3 ce 75 30                  	ldx	#30000		;LED On count.
1282                                
1283                                sflash_on:
1284                                
1285 7cd6 09                        	dex			; should decrement x by 1.
1286 7cd7 26 fd                     	bne	#sflash_on	; keep on for LED on count. 
1287                                
1288                                ;	setup to turn off now to complete flash.
1289                                
1290 7cd9 ce 28 00                  	ldx	#pia1_sel	;x has pia1 enable base addr.  addr of pia1
1291 7cdc 86 30                     	ldaa	#pia_ddr_reg+led_off	;set to select ddra, cra 2,3,4 set.
1292 7cde a7 01                     	staa	cra_sel,x	;ddra is now selected, cra 2,3,4 now set.
1293 7ce0 86 34                     	ldaa	#pia_out_reg+led_off	;Should be 34.
1294 7ce2 a7 01                     	staa	cra_sel,x	;do it.  Should now be accessing outreg.
1295 7ce4 a7 01                     	staa	cra_sel,x	;do it.  Twice to be sure. CA2 should be high.
1296 7ce6 86 00                     	ldaa	#led_bits_off	;to reset pa4 pa5 and turn off LEDs.
1297 7ce8 a7 00                     	staa	pra_sel,x	;PA4 AND PA5 SHOULD HAVE GONE LOW. LEDs OFF.
1298                                
1299 7cea ce 75 30                  	ldx	#30000		;LED Off count.
1300                                
1301                                sflash_off:
1302 7ced 09                        	dex			; should decrement x by 1.
1303 7cee 26 fd                     	bne	#sflash_off	; keep off for LED off count. 
1304 7cf0 5a                        	decb
1305 7cf1 26 c7                     	bne	#sflash_svc_lp	; go till done flashing.
1306                                
1307 7cf3 33                        	pulb			;restoring x.
1308 7cf4 32                        	pula			;restoring x.
1309 7cf5 f7 12 07                  	stab	x_place+1	;restoring x.
1310 7cf8 b7 12 06                  	staa	x_place		;restoring x.
1311 7cfb fe 12 06                  	ldx	x_place		;x is now restored.
1312 7cfe 32                        	pula			;restore a.
1313 7cff 39                        	rts			; return to caller.
1314                                
1315                                ;===========================================================================
1316                                
1317 7ff8                           	org	ic17_end-7	; start of 6800 vector table.
1318                                
1319                                	; currently we will point all vectors to start for now.
1320                                	; maybe at some time we will mess with them.
1321                                
1322                                
1323                                	; Currently we will point most vectors to start for now.
1324                                	; Some day we may toy some more with them.
1325                                
1326 7ff8 7b cf                     	fdb	halt_loop	; FFF8,FFF9 IRQ	 NOT USED CURRENTLY, HALT.
1327 7ffa 7b cf                     	fdb	halt_loop	; FFFA,FFFB SWI	 NOT USED CURRENTLY, HALT.
1328 7ffc 78 4a                     	fdb	show_revision	; FFFC,FFFD NMI CLEAR SWITCH (SW 33)
1329 7ffe 78 5d                     	fdb	start		; FFFE,FFFF RESET
1330                                
1331                                
1332                                ;===========================================================================

cmos_a_datloop   7ab3 *0842 0834 0839 0860 
cmos_a_errloop   7aa8 *0836 0849 
cmos_addr_test   7a9c *0828 0748 
cmos_addr_uniq   7ad7 *0862 
cmos_continue    7ad1 *0857 0852 
cmos_d_datloop   7a84 *0809 0801 0806 0818 
cmos_d_errloop   7a79 *0803 0815 
cmos_d_nextadr   7a73 *0797 0822 
cmos_data_test   7a70 *0789 0744 
cmos_find_loc    7b04 *0896 
cmos_init        7898 *0348 0355 
cmos_max         01ff *0188 0354 0692 0821 0859 0871 0884 
cmos_min         0100 *0187 0346 0698 0795 0829 0865 0874 0892 
cmos_uclr        7ad7 *0864 
cmos_uclr_addr   7adc *0868 0872 
cmos_uerr_lloop  7b1e *0913 0927 
cmos_uerr_loop   7b29 *0919 0906 0916 
cmos_uerror      7afa *0889 0881 
cmos_uloop       7ae9 *0877 0885 
cmos_unot        7b39 *0929 0909 
cra_sel          0001 *0200 0616 0620 0624 0625 0638 0640 0641 0950 1089 
                       1093 1097 1098 1112 1114 1115 1148 1152 1156 1157 1171 
                       1173 1174 1207 1211 1215 1216 1229 1231 1232 1270 1274 
                       1278 1279 1292 1294 1295 
crb_sel          0003 *0204 
ddra_sel         0000 *0202 0618 1091 1150 1209 1272 
ddrb_sel         0002 *0206 
delay            7a6a *0768 0771 
error_action     7800 *0255 0386 0437 0481 0589 0716 0805 0838 0915 0943 
                       0967 0981 0997 1041 
flash_err_delay  7bb2 *1032 1034 
flash_err_ret    7bbd *1040 1037 
flash_error      7baf *1028 0388 0439 0483 0591 0718 0807 0840 0917 0945 
                       0969 0983 0999 
flash_error_rst  7bcc *1051 1043 1047 
flash_off        7c95 *1238 1240 
flash_on         7c7e *1220 1223 
flash_sp_lp      7bd7 *1085 1125 
flash_sp_ofent   7bf6 *1109 0326 
flash_sp_off     7c0a *1121 1123 
flash_sp_on      7bf3 *1102 1105 
flash_sp_svc     7bd6 *1073 0405 0456 0676 0732 
flash_svc        7c50 *1191 0746 0750 0756 0762 
flash_svc_lp     7c62 *1204 1242 
halt_loop        7bcf *1059 1045 1326 1327 
halt_lp          7bd2 *1061 1064 
halt_val         0002 *0220 1044 
ic14_end         67ff *0186 
ic14_strt        6000 *0185 
ic17_end         7fff *0182 1317 
ic17_old_strt    7800 *0181 0248 
ic17_strt        7000 *0180 
ic20_end         6fff *0184 
ic20_strt        6800 *0183 
irq_vector       fff8 *0214 
led_bits         0080 *0211 0617 1090 1149 1208 1271 
led_bits_off     0000 *0213 0642 1116 1175 1233 1296 
led_bits_on      0030 *0212 0621 1094 1153 1212 1275 
led_off          0030 *0210 0637 0639 1111 1113 1170 1172 1228 1230 1291 
                       1293 
led_on           0038 *0209 0615 0623 1088 1096 1147 1155 1206 1214 1269 
                       1277 
loop_val         0000 *0218 0256 1042 
nmi_vector       fffc *0216 
old_ram_max      007f *0177 0450 
old_ram_min      0000 *0176 0421 0428 
oram_d_datlp     78f3 *0441 0433 0438 0447 
oram_d_errlp     78e8 *0435 0445 
oram_d_nextadr   78e4 *0430 0451 
oram_d_return    790b *0457 0455 
oram_data        78e1 *0423 
pass             788b *0330 
pass_return      7893 *0335 0332 
pia1_mask        2803 *0189 
pia1_sel         2800 *0190 0614 0636 0752 1087 1110 1146 1169 1205 1227 
                       1268 1290 
pia2_mask        3003 *0191 
pia2_sel         3000 *0192 
pia3_mask        2403 *0193 
pia3_sel         2400 *0194 
pia4_mask        2203 *0195 
pia4_sel         2200 *0196 
pia5_mask        2103 *0197 
pia5_sel         2100 *0198 0758 
pia_ddr_reg      0000 *0207 0615 0637 0949 1088 1111 1147 1170 1206 1228 
                       1269 1291 
pia_loop1        7b72 *0971 0963 0968 
pia_loop1_err    7b67 *0965 0976 
pia_loop2        7b88 *0985 0977 0982 
pia_loop2_err    7b7d *0979 0992 1008 
pia_loop3        7ba1 *1001 0993 0998 
pia_loop3_err    7b96 *0995 1006 
pia_out_reg      0004 *0208 0619 0623 0639 1092 1096 1113 1151 1155 1172 
                       1210 1214 1230 1273 1277 1293 
pia_reg_a_sel    0000 *0199 0954 0955 0973 0974 0987 1007 
pia_reg_b_sel    0002 *0203 0952 0960 0989 0990 1003 1004 
pia_test         7b4c *0947 0754 0760 0944 
pia_test_err     7b41 *0941 0957 0962 
pra_sel          0000 *0201 0622 0643 1095 1117 1154 1176 1213 1234 1276 
                       1297 
prb_sel          0002 *0205 
ram_aed_dec      7942 *0524 0529 
ram_aed_floop    7982 *0587 0604 
ram_aed_found    798d *0593 0574 0590 
ram_aed_inc      7950 *0536 0543 
ram_aed_passed   79de *0659 0547 
ram_aed_return   79f3 *0677 0675 
ram_aed_test     793d *0520 
ram_aed_unot     79a0 *0606 0580 
ram_au0_ckdone   7934 *0498 0495 
ram_au0_done     793d *0505 0500 
ram_au0_err      7911 *0479 0491 0493 
ram_au0_loop     791c *0485 0477 0482 0496 0503 
ram_au0_part     790c *0475 
ram_au_nxt_adr   796b *0568 0577 
ram_au_nxt_dat   7967 *0564 0579 
ram_d_datlp      78c4 *0390 0382 0387 0396 
ram_d_errlp      78b9 *0384 0394 
ram_d_nextadr    78b5 *0379 0400 
ram_d_return     78dc *0406 0404 
ram_data         78b2 *0372 
ram_find_loc     795f *0558 0539 
ram_max          13ff *0179 0234 0399 0499 0521 0522 0542 0666 0690 0710 
ram_min          1000 *0178 0234 0244 0370 0377 0476 0487 0488 0490 0492 
                       0684 0702 
ram_set_loop     79e3 *0662 0667 
ram_zflash       79a2 *0611 0651 
ram_zflash_off   79d5 *0647 0649 
ram_zflash_on    79be *0629 0632 
ramcmos_chk      7a0c *0701 
ramcmos_chklp    7a0f *0704 0711 
ramcmos_clr      79f8 *0687 0691 
ramcmos_err      7a1b *0714 0706 
ramcmos_errlp    7a26 *0720 0717 0725 
ramcmos_lp       7a03 *0694 0712 
ramcmos_pass     7a30 *0728 0699 
ramcmos_reent    7a13 *0708 0726 
ramcmos_return   7a38 *0733 0731 
ramcmos_uniq     79f3 *0683 
reset_vector     fffe *0217 0385 0436 0480 0588 0715 0804 0837 0914 0942 
                       0966 0980 0996 1060 
restart_val      0001 *0219 1046 
rev_x_lp         7857 *0281 0283 
revision_lp      7854 *0279 0285 
revision_ret     7852 *0277 0275 
revision_val     0004 *0221 0263 0274 
sflash_off       7ced *1301 1303 
sflash_on        7cd6 *1283 1286 
sflash_sp_lp     7c14 *1144 1184 
sflash_sp_ofent  7c33 *1168 
sflash_sp_off    7c47 *1180 1182 
sflash_sp_on     7c30 *1161 1164 
sflash_sp_svc    7c13 *1132 0276 0334 0364 1038 
sflash_svc       7ca8 *1254 0931 
sflash_svc_lp    7cba *1267 1305 
show_revision    784a *0272 1328 
stack_strt       11ff *0234 0737 
start            785d *0287 0653 0772 0932 1052 1329 
start_return     78a4 *0359 0324 
start_return1    78ad *0365 0362 
swi_vector       fffa *0215 
temp             1208 *0241 1195 1202 1258 1265 
temp_0           1000 *0244 0528 0533 0534 0561 0566 0571 0576 0596 0601 
var_1            1200 *0237 0753 0759 0831 0843 0853 0856 0890 0900 0908 
                       0922 0948 
var_2            1202 *0238 0904 0924 
var_3            1204 *0239 
x_place          1206 *0240 1197 1198 1199 1246 1247 1248 1260 1261 1262 
                       1309 1310 1311 


Number of errors 0
Number of warnings 0
