
  Assembling wilt21.asm
0001                                ;
0002                                ; Written by Dallas Overturf 12-9-92
0003                                ;
0004                                ; DEO:  Released to Public Domain Nov. 16, 1995
0005                                ;
0006                                ; Questions Comments etc... On this program should be directed to the
0007                                ; author at the following address (If you wish a reply please send a SASE)
0008                                ;
0009                                ; Dallas E. Overturf
0010                                ; 267 Main St
0011                                ; Ashland, MA 01721 (USA)
0012                                ;
0013                                ; e-mail:  overturf@vos.stratus.com
0014                                ;
0015                                ;
0016                                ;		Memory Map for Williams Level 3-7 MPU
0017                                ;		(Includes all PIAs on mpu and driver)
0018                                ;
0019                                ;			ADDRESS
0020                                ;Device	| 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0021                                ;==============================================================================
0022                                ;IC19	|     0  0  0       0 1 x x x x x x x x	 5101	100-1FF Level 3-7 CMOS
0023                                ;------------------------------------------------------------------------------
0024                                ;IC13	|     0  0            0 0 x x x x x x x	 6810	00-7F Level 3-6 ram
0025                                ;------------------------------------------------------------------------------
0026                                ;IC13	|     0  0  1       x x x x x x x x x x	 2114	1000-13FF Level 7 ram
0027                                ;------------------------------------------------------------------------------
0028                                ;IC16	|     0  0            0 1 x x x x x x x	 6810	00-7F Level 3-6 ram
0029                                ;------------------------------------------------------------------------------
0030                                ;IC16	|     0  0  1       x x x x x x x x x x	 2114	1000-13FF Level 7 ram
0031                                ;------------------------------------------------------------------------------
0032                                ;PIA 1  |     0  1     1                    x x         2800-2803 Displays
0033                                ;------------------------------------------------------------------------------
0034                                ;PIA 2  |     0  1  1                       x x         3000-3003 switches
0035                                ;------------------------------------------------------------------------------
0036                                ;PIA 3  |     0  1        1                 x x         2400-2403 lamps
0037                                ;------------------------------------------------------------------------------
0038                                ;PIA 4  |     0  1          1               x x         2200-2203 solenoids
0039                                ;------------------------------------------------------------------------------
0040                                ;PIA 5  |     0  1            1             x x         2100-2103 L7 snd/commas
0041                                ;------------------------------------------------------------------------------
0042                                ;ic17_L7      1  1  1  x  x x x x x x x x x x x	 IC17 L7 7000-7FFF Program upper addresses.
0043                                ;------------------------------------------------------------------------------
0044                                ;ic17_L36     1  1  1  1  x x x x x x x x x x x  IC17 L346 7800-7FFF Program upper addresses.
0045                                ;------------------------------------------------------------------------------
0046                                ;ic20    |     1  1  1  x  x x x x x x x x x x x	 IC20	6800-6FFF Program.
0047                                ;------------------------------------------------------------------------------
0048                                ;ic14	|     1  1  0  0  x x x x x x x x x x x  IC14 	6000-67FF Program.
0049                                ;------------------------------------------------------------------------------
0050                                ;=============================================================================
0051                                
0052                                ;Our Test prom code goes into IC17.burn into address 7800-7FFF.  
0053                                
0054                                ;=============================================================================
0055                                ;Notes:  An 'x' indicates used for addressing, Nothing indicates don't care;
0056                                ; a '1' or a '0' indicates TRUE or FALSE address line state to enable the part.
0057                                ;CMOS map shown will work for levels 3-7; and is combined via commonalities
0058                                ;between 3-6 and 7.  Looking at just 3-6 or 7 you won't see this unless you
0059                                ;look at both.
0060                                ; 
0061                                ; This code will do a thorough test of the Williams MPU Level 3-6
0062                                ; memory/bus; with scope loops on errors.  This should be a
0063                                ; reasonably sufficient check of the board prior to booting with actual
0064                                ; Williams Rom.  If this program completes without error then the tests
0065                                ; in the actual Williams Game Rom should be sufficient to find other
0066                                ; problems which are not likely to be memory/bus related such as 
0067                                ; stuck switch, display, and solenoid problems.
0068                                ; What this test will not do:
0069                                ;
0070                                ;
0071                                ; 1.  	This test will not run with shorted data lines and will likely not
0072                                ; 	run with shorted address lines.  It can easily be used to identify
0073                                ;	most shorted address and/or data lines with the help of a logic
0074                                ;	analyzer and this listing.
0075                                ;
0076                                ; 2.	Contrary to Williams statements; that the mpu will pass selftest
0077                                ;	with the driver board disconnected; you MAY need the driver board 
0078                                ;	plugged in to run this test or the Williams Self Tests.  The
0079                                ;	reasoning behind this is as follows:
0080                                ;	Looking at a Williams Level 6 MPU you will find two unused locations
0081                                ;	at the bottom of the board near the driver board connector.  These
0082                                ;	two locations used to be at one time (according to the schematics
0083                                ;	part list) 4.7k pullups.  I have had MPUs fail the Williams
0084                                ;	self test on the 5101 ram with the driver disconnected but run
0085                                ;	with it connected.  This would imply that the driver is having
0086                                ;	an effect on the mpu; likely pulling up the address and data lines
0087                                ;	that these pullups once went to.  I have in fact partially proven
0088                                ;	this by adding in pullups on just the data lines to a board that
0089                                ;	was otherwise known good.  The board got past the 5101 check at
0090                                ;	that point and was partially able to strobe digits.  
0091                                ;	That was all the proof I needed and all I offer.  Beware and use a
0092                                ;	known good driver board when checking an mpu once the mpu has been
0093                                ;	partially checked out by itself and especially if it fails with
0094                                ;	a CMOS ram failure indication.
0095                                ;
0096                                ; 3.	This test is most effective when used with a logic analyzer
0097                                ;	such as an HP 1630 or some other such analyzer.  With an analyzer
0098                                ;	and this listing it should be possible to see what bits are shorted
0099                                ;	in the case of a short.  With just a scope that will be difficult to
0100                                ;	see; though opens will be detectable provided the program prom 
0101                                ;	address	and data lines are intact to the mpu, the clock to the
0102                                ;	microprocessor is running, reset has been release and various other
0103                                ;	signals to/from the microprocessor are functioning.  The first thing
0104                                ;	to check if the program does not run is to check that as reset
0105                                ;	goes away from the microprocessor, that the processor does a fetch
0106                                ;	from address FFFE and FFFF and that the data comming out is in fact
0107                                ;	a 7800.  The 7800 is the starting address of this program.  The user
0108                                ;	should be able to follow the program from there and watch
0109                                ;	the microprocessor fetch and execute if necessary by tracing on
0110                                ;	selected points in the program till you find where the program goes
0111                                ;	into hyperspace.
0112                                ;
0113                                ;	Note:  All findable errors report in by writing once to the
0114                                ;		reset_vector of the microprocessor, address FFFE.  Error
0115                                ;		loops are setup to continue the program if the error goes
0116                                ;		away and the loop gets good data.  Thus a flakey problem is
0117                                ;		best caught using an analyzer and tracing on a write to
0118                                ;		address FFFE.
0119                                ;
0120                                ;		Note that error loops may or may not continually write to 
0121                                ;		the error check in address (FFFE).  All errors found will
0122                                ;		write to the error check in address at least once.  
0123                                ;		Thus when using	a logic analyzer, it is recommended that
0124                                ;		you look for error check in starting from power up so that
0125                                ;		there is no chance that you miss it by already being in
0126                                ;		an error loop that does not repeat error checkin.
0127                                ;
0128                                ; Testing Notes:
0129                                ;
0130                                ;	This test prom is placed into socket U17 to be used.
0131                                ;	Note socket u17 must be jumpered to match the prom type used.
0132                                ;	If this prom code is put into a 2732 it may be used in a u17
0133                                ;	socket that is jumpered as a 2716 by programming the upper half
0134                                ;	of the 2732 from 0800 - 0FFF
0135                                ;
0136                                ;	The test prom should be in the socket that will be enabled by
0137                                ;	an address of FFFE.  (the reset vector of the 6800).
0138                                ;
0139                                ;	Programming the code into an EPROM:
0140                                ;	For a 2716 just program it in normal (IE: start address is 0000).
0141                                ;	If your burner requires an end address, it is 07FF.
0142                                ;
0143                                ;	For a 2732 or a 2532 the start address is 0800 (this means 0000-07FF
0144                                ;	remain blank.  If your burner requires an end address, it is 0FFF.
0145                                ;
0146                                ;	NOTE:  If the binary file of this program is larger than 2048 bytes;
0147                                ;	and the file starts at address 0000; then you will need to give your
0148                                ;	prom programmer a starting address within the binary file as well to
0149                                ;	start taking data from.  In this case you need to give it address
0150                                ;	7800 which will be the offset (in hexadecimal) of the start of code
0151                                ;	in the binary file.
0152                                ;
0153                                ;
0154                                ;	It is recommended that you verify the prom in a known good board
0155                                ;	prior to attempting to use it on a bad board!
0156                                ;
0157                                ;	Things of that may keep you from comming up and working correctly
0158                                ;	on the game rom that are untested in this game.
0159                                ;	INTERRUPTS!!  This test program specifically does not test program
0160                                ;	interrupts (the IRQ lines on the 6800 and PIAs).
0161                                ;
0162                                ;
0163                                ; Modification history
0164                                ;
0165                                ;		12-28-92 Last development file is wilt18.asm
0166                                ;		Remove Development history.  Set revision_val to 2.
0167                                ;		Add in revision and error_action routines.
0168                                ;		setup jmp to flash_error after checkin.
0169                                ;		File is wilt19.asm  Revision is 2. 
0170                                ;
0171                                ;		04-15-93 Added up front dummy reads and writes to allow
0172                                ;		us to basically verify addr and data buses are okay
0173                                ;		prior to hitting any real routines.  These are unchecked.
0174                                ;
0175                                ;		05-26-96 By DEO:  Fix a problem added in upgrading
0176                                ;		pia testing I believe.  pia_loop3 should not have
0177                                ;		done a comare just prior to the last bne before rts.
0178                                ;		The expected data was 0 the ldab will set the CCs and
0179                                ;		that is all that is needed.  We had a cba and were comparing
0180                                ;		AA or 55 to 0 which of course will always fail!
0181                                ;
0182                                ;
0183                                ; End Modification history
0184                                ;
0185                                ;
0186                                ;
0187                                ;	Notes:
0188                                ;		1.  When a 6802 microprocessor is used and ram1 is not
0189                                ;			per Williams schematics notes: if any ram1 test
0190                                ;			fails; then the processor should be changed if
0191                                ;			it is not absolutely known good as ram1 exists
0192                                ;			within the 6802 processor.  Also it would be
0193                                ;			suggested that the processor jumper for ram1 out
0194                                ;			is checked to be correct.  (Pin 36 of the 6802
0195                                ;			"RE" must be pulled up to enable the 6802
0196                                ;			internal RAM or if not used Pin 36 should be
0197                                ;			tied to ground.)
0198                                ;			
0199                                ;
0200                                ;
0201                                ;
0202                                ;
0203                                ;
0204                                
0205 7800                           ic17_strt	equ	$7800	
0206 7fff                           ic17_end	equ	$7fff	
0207 7000                           ic20_strt	equ	$7000	
0208 77ff                           ic20_end	equ	$77ff	
0209 0000                           ram1_min	equ	$0	;low addr for 6810. In 6802 or 6810 if 6808. 
0210 007f                           ram1_max	equ	$7f	;high addr for 6810. In 6802 or 6810 if 6808.  
0211 0080                           ram2_min	equ	$80	;low addr for 6810. Second Ram.
0212 00ff                           ram2_max	equ	$ff	;high addr for 6810. Second Ram.
0213 0100                           cmos_min	equ	$100	;low addr for 5101.
0214 01ff                           cmos_max	equ	$1ff	;high addr for 5101.
0215 2803                           pia1_mask	equ	$2803 	;mask for pia1. Displays/LED
0216 2800                           pia1_sel	equ	$2800 	;Enable for pia1. Display/LED
0217 3003                           pia2_mask	equ	$3003 	;mask for pia2. Switch Matrix.
0218 3000                           pia2_sel	equ	$3000 	;Enable for pia2. Switch Matrix.
0219 2403                           pia3_mask	equ	$2403 	;mask for pia3.  Lamps.
0220 2400                           pia3_sel	equ	$2400 	;Enable for pia3. Lamps.
0221 2203                           pia4_mask	equ	$2203 	;mask for pia4.  Solenoids.
0222 2200                           pia4_sel	equ	$2200	;Enable for pia4. Solenoids.
0223 0000                           pia_reg_a_sel	equ	$00  ;Register A slections in PIA.  For DDRA and PRA
0224 0001                           cra_sel		equ	$01  ;control register A.
0225 0000                           pra_sel		equ	$00  ;For Peripheral Registrer A.
0226 0000                           ddra_sel	equ	$00  ;For DDRA.
0227 0002                           pia_reg_b_sel	equ	$02  ;Register B slections in PIA.  For DDRB and PRB
0228 0003                           crb_sel		equ	$03  ;control register B.
0229 0002                           prb_sel		equ	$02  ;For Peripheral Registrer B.
0230 0002                           ddrb_sel	equ	$02  ;For DDRA.
0231                                ;  NOTE these next two are specified in binary so you know the syntax.
0232                                ;  specifying in hex is probably easier to look at and read.% is binary. 
0233 0000                           pia_ddr_reg	equ	%00000000 ; access data direction reg access.
0234 0004                           pia_out_reg	equ	%00000100 ; access output reg access. binary = $0004
0235                                
0236 0020                           led_1_bit	equ	$20	;Turns On LED 1. Upper LED set in ddra and pra.
0237 0010                           led_2_bit	equ	$10	;Turns On LED 2. Lower LED set in ddra and pra.
0238 0038                           led_on		equ	$38	;should turn on LED.  Sets CRA-2,3,4,5.
0239 0030                           led_off		equ	$30	;should turn off LED.
0240 0030                           led_bits	equ	$30	;led bits are PA4, PA5 set in ddra to use pra.
0241 0030                           led_bits_on	equ	$30	;led bits; PA4, PA5 set to light; set in pra.
0242 0000                           led_bits_off	equ	$00	;led bits; PA4, PA5 reset to clear; set in pra.
0243 fff8                           irq_vector	equ	$FFF8	; FFF8,FFF9  IRQ interrupt.
0244 fffa                           swi_vector	equ	$FFFA	; FFFA,FFFB SWI	interrupt.
0245 fffc                           nmi_vector	equ	$FFFC	; FFFC,FFFD NMI CLEAR SWITCH (SW 33).
0246 fffe                           reset_vector	equ	$FFFE	; FFFE,FFFF RESET vector for 68xx processors.
0247 0000                           loop_val	equ	$0	; see error_action settings, or flash_error.
0248 0001                           restart_val	equ	$1	; see error_action settings, or flash_error.
0249 0002                           halt_val	equ	$2	; see error_action settings, or flash_error.
0250 0002                           revision_val	equ	$2	; Revision.
0251                                
0252                                ;
0253                                ; THE FOLLOWING LOCATIONS ARE RESERVED IN THE 6810 AS PROGRAM VARIABLES
0254                                ; THEY MAY NOT BE ACCESSED UNTIL AFTER WE HAVE DECIDED THE 6810 IS OK.
0255                                ;
0256                                
0257 004f                           stack_strt	equ	$4f	; stack will be from 4f to 0, with the
0258                                				; top $30 locations reserved for variables.
0259                                
0260                                ; Variable region exists from addr $50 to addr $7f.
0261 0050                           var_1		equ	$50	; two bytes for first variable in call
0262 0052                           var_2		equ	$52	; two bytes for second variable in call
0263 0054                           var_3		equ	$54	; two bytes for third variable in call
0264 0056                           x_place		equ	$56	; two bytes for allowing push of x.
0265 0058                           temp		equ	$58	; two bytes used for local temp storage.
0266                                
0267                                ; define  some important space for address uniqness testing of 6810 RAM.
0268 0000                           temp_0		equ	ram1_min	; two bytes of space at 00 and 01 in RAM.
0269                                
0270                                ;=============================================================================
0271                                
0272 7800                           	org 	ic17_strt	;start of program.
0273                                
0274                                ;	Note:  "error_action" is intended to always be at u6_strt
0275                                ;	for convenience and is the first byte of u6.  The next few
0276                                ;	bytes or so are the REV string.  Followed by copyright notice.
0277                                
0278                                error_action:
0279 7800 00                        	fcb	#loop_val	;set to restart_val; will cause 5 flashes on
0280                                				;error and then restart the test.  Set to 
0281                                				;loop_val; will loop on error.  If the error
0282                                				;goes away, the test will continue.  Set to
0283                                				;halt_val; will effectively halt the test.
0284                                				;See description of error_action.
0285                                
0286 7801 02                        	fcb	#revision_val	;Put rev in rom also in case we want to know.
0287                                
0288                                ;		Now put in my copyright notice.
0289                                
0290 7802 4d 59 20 57 49 4c         	fcc	"MY WILLIAMS TEST PROM LEVEL 3,4,6 "
          4c 49 41 4d 53 20
          54 45 53 54 20 50
          52 4f 4d 20 4c 45
          56 45 4c 20 33 2c
          34 2c 36 20
0291 7824 57 52 49 54 54 45         	fcc	"WRITTEN 1992 BY DALLAS E. OVERTURF "
          4e 20 31 39 39 32
          20 42 59 20 44 41
          4c 4c 41 53 20 45
          2e 20 4f 56 45 52
          54 55 52 46 20
0292                                
0293                                ;	A Non Maskable Interrupt (switch 33) will restart at show_revision.
0294                                
0295                                show_revision:
0296                                
0297 7847 c6 02                     	ldab	#revision_val	;b now has revision.
0298 7849 ce 78 4f                  	ldx	#revision_ret	;x has return address.
0299 784c 7e 7d 8d                  	jmp	sflash_sp_svc	;
0300                                revision_ret:
0301 784f 86 02                     	ldaa	#2		;two times will be a very long wait.
0302                                revision_lp:
0303 7851 ce 75 30                  	ldx	#30000		;long wait.
0304                                rev_x_lp:
0305 7854 09                        	dex			;dec wait count
0306 7855 26 fd                     	bne	rev_x_lp	;
0307 7857 4a                        	deca			;dec loop count.
0308 7858 26 f7                     	bne	#revision_lp	;branch if not done or fall through to start.
0309                                
0310                                start:
0311                                
0312                                	;1st write and or read some data and address patterns to see that
0313                                	;the address and data buses are basically ok on the analyzer.
0314                                
0315 785a ce 00 00                  	ldx	#$0000		;An address to write to write to. = 0000.
0316 785d 86 00                     	ldaa	#$0		;some data to write= 00.
0317 785f a7 00                     	staa	0,x		;unchecked data only to look at bus.
0318 7861 43                        	coma			;some data to write= FF.
0319 7862 a7 00                     	staa	0,x		;unchecked data only to look at bus.
0320 7864 86 55                     	ldaa	#$55		;some data to write= 55.
0321 7866 a7 00                     	staa	0,x		;unchecked data only to look at bus.
0322 7868 43                        	coma			;some data to write= AA.
0323 7869 a7 00                     	staa	0,x		;unchecked data only to look at bus.
0324 786b ce 00 00                  	ldx	#$0000		;address pattern to read from.
0325 786e a6 00                     	ldaa	0,x		;read address, don't care about data.
0326 7870 ce ff ff                  	ldx	#$FFFF		;address pattern to read from.
0327 7873 a6 00                     	ldaa	0,x		;read address, don't care about data.
0328 7875 ce 55 55                  	ldx 	#$5555		;address pattern to read from.
0329 7878 a6 00                     	ldaa	0,x		;read address, don't care about data.
0330 787a ce aa aa                  	ldx 	#$AAAA		;address pattern to read from.
0331 787d a6 00                     	ldaa	0,x		;read address, don't care about data.
0332                                
0333                                
0334                                ;	The LED is ON, when the board is reset, for about 1/2 - 1 second.
0335                                ;	That is not to be confused with the first flash.
0336                                ;	Turn it off so we know we successfully entered our code.
0337                                ;	Successfull entry into prom will show two short flashes 
0338                                ;	not counting the flash for reset.  If there is any question of 
0339                                ;	the number of flashes, the diagnostic pushbutton on the mpu
0340                                ;	(lower of the two buttons) may be depressed to cause a non-maskable
0341                                ;	interrupt at any time to restart the program.  Since there is no
0342                                ;	reset the only flashes seen at that point should be real.
0343                                
0344                                
0345 787f c6 01                     	ldab	#$1		;Flash routines expect a count in b.
0346 7881 ce 78 a1                  	ldx	#start_return	;x now has return address.
0347 7884 35                        	txs			;sp now has return address.
0348 7885 7e 7d 70                  	jmp	#flash_sp_ofent	;go turn off the light.
0349                                
0350                                ; 	Now we will do our 2 short flashes to show we have entered the code.
0351                                
0352                                pass:
0353                                
0354 7888 ce 78 90                  	ldx	#pass_return	;x has return address.
0355 788b c6 02                     	ldab	#2		;flash count.  Double quick blink so we know
0356 788d 7e 7d 8d                  	jmp	sflash_sp_svc	;we are in code and where start is on a pass.
0357                                pass_return:
0358                                
0359                                
0360                                
0361                                
0362                                ;	We init data in the CMOS ram to make sure that it will interfere
0363                                ;	with either ram1 or ram2 if by chance it is not unique. Thus if
0364                                ;	bus is corrupted during ram1 or ram2 testing; the user may
0365                                ;	remove the cmos ram to see if the diagnostic will get past that
0366                                ;	point.  If so the cmos enable circuitry should be check out.
0367                                
0368 7890 ce 01 00                  	ldx	#cmos_min	;setup to init cmos.
0369 7893 86 00                     	ldaa	#$0		;
0370                                cmos_init:
0371 7895 84 0f                     	anda	#$0f		;CMOS uses low 4 bits of data. Mask out unused.
0372 7897 a7 00                     	staa	0,x		;write to cmos.  If cmos bad we find out later.
0373 7899 8b 03                     	adda	#$3		;this will cause bits to vary so odd even addr
0374                                				;sees all bits set and cleared.
0375 789b 08                        	inx			;next addr.
0376 789c 8c 02 00                  	cpx	#cmos_max+1	;check range.
0377 789f 26 f4                     	bne	#cmos_init	;branch if not done; else fall through.
0378                                
0379                                ;=============================================================================
0380                                
0381                                start_return:
0382                                
0383 78a1 c6 02                     	ldab	#$02		;Two flashes on entry.
0384 78a3 ce 78 aa                  	ldx	#start_return1	;x now has return address.
0385 78a6 35                        	txs			;sp now has return address.
0386 78a7 7e 7d 8d                  	jmp	#sflash_sp_svc	;Do flashes.
0387                                start_return1:
0388                                
0389                                
0390                                ; The first real test starts here.
0391                                
0392 78aa ce 00 00                  	ldx	#ram1_min		; Start addr of 6810.
0393 78ad 86 00                     	ldaa	#$0
0394                                ram1_data:
0395                                ;	ram1_data attempts to check that each cell can hold any
0396                                ;	data pattern in the 6810.  address has not been qualified yet.
0397                                
0398                                
0399 78af ce 00 00                  	ldx	#ram1_min
0400                                
0401                                ram1_d_nextadr:
0402 78b2 86 00                     	ldaa	#$0		;aa will be expected data
0403                                				;start at zero so this must get zero on a read
0404 78b4 20 0b                     	bra	#ram1_d_datlp	;
0405                                
0406                                ram1_d_errlp:
0407 78b6 7f ff fe                  	clr	#reset_vector	;failure check in.  Write to read only space.
0408 78b9 f6 78 00                  	ldab	error_action	;sets CCs.
0409 78bc 27 03                     	beq	#ram1_d_datlp	;no flash error.
0410 78be 7e 7d 29                  	jmp	flash_error	;
0411                                
0412                                ram1_d_datlp:
0413 78c1 a7 00                     	staa	0,x		;write to the 6810.
0414 78c3 e6 00                     	ldab	0,x		;read actual data from the 6810.
0415 78c5 11                        	cba			;compare a and b accumulators.
0416 78c6 26 ee                     	bne	#ram1_d_errlp	;loop on the error till it clears.
0417 78c8 4c                        	inca			;increment a.
0418 78c9 26 f6                     	bne	#ram1_d_datlp	;data is 00-FF on FF we roll to 00 indicating
0419                                				;we have checked all data on current address.
0420 78cb 08                        	inx			;inc x to next addr.
0421 78cc 8c 00 80                  	cpx	#ram1_max+1	;if past max addr then we are done.
0422 78cf 26 e1                     	bne	#ram1_d_nextadr	;not done; do next address, or fall through.
0423                                
0424 78d1 c6 01                     	ldab	#$1		;flash #1.  ram1 data bits are unique.
0425                                
0426 78d3 ce 78 d9                  	ldx	#ram1_d_return	;x now has return address.
0427 78d6 7e 7d 50                  	jmp	#flash_sp_svc	;go flash.
0428                                ram1_d_return:			;return here.
0429                                
0430                                ;=============================================================================
0431                                
0432                                ;	This test will verify that locations zero and one in ram1 are unique
0433                                ;	from all other locations in ram1.  Thus we will have identified two
0434                                ;	bytes of memory that can be used as stack space or temp storage in
0435                                ;	the full ram1 address uniqueness test which is an address equal data
0436                                ;	test.
0437                                ;	By using all data patterns we verify that there is no data line(s)
0438                                ;	shorted to an address line which would later confuse things for the
0439                                ;	four addresses in question.  Probably most address uniqueness problems
0440                                ;	will be caught here; however we will do adress equal data test later
0441                                ;	to be very safe.  Note:  Between this test and the ram1_data_test; we
0442                                ;	really should not see data shorted to an address.
0443                                
0444                                
0445 78d9 4f                        	clra		;aa holds pattern to write. Do all patterns. 00-FF.
0446                                ram1_au0_part:
0447 78da ce 00 02                  	ldx	#ram1_min+2
0448 78dd 20 0b                     	bra	#ram1_au0_loop
0449                                
0450                                ram1_au0_err:
0451 78df 7f ff fe                  	clr	#reset_vector	;failure check in.  Write to read only space.
0452 78e2 f6 78 00                  	ldab	error_action	;sets CCs.
0453 78e5 27 03                     	beq	#ram1_au0_loop	;no flash error.
0454 78e7 7e 7d 29                  	jmp	flash_error	;
0455                                
0456                                ram1_au0_loop:
0457 78ea 5f                        	clrb			;to clear temp locs. We need some temp space.
0458 78eb d7 00                     	stab	ram1_min		;temp loc 0.  Part of temp_0.  Used for
0459 78ed d7 01                     	stab	ram1_min+1	;temp loc 1.  Part of temp_0.  Future storage.
0460 78ef a7 00                     	staa	0,x		;write test data to all other ram1 locations.
0461 78f1 d6 00                     	ldab	ram1_min		;temp loc 0.  This will set CCs.
0462 78f3 26 ea                     	bne	ram1_au0_err	;loop on error.
0463 78f5 d6 01                     	ldab	ram1_min+1	;temp loc 1.  This will set CCs.
0464 78f7 26 e6                     	bne	ram1_au0_err	;loop on error.
0465 78f9 4c                        	inca			;inc aa to next data pattern.
0466 78fa 27 02                     	beq	#ram1_au0_ckdone
0467 78fc 20 ec                     	bra	#ram1_au0_loop	;Do next data pattern.
0468                                
0469                                ram1_au0_ckdone:
0470 78fe 8c 00 7f                  	cpx	#ram1_max	; check if really done.
0471 7901 27 04                     	beq	ram1_au0_done	; yes we are really done.
0472 7903 08                        	inx	
0473 7904 4f                        	clra			; Start pattern at 00 again.
0474 7905 20 e3                     	bra	#ram1_au0_loop	;not done continue looping.
0475                                
0476                                ram1_au0_done:
0477                                ;	ram1 Address Equal Data test.  Final adress uniqness test of ram1.
0478                                ;	It is not expected that this test will ever likely fail except
0479                                ;	in the case of a bad 6810.  However this test has a scope loop
0480                                ;	in case strange circumstances are encountered and we fail due
0481                                ;	to something other than a bad 6810.
0482                                ;	The scope loop is only a repetative read of the failed location.
0483                                ;	Since the data should equal the address, then using a 2 channel
0484                                ;	scope it should be easy to look at the address being read; and
0485                                ;	what the data comming out is.  The data comming out will most
0486                                ;	likely not equal the address by a single bit.  That bit will
0487                                ;	most likely be the address bit that is bad going into the
0488                                ;	6810; assuming that the 6810 is known good, the address line
0489                                ;	in question should be checked for shorts to surronding signals.
0490                                
0491                                ram1_aed_test:
0492 7907 86 7f                     	ldaa	#ram1_max
0493 7909 ce 00 7f                  	ldx	#ram1_max
0494                                
0495                                ram1_aed_dec:
0496 790c a7 00                     	staa	0,x		;write pattern to address.
0497 790e 4a                        	deca			;next pattern.
0498 790f 09                        	dex			;next address.
0499 7910 8c 00 01                  	cpx	#temp_0+1	;leave our two byte space alone!
0500 7913 26 f7                     	bne	ram1_aed_dec	;done if equal else continue.
0501                                
0502                                ;	ram1 should now be completely address equal data less first two locs.
0503                                
0504 7915 86 02                     	ldaa	#temp_0+2	;get initial value in a register.
0505 7917 ce 00 02                  	ldx	#temp_0+2	;get start address from temp storage.
0506                                
0507                                ram1_aed_inc:
0508 791a e6 00                     	ldab	0,x		;read 1st address.
0509 791c 11                        	cba			;compare expected in a, to actual in b.
0510 791d 26 0a                     	bne	ram1_find_loc	;Try to find the conflict for a scope loop.
0511 791f 4c                        	inca			;next pattern.
0512 7920 08                        	inx			;next address.
0513 7921 8c 00 80                  	cpx	#ram1_max+1	;done when we reach ram1_max.
0514 7924 26 f4                     	bne	ram1_aed_inc	;continue if not done or fall through and pass.
0515                                
0516                                ;	ram1 should now be completely address equal data, less first two locs.
0517                                
0518 7926 7e 79 a3                  	jmp	ram1_aed_passed	;no error, we passed.
0519                                
0520                                ;	On entry x is the location in error found as follows:
0521                                ;	The routine prior to this is expected to write data from max to
0522                                ;	min addresses and then do the check from min to max so that 
0523                                ;	temp_0 - 1 will be the highest address needed to find the error.
0524                                ;	If this policy is not adhered to then this routine's ability to
0525                                ;	localize the error will be compromised.
0526                                ;	Note:  Temp_0 occupies the first two bytes of ram1 thus it MUST BE
0527                                ;	gauranteed to to be uniqe to ram1 prior to using this routine.
0528                                
0529                                ram1_find_loc:
0530 7929 4f                        	clra			;
0531 792a a7 00                     	staa	0,x		;clear error location.
0532 792c df 00                     	stx	temp_0		;store away error loc for now.
0533 792e 86 aa                     	ldaa	#$AA		;Compliment of first pattern.  We do two.
0534                                
0535                                ram1_au_nxt_dat:
0536 7930 43                        	coma			;compliment so 1st pattern will be 55.
0537 7931 ce 00 02                  	ldx	#temp_0+2	;initial loc we write to.
0538                                
0539                                ram1_au_nxt_adr:
0540 7934 a7 00                     	staa	0,x		;write to location then check error loc.
0541 7936 35                        	txs			;store x in sp for now.
0542 7937 de 00                     	ldx	temp_0		;get error loc into x.
0543 7939 e6 00                     	ldab	0,x		;check it.  This will set CCs.
0544 793b 30                        	tsx			;restore x from sp. This will not change CCs.
0545 793c 26 16                     	bne	ram1_aed_found	;we will now go and try to loop on the error.
0546 793e 08                        	inx			;next address.  If x temp_0, we wrote up
0547 793f 9c 00                     	cpx	temp_0		;to temp_0 - 1 and cannot find the error.
0548 7941 2d f1                     	blt	ram1_au_nxt_adr	;continue to next addr.
0549 7943 81 aa                     	cmpa	#$AA		;if AA then we are done.
0550 7945 26 e9                     	bne	ram1_au_nxt_dat	;if only 55 then we need to do AA still.
0551 7947 20 1c                     	bra	ram1_aed_unot	;We should never exit this routine unless
0552                                				;we could not find error for some reason.
0553                                				;there for we branch, flash and restart.
0554                                
0555                                ;	ram1_f_loop expects the bad address in temp_0 and conflict addr in x.
0556                                ;	data written to find error will be in aa still.  aa has the data.
0557                                
0558                                ram1_aed_floop:
0559 7949 7f ff fe                  	clr	#reset_vector	;failure check in.  Write to read only space.
0560 794c f6 78 00                  	ldab	error_action	;sets CCs.
0561 794f 27 03                     	beq	#ram1_aed_found	;no flash error.
0562 7951 7e 7d 29                  	jmp	flash_error	;
0563                                
0564                                ram1_aed_found:
0565 7954 35                        	txs			;hold x in sp.  Note x is unchanged.
0566 7955 5f                        	clrb			;
0567 7956 de 00                     	ldx	temp_0		;x has error loc.
0568 7958 e7 00                     	stab	0,x		;clear error loc.
0569 795a 30                        	tsx			;restore x.
0570 795b a7 00                     	staa	0,x		;write to x, we expect to overwrite error loc.
0571 795d 35                        	txs			;hold x in sp.
0572 795e de 00                     	ldx	temp_0		;x has error loc.
0573 7960 e6 00                     	ldab	0,x		;this will set CCs.
0574 7962 30                        	tsx			;restore x from sp.  This does not affect CCs.
0575 7963 26 e4                     	bne	ram1_aed_floop	;if not equal we are seeing the error.
0576                                
0577                                ram1_aed_unot:
0578                                
0579 7965 c6 03                     	ldab	#$3		;setup to flash three times so we know
0580                                				;we lost the error.  We will restart.
0581                                
0582                                ram1_zflash:
0583                                ;	attempt to flash the light. n times based on contents of ab.
0584                                
0585 7967 ce 28 00                  	ldx	#pia1_sel	;x has pia1 enable base addr.  addr of pia1
0586 796a 86 38                     	ldaa	#pia_ddr_reg+led_on	;set to select ddra, cra 3,4,5 set.
0587 796c a7 01                     	staa	cra_sel,x	;ddra is now selected, cra 3,4,5 now set.
0588 796e 86 30                     	ldaa	#led_bits	;set bits 4 and 5 for led select in ddr.
0589 7970 a7 00                     	staa	ddra_sel,x	;setup mask in ddra.
0590 7972 86 04                     	ldaa	#pia_out_reg	;bits for CRA to access PRA.
0591 7974 a7 01                     	staa	cra_sel,x	;set CRA.
0592 7976 86 30                     	ldaa	#led_bits_on	;try to light Both LEDs.
0593 7978 a7 00                     	staa	pra_sel,x	;set bits in PRA.
0594 797a 86 3c                     	ldaa	#pia_out_reg+led_on	;Should be 3C.
0595 797c a7 01                     	staa	cra_sel,x	;do it.  Should now be accessing outreg.
0596 797e a7 01                     	staa	cra_sel,x	;do it.  Twice to be sure. CA2 should be high.
0597                                
0598 7980 ce 27 10                  	ldx	#10000		;LED On count.
0599                                
0600                                ram1_zflash_on:
0601                                
0602 7983 09                        	dex			; should decrement x by 1.
0603 7984 26 fd                     	bne	#ram1_zflash_on	; keep on for LED on count. 
0604                                
0605                                ;	setup to turn off now to complete flash.
0606                                
0607 7986 ce 28 00                  	ldx	#pia1_sel	;x has pia1 enable base addr.  addr of pia1
0608 7989 86 30                     	ldaa	#pia_ddr_reg+led_off	;set to select ddra, cra 2,3,4 set.
0609 798b a7 01                     	staa	cra_sel,x	;ddra is now selected, cra 2,3,4 now set.
0610 798d 86 34                     	ldaa	#pia_out_reg+led_off	;Should be 34.
0611 798f a7 01                     	staa	cra_sel,x	;do it.  Should now be accessing outreg.
0612 7991 a7 01                     	staa	cra_sel,x	;do it.  Twice to be sure. CA2 should be high.
0613 7993 86 00                     	ldaa	#led_bits_off	;to reset pa4 pa5 and turn off LEDs.
0614 7995 a7 00                     	staa	pra_sel,x	;PA4 AND PA5 SHOULD HAVE GONE LOW. LEDs OFF.
0615                                
0616 7997 ce 27 10                  	ldx	#10000		;LED Off count.
0617                                
0618                                ram1_zflash_off:
0619 799a 09                        	dex			; should decrement x by 1.
0620 799b 26 fd                     	bne	#ram1_zflash_off	; keep off for LED off count. 
0621 799d 5a                        	decb
0622 799e 26 c7                     	bne	#ram1_zflash	; go till done flashing; then fall through.
0623                                
0624 79a0 7e 78 5a                  	jmp	start		;we will restart from scratch.
0625                                
0626                                
0627                                ;	The next test expects that ram1 has addr equal data pattern in it.
0628                                ;	make it so.
0629                                
0630                                ram1_aed_passed:
0631 79a3 86 00                     	ldaa	#$0
0632 79a5 ce 00 00                  	ldx	#$0
0633                                ram1_set_loop:
0634 79a8 a7 00                     	staa	0,x
0635 79aa 08                        	inx			;next address.
0636 79ab 4c                        	inca			;next pattern.
0637 79ac 81 80                     	cmpa	#ram1_max+1	;if equal then we are done.
0638 79ae 26 f8                     	bne	#ram1_set_loop	;go write pattern.
0639                                
0640                                ;	ram1 should now be completely address equal data.
0641                                
0642 79b0 c6 01                     	ldab	#$1		;flash #2.  ram1 addresses are unique.
0643                                				;we don't call flash svc yet till we check
0644                                				;that the ram is unique from other devices.
0645                                				;such as ram2 and the 5101 CMOS ram.
0646 79b2 ce 79 b8                  	ldx	#ram1_aed_return	;x now has return address.
0647 79b5 7e 7d 50                  	jmp	#flash_sp_svc	;go flash.
0648                                ram1_aed_return:
0649                                
0650                                ;=============================================================================
0651                                
0652                                ;	Verify that writing to ram2 does not write to ram1.
0653                                
0654 79b8 ce 00 00                  	ldx	#ram1_min	;
0655 79bb 86 00                     	ldaa	#$00		;setup ram1 data to known 00 is simplest.
0656                                ram1_u_clr:			; 
0657 79bd a7 00                     	staa	0,x		; clear.
0658 79bf 08                        	inx
0659 79c0 8c 00 80                  	cpx	#ram1_max+1	; set CCs. equal if done.
0660 79c3 26 f8                     	bne	#ram1_u_clr	; continue or fall through.
0661                                
0662                                ram1_u_test:
0663 79c5 8e 00 ff                  	lds	#ram2_max	; high addr of device we are checking against.
0664 79c8 86 ff                     	ldaa	#$ff		; data pattern we will write.
0665                                
0666                                ram1ram2u_lp:
0667 79ca 36                        	psha			; This will write a byte to ram2.
0668 79cb 30                        	tsx			; x now has a copy of sp+1 sp is unchanged.
0669 79cc 8c 00 80                  	cpx	#ram2_min	; because got sp+1 this is a straight cmpare.
0670 79cf 27 26                     	beq	#ram1ram2_unxt	; done goto next test; or continue.
0671 79d1 20 f7                     	bra	ram1ram2u_lp	;
0672                                
0673                                ram1ram2u_chk:
0674 79d3 ce 00 00                  	ldx	#ram1_min	;
0675                                
0676                                ram1ram2u_chklp:
0677 79d6 e6 00                     	ldab	0,x		; read device location.  This will set CCs.
0678 79d8 26 08                     	bne	#ram1ram2_err	; if not zero goto error routine.
0679                                
0680                                ram1ram2u_reent:
0681 79da 8c 00 7f                  	cpx	#ram1_max	; check if done.
0682 79dd 26 f7                     	bne	#ram1ram2u_chklp	; loop if not done
0683 79df 08                        	inx			; inc x.
0684 79e0 20 f4                     	bra	#ram1ram2u_chklp	;
0685                                
0686                                ram1ram2_err:
0687 79e2 7f ff fe                  	clr	#reset_vector	;failure check in.  Write to read only space.
0688 79e5 f6 78 00                  	ldab	error_action	;sets CCs.
0689 79e8 27 03                     	beq	#ram1ram2_errlp	;no flash error.
0690 79ea 7e 7d 29                  	jmp	flash_error	;
0691                                
0692                                ram1ram2_errlp:
0693 79ed 6f 00                     	clr	0,x		; clear overwritten location.
0694 79ef 34                        	des			; sp will always be fail addr+1. fix it.
0695 79f0 36                        	psha			; write to suspect location.
0696 79f1 e6 00                     	ldab	0,x		; check for failure.  This sets CCs.
0697 79f3 26 f8                     	bne	#ram1ram2_errlp	; continue to loop on error if failing.
0698 79f5 20 e3                     	bra	#ram1ram2u_reent	;failure not solid;continue.
0699                                
0700                                ram1ram2_unxt:
0701                                
0702                                ;	Verify that writing to cmos does not write to ram1.
0703                                
0704                                ram1cmos_uniq:
0705 79f7 ce 00 00                  	ldx	#ram1_min	; start of ram1.
0706 79fa 86 00                     	ldaa	#$0		; zero to clear.
0707                                
0708                                ram1cmos_clr:			; setup ram1 data to known 00 is simplest.
0709 79fc a7 00                     	staa	0,x		; clear ram1.
0710 79fe 08                        	inx
0711 79ff 8c 00 80                  	cpx	#ram1_max+1	; check if done.
0712 7a02 26 f8                     	bne	#ram1cmos_clr	; continue or fall through.
0713 7a04 8e 01 ff                  	lds	#cmos_max	; high addr of device we are checking against.
0714                                				; sp grows from high to low.
0715                                ram1cmos_lp:
0716 7a07 86 ff                     	ldaa	#$FF		; Any pattern besides zero will do here.
0717 7a09 36                        	psha			; This will write a byte to cmos.
0718 7a0a 30                        	tsx			; x now has a copy of sp+1. sp is unchanged.
0719 7a0b 8c 01 00                  	cpx	#cmos_min	; because got sp+1 this is a straight cmpare.
0720 7a0e 27 24                     	beq	#ram1cmos_pass	; if done then pass.
0721                                
0722                                ram1cmos_chk:
0723 7a10 ce 00 00                  	ldx	#ram1_min	; Setup to check out ram1.  All addrs SB 00.
0724                                
0725                                ram1cmos_chklp:
0726 7a13 e6 00                     	ldab	0,x		; read device location.  This will set CCs.
0727 7a15 26 08                     	bne	#ram1cmos_err	; if not zero goto error routine.
0728                                
0729                                ram1cmos_reent:			; if error goes away in errloop then re-enter.
0730 7a17 08                        	inx			; inc x.
0731 7a18 8c 00 80                  	cpx	#ram1_max+1	; check if done.
0732 7a1b 26 f6                     	bne	#ram1cmos_chklp	; loop if not done
0733 7a1d 20 e8                     	bra	#ram1cmos_lp	; current did not overwrite, next cmos address.
0734                                
0735                                ram1cmos_err:
0736 7a1f 7f ff fe                  	clr	#reset_vector	;failure check in.  Write to read only space.
0737 7a22 f6 78 00                  	ldab	error_action	;sets CCs.
0738 7a25 27 03                     	beq	#ram1cmos_errlp	;no flash error.
0739 7a27 7e 7d 29                  	jmp	flash_error	;
0740                                
0741                                ram1cmos_errlp:
0742 7a2a 6f 00                     	clr	0,x		; clear overwritten location.
0743 7a2c 34                        	des			; sp will always be fail addr+1. fix it.
0744 7a2d 36                        	psha			; write to suspect location.
0745 7a2e e6 00                     	ldab	0,x		; check for failure.  This sets CCs.
0746 7a30 26 f8                     	bne	#ram1cmos_errlp	; continue to loop on error if failing.
0747 7a32 20 e3                     	bra	#ram1cmos_reent	; failure not solid;continue.
0748                                
0749                                ram1cmos_pass:
0750                                
0751 7a34 c6 01                     	ldab	#$1		;flash #3.  ram1 unique from ram2 & cmos.
0752                                				; by ram2 or by cmos.
0753 7a36 ce 7a 3c                  	ldx	#ram1cmos_return	;x now has return address.
0754 7a39 7e 7d 50                  	jmp	#flash_sp_svc	;go flash.
0755                                ram1cmos_return:
0756                                
0757                                ;=============================================================================
0758                                
0759 7a3c ce 00 80                  	ldx	#ram2_min		; Start addr of 6810.
0760 7a3f 86 00                     	ldaa	#$0
0761                                ram2_data:
0762                                ;	ram2_data attempts to check that each cell can hold any
0763                                ;	data pattern in the 6810.  address has not been qualified yet.
0764                                
0765                                
0766 7a41 ce 00 80                  	ldx	#ram2_min
0767                                
0768                                ram2_d_nextadr:
0769 7a44 86 00                     	ldaa	#$0		;aa will be expected data
0770                                				;start at zero so this must get zero on a read
0771 7a46 20 0b                     	bra	#ram2_d_datlp	;
0772                                
0773                                ram2_d_errlp:
0774 7a48 7f ff fe                  	clr	#reset_vector	;failure check in.  Write to read only space.
0775 7a4b f6 78 00                  	ldab	error_action	;sets CCs.
0776 7a4e 27 03                     	beq	#ram2_d_datlp	;no flash error.
0777 7a50 7e 7d 29                  	jmp	flash_error	;
0778                                
0779                                ram2_d_datlp:
0780 7a53 a7 00                     	staa	0,x		;write to the 6810.
0781 7a55 e6 00                     	ldab	0,x		;read actual data from the 6810.
0782 7a57 11                        	cba			;compare a and b accumulators.
0783 7a58 26 ee                     	bne	#ram2_d_errlp	;loop on the error till it clears.
0784 7a5a 4c                        	inca			;increment a.
0785 7a5b 26 f6                     	bne	#ram2_d_datlp	;data is 00-FF on FF we roll to 00 indicating
0786                                				;we have checked all data on current address.
0787 7a5d 08                        	inx			;inc x to next addr.
0788 7a5e 8c 01 00                  	cpx	#ram2_max+1	;if past max addr then we are done.
0789 7a61 26 e1                     	bne	#ram2_d_nextadr	;not done; do next address, or fall through.
0790                                
0791 7a63 c6 01                     	ldab	#$1		;flash #4.  ram2 data bits are unique.
0792                                
0793 7a65 ce 7a 6b                  	ldx	#ram2_d_return	;x now has return address.
0794 7a68 7e 7d 50                  	jmp	#flash_sp_svc	;go flash.
0795                                ram2_d_return:			;return here.
0796                                
0797                                ;=============================================================================
0798                                
0799                                ;	This test will verify that locations zero and one in ram2 are unique
0800                                ;	from all other locations in ram2.  Thus we will have identified two
0801                                ;	bytes of memory that can be used as stack space or temp storage in
0802                                ;	the full ram2 address uniqueness test which is an address equal data
0803                                ;	test.
0804                                ;	By using all data patterns we verify that there is no data line(s)
0805                                ;	shorted to an address line which would later confuse things for the
0806                                ;	four addresses in question.  Probably most address uniqueness problems
0807                                ;	will be caught here; however we will do adress equal data test later
0808                                ;	to be very safe.  Note:  Between this test and the ram2_data_test; we
0809                                ;	really should not see data shorted to an address.
0810                                
0811                                
0812 7a6b 4f                        	clra		;aa holds pattern to write. Do all patterns. 00-FF.
0813                                ram2_au0_part:
0814 7a6c ce 00 82                  	ldx	#ram2_min+2
0815 7a6f 20 0b                     	bra	#ram2_au0_loop
0816                                
0817                                ram2_au0_err:
0818 7a71 7f ff fe                  	clr	#reset_vector	;failure check in.  Write to read only space.
0819 7a74 f6 78 00                  	ldab	error_action	;sets CCs.
0820 7a77 27 03                     	beq	#ram2_au0_loop	;no flash error.
0821 7a79 7e 7d 29                  	jmp	flash_error	;
0822                                
0823                                ram2_au0_loop:
0824 7a7c 5f                        	clrb			;to clear temp locs. We need some temp space.
0825 7a7d d7 80                     	stab	ram2_min		;temp loc 0.  Part of temp_0.  Used for
0826 7a7f d7 81                     	stab	ram2_min+1	;temp loc 1.  Part of temp_0.  Future storage.
0827 7a81 a7 00                     	staa	0,x		;write test data to all other ram2 locations.
0828 7a83 d6 80                     	ldab	ram2_min		;temp loc 0.  This will set CCs.
0829 7a85 26 ea                     	bne	ram2_au0_err	;loop on error.
0830 7a87 d6 81                     	ldab	ram2_min+1	;temp loc 1.  This will set CCs.
0831 7a89 26 e6                     	bne	ram2_au0_err	;loop on error.
0832 7a8b 4c                        	inca			;inc aa to next data pattern.
0833 7a8c 27 02                     	beq	#ram2_au0_ckdone
0834 7a8e 20 ec                     	bra	#ram2_au0_loop	;Do next data pattern.
0835                                
0836                                ram2_au0_ckdone:
0837 7a90 8c 00 ff                  	cpx	#ram2_max	; check if really done.
0838 7a93 27 04                     	beq	ram2_au0_done	; yes we are really done.
0839 7a95 08                        	inx	
0840 7a96 4f                        	clra			; Start pattern at 00 again.
0841 7a97 20 e3                     	bra	#ram2_au0_loop	;not done continue looping.
0842                                
0843                                ram2_au0_done:
0844                                ;	ram2 Address Equal Data test.  Final adress uniqness test of ram2.
0845                                ;	It is not expected that this test will ever likely fail except
0846                                ;	in the case of a bad 6810.  However this test has a scope loop
0847                                ;	in case strange circumstances are encountered and we fail due
0848                                ;	to something other than a bad 6810.
0849                                ;	The scope loop is only a repetative read of the failed location.
0850                                ;	Since the data should equal the address, then using a 2 channel
0851                                ;	scope it should be easy to look at the address being read; and
0852                                ;	what the data comming out is.  The data comming out will most
0853                                ;	likely not equal the address by a single bit.  That bit will
0854                                ;	most likely be the address bit that is bad going into the
0855                                ;	6810; assuming that the 6810 is known good, the address line
0856                                ;	in question should be checked for shorts to surronding signals.
0857                                
0858                                ram2_aed_test:
0859 7a99 86 ff                     	ldaa	#ram2_max
0860 7a9b ce 00 ff                  	ldx	#ram2_max
0861                                
0862                                ram2_aed_dec:
0863 7a9e a7 00                     	staa	0,x		;write pattern to address.
0864 7aa0 4a                        	deca			;next pattern.
0865 7aa1 09                        	dex			;next address.
0866 7aa2 8c 00 01                  	cpx	#temp_0+1	;leave our two byte space alone!
0867 7aa5 26 f7                     	bne	ram2_aed_dec	;done if equal else continue.
0868                                
0869                                ;	ram2 should now be completely address equal data less first two locs.
0870                                
0871 7aa7 86 02                     	ldaa	#temp_0+2	;get initial value in a register.
0872 7aa9 ce 00 02                  	ldx	#temp_0+2	;get start address from temp storage.
0873                                
0874                                ram2_aed_inc:
0875 7aac e6 00                     	ldab	0,x		;read 1st address.
0876 7aae 11                        	cba			;compare expected in a, to actual in b.
0877 7aaf 26 0a                     	bne	ram2_find_loc	;Try to find the conflict for a scope loop.
0878 7ab1 4c                        	inca			;next pattern.
0879 7ab2 08                        	inx			;next address.
0880 7ab3 8c 01 00                  	cpx	#ram2_max+1	;done when we reach ram2_max.
0881 7ab6 26 f4                     	bne	ram2_aed_inc	;continue if not done or fall through and pass.
0882                                
0883                                ;	ram2 should now be completely address equal data, less first two locs.
0884                                
0885 7ab8 7e 7b 35                  	jmp	ram2_aed_passed	;no error, we passed.
0886                                
0887                                ;	On entry x is the location in error found as follows:
0888                                ;	The routine prior to this is expected to write data from max to
0889                                ;	min addresses and then do the check from min to max so that 
0890                                ;	temp_0 - 1 will be the highest address needed to find the error.
0891                                ;	If this policy is not adhered to then this routine's ability to
0892                                ;	localize the error will be compromised.
0893                                ;	Note:  Temp_0 occupies the first two bytes of ram2 thus it MUST BE
0894                                ;	gauranteed to to be uniqe to ram2 prior to using this routine.
0895                                
0896                                ram2_find_loc:
0897 7abb 4f                        	clra			;
0898 7abc a7 00                     	staa	0,x		;clear error location.
0899 7abe df 00                     	stx	temp_0		;store away error loc for now.
0900 7ac0 86 aa                     	ldaa	#$AA		;Compliment of first pattern.  We do two.
0901                                
0902                                ram2_au_nxt_dat:
0903 7ac2 43                        	coma			;compliment so 1st pattern will be 55.
0904 7ac3 ce 00 02                  	ldx	#temp_0+2	;initial loc we write to.
0905                                
0906                                ram2_au_nxt_adr:
0907 7ac6 a7 00                     	staa	0,x		;write to location then check error loc.
0908 7ac8 35                        	txs			;store x in sp for now.
0909 7ac9 de 00                     	ldx	temp_0		;get error loc into x.
0910 7acb e6 00                     	ldab	0,x		;check it.  This will set CCs.
0911 7acd 30                        	tsx			;restore x from sp. This will not change CCs.
0912 7ace 26 16                     	bne	ram2_aed_found	;we will now go and try to loop on the error.
0913 7ad0 08                        	inx			;next address.  If x temp_0, we wrote up
0914 7ad1 9c 00                     	cpx	temp_0		;to temp_0 - 1 and cannot find the error.
0915 7ad3 2d f1                     	blt	ram2_au_nxt_adr	;continue to next addr.
0916 7ad5 81 aa                     	cmpa	#$AA		;if AA then we are done.
0917 7ad7 26 e9                     	bne	ram2_au_nxt_dat	;if only 55 then we need to do AA still.
0918 7ad9 20 1c                     	bra	ram2_aed_unot	;We should never exit this routine unless
0919                                				;we could not find error for some reason.
0920                                				;there for we branch, flash and restart.
0921                                
0922                                ;	ram2_f_loop expects the bad address in temp_0 and conflict addr in x.
0923                                ;	data written to find error will be in aa still.  aa has the data.
0924                                
0925                                ram2_aed_floop:
0926 7adb 7f ff fe                  	clr	#reset_vector	;failure check in.  Write to read only space.
0927 7ade f6 78 00                  	ldab	error_action	;sets CCs.
0928 7ae1 27 03                     	beq	#ram2_aed_found	;no flash error.
0929 7ae3 7e 7d 29                  	jmp	flash_error	;
0930                                
0931                                ram2_aed_found:
0932 7ae6 35                        	txs			;hold x in sp.  Note x is unchanged.
0933 7ae7 5f                        	clrb			;
0934 7ae8 de 00                     	ldx	temp_0		;x has error loc.
0935 7aea e7 00                     	stab	0,x		;clear error loc.
0936 7aec 30                        	tsx			;restore x.
0937 7aed a7 00                     	staa	0,x		;write to x, we expect to overwrite error loc.
0938 7aef 35                        	txs			;hold x in sp.
0939 7af0 de 00                     	ldx	temp_0		;x has error loc.
0940 7af2 e6 00                     	ldab	0,x		;this will set CCs.
0941 7af4 30                        	tsx			;restore x from sp.  This does not affect CCs.
0942 7af5 26 e4                     	bne	ram2_aed_floop	;if not equal we are seeing the error.
0943                                
0944                                ram2_aed_unot:
0945                                
0946 7af7 c6 03                     	ldab	#$3		;setup to flash three times so we know
0947                                				;we lost the error.  We will restart.
0948                                
0949                                ram2_zflash:
0950                                ;	attempt to flash the light. n times based on contents of ab.
0951                                
0952 7af9 ce 28 00                  	ldx	#pia1_sel	;x has pia1 enable base addr.  addr of pia1
0953 7afc 86 38                     	ldaa	#pia_ddr_reg+led_on	;set to select ddra, cra 3,4,5 set.
0954 7afe a7 01                     	staa	cra_sel,x	;ddra is now selected, cra 3,4,5 now set.
0955 7b00 86 30                     	ldaa	#led_bits	;set bits 4 and 5 for led select in ddr.
0956 7b02 a7 00                     	staa	ddra_sel,x	;setup mask in ddra.
0957 7b04 86 04                     	ldaa	#pia_out_reg	;bits for CRA to access PRA.
0958 7b06 a7 01                     	staa	cra_sel,x	;set CRA.
0959 7b08 86 30                     	ldaa	#led_bits_on	;try to light Both LEDs.
0960 7b0a a7 00                     	staa	pra_sel,x	;set bits in PRA.
0961 7b0c 86 3c                     	ldaa	#pia_out_reg+led_on	;Should be 3C.
0962 7b0e a7 01                     	staa	cra_sel,x	;do it.  Should now be accessing outreg.
0963 7b10 a7 01                     	staa	cra_sel,x	;do it.  Twice to be sure. CA2 should be high.
0964                                
0965 7b12 ce 27 10                  	ldx	#10000		;LED On count.
0966                                
0967                                ram2_zflash_on:
0968                                
0969 7b15 09                        	dex			; should decrement x by 1.
0970 7b16 26 fd                     	bne	#ram2_zflash_on	; keep on for LED on count. 
0971                                
0972                                ;	setup to turn off now to complete flash.
0973                                
0974 7b18 ce 28 00                  	ldx	#pia1_sel	;x has pia1 enable base addr.  addr of pia1
0975 7b1b 86 30                     	ldaa	#pia_ddr_reg+led_off	;set to select ddra, cra 2,3,4 set.
0976 7b1d a7 01                     	staa	cra_sel,x	;ddra is now selected, cra 2,3,4 now set.
0977 7b1f 86 34                     	ldaa	#pia_out_reg+led_off	;Should be 34.
0978 7b21 a7 01                     	staa	cra_sel,x	;do it.  Should now be accessing outreg.
0979 7b23 a7 01                     	staa	cra_sel,x	;do it.  Twice to be sure. CA2 should be high.
0980 7b25 86 00                     	ldaa	#led_bits_off	;to reset pa4 pa5 and turn off LEDs.
0981 7b27 a7 00                     	staa	pra_sel,x	;PA4 AND PA5 SHOULD HAVE GONE LOW. LEDs OFF.
0982                                
0983 7b29 ce 27 10                  	ldx	#10000		;LED Off count.
0984                                
0985                                ram2_zflash_off:
0986 7b2c 09                        	dex			; should decrement x by 1.
0987 7b2d 26 fd                     	bne	#ram2_zflash_off	; keep off for LED off count. 
0988 7b2f 5a                        	decb
0989 7b30 26 c7                     	bne	#ram2_zflash	; go till done flashing; then fall through.
0990                                
0991                                	
0992 7b32 7e 78 5a                  	jmp	start		;we will restart from scratch.
0993                                
0994                                
0995                                
0996                                ;	The next test expects that ram2 has addr equal data pattern in it.
0997                                ;	make it so.
0998                                
0999                                ram2_aed_passed:
1000 7b35 86 00                     	ldaa	#$0
1001 7b37 ce 00 00                  	ldx	#$0
1002                                ram2_set_loop:
1003 7b3a a7 00                     	staa	0,x
1004 7b3c 08                        	inx			;next address.
1005 7b3d 4c                        	inca			;next pattern.
1006 7b3e 81 00                     	cmpa	#ram2_max+1	;if equal then we are done.
1007 7b40 26 f8                     	bne	#ram2_set_loop	;go write pattern.
1008                                
1009                                ;	ram2 should now be completely address equal data.
1010                                
1011 7b42 c6 01                     	ldab	#$1		;flash #5.  ram2 addresses are unique.
1012                                				;we don't call flash svc yet till we check
1013                                				;that the ram is unique from other devices.
1014                                				;such as ram1 and the 5101 CMOS ram.
1015 7b44 ce 7b 4a                  	ldx	#ram2_aed_return	;x now has return address.
1016 7b47 7e 7d 50                  	jmp	#flash_sp_svc	;go flash.
1017                                ram2_aed_return:
1018                                
1019                                ;=============================================================================
1020                                
1021                                ;	Verify that writing to ram1 does not write to ram2.
1022                                
1023                                ram2ram1_uniq:
1024 7b4a ce 00 80                  	ldx	#ram2_min	; start of ram2.
1025 7b4d 86 00                     	ldaa	#$0		; zero to clear.
1026                                
1027                                ram2ram1_clr:			; setup ram2 data to known 00 is simplest.
1028 7b4f a7 00                     	staa	0,x		; clear ram2.
1029 7b51 08                        	inx
1030 7b52 8c 01 00                  	cpx	#ram2_max+1	; check if done.
1031 7b55 26 f8                     	bne	#ram2ram1_clr	; continue or fall through.
1032 7b57 8e 00 7f                  	lds	#ram1_max	; high addr of device we are checking against.
1033                                				; sp grows from high to low.
1034                                ram2ram1_lp:
1035 7b5a 86 ff                     	ldaa	#$FF		; Any pattern besides zero will do here.
1036 7b5c 36                        	psha			; This will write a byte to ram1.
1037 7b5d 30                        	tsx			; x now has a copy of sp+1. sp is unchanged.
1038 7b5e 8c 00 00                  	cpx	#ram1_min	; because got sp+1 this is a straight cmpare.
1039 7b61 27 24                     	beq	#ram2ram1_pass	; if done then pass.
1040                                
1041                                ram2ram1_chk:
1042 7b63 ce 00 80                  	ldx	#ram2_min	; Setup to check out ram2.  All addrs SB 00.
1043                                
1044                                ram2ram1_chklp:
1045 7b66 e6 00                     	ldab	0,x		; read device location.  This will set CCs.
1046 7b68 26 08                     	bne	#ram2ram1_err	; if not zero goto error routine.
1047                                
1048                                ram2ram1_reent:			; if error goes away in errloop then re-enter.
1049 7b6a 08                        	inx			; inc x.
1050 7b6b 8c 01 00                  	cpx	#ram2_max+1	; check if done.
1051 7b6e 26 f6                     	bne	#ram2ram1_chklp	; loop if not done
1052 7b70 20 e8                     	bra	#ram2ram1_lp	; current did not overwrite, next ram1 address.
1053                                
1054                                ram2ram1_err:
1055 7b72 7f ff fe                  	clr	#reset_vector	;failure check in.  Write to read only space.
1056 7b75 f6 78 00                  	ldab	error_action	;sets CCs.
1057 7b78 27 03                     	beq	#ram2ram1_errlp	;no flash error.
1058 7b7a 7e 7d 29                  	jmp	flash_error	;
1059                                
1060                                ram2ram1_errlp:
1061 7b7d 6f 00                     	clr	0,x		; clear overwritten location.
1062 7b7f 34                        	des			; sp will always be fail addr+1. fix it.
1063 7b80 36                        	psha			; write to suspect location.
1064 7b81 e6 00                     	ldab	0,x		; check for failure.  This sets CCs.
1065 7b83 26 f8                     	bne	#ram2ram1_errlp	; continue to loop on error if failing.
1066 7b85 20 e3                     	bra	#ram2ram1_reent	; failure not solid;continue.
1067                                
1068                                ram2ram1_pass:
1069                                
1070                                ;	Verify that writing to cmos does not write to ram2.
1071                                
1072                                ram2cmos_uniq:
1073 7b87 ce 00 80                  	ldx	#ram2_min	; start of ram2.
1074 7b8a 86 00                     	ldaa	#$0		; zero to clear.
1075                                
1076                                ram2cmos_clr:			; setup ram2 data to known 00 is simplest.
1077 7b8c a7 00                     	staa	0,x		; clear ram2.
1078 7b8e 08                        	inx
1079 7b8f 8c 01 00                  	cpx	#ram2_max+1	; check if done.
1080 7b92 26 f8                     	bne	#ram2cmos_clr	; continue or fall through.
1081 7b94 8e 01 ff                  	lds	#cmos_max	; high addr of device we are checking against.
1082                                				; sp grows from high to low.
1083                                ram2cmos_lp:
1084 7b97 86 ff                     	ldaa	#$FF		; Any pattern besides zero will do here.
1085 7b99 36                        	psha			; This will write a byte to cmos.
1086 7b9a 30                        	tsx			; x now has a copy of sp+1. sp is unchanged.
1087 7b9b 8c 01 00                  	cpx	#cmos_min	; because got sp+1 this is a straight cmpare.
1088 7b9e 27 24                     	beq	#ram2cmos_pass	; if done then pass.
1089                                
1090                                ram2cmos_chk:
1091 7ba0 ce 00 80                  	ldx	#ram2_min	; Setup to check out ram2.  All addrs SB 00.
1092                                
1093                                ram2cmos_chklp:
1094 7ba3 e6 00                     	ldab	0,x		; read device location.  This will set CCs.
1095 7ba5 26 08                     	bne	#ram2cmos_err	; if not zero goto error routine.
1096                                
1097                                ram2cmos_reent:			; if error goes away in errloop then re-enter.
1098 7ba7 08                        	inx			; inc x.
1099 7ba8 8c 01 00                  	cpx	#ram2_max+1	; check if done.
1100 7bab 26 f6                     	bne	#ram2cmos_chklp	; loop if not done
1101 7bad 20 e8                     	bra	#ram2cmos_lp	; current did not overwrite, next cmos address.
1102                                
1103                                ram2cmos_err:
1104 7baf 7f ff fe                  	clr	#reset_vector	;failure check in.  Write to read only space.
1105 7bb2 f6 78 00                  	ldab	error_action	;sets CCs.
1106 7bb5 27 03                     	beq	#ram2cmos_errlp	;no flash error.
1107 7bb7 7e 7d 29                  	jmp	flash_error	;
1108                                
1109                                ram2cmos_errlp:
1110 7bba 6f 00                     	clr	0,x		; clear overwritten location.
1111 7bbc 34                        	des			; sp will always be fail addr+1. fix it.
1112 7bbd 36                        	psha			; write to suspect location.
1113 7bbe e6 00                     	ldab	0,x		; check for failure.  This sets CCs.
1114 7bc0 26 f8                     	bne	#ram2cmos_errlp	; continue to loop on error if failing.
1115 7bc2 20 e3                     	bra	#ram2cmos_reent	; failure not solid;continue.
1116                                
1117                                ram2cmos_pass:
1118                                
1119 7bc4 c6 01                     	ldab	#$1		;flash #6.  ram2 unique from ram1 & cmos.
1120                                				; by ram1 or by cmos.
1121 7bc6 ce 7b cc                  	ldx	#ram2cmos_return	;x now has return address.
1122 7bc9 7e 7d 50                  	jmp	#flash_sp_svc	;go flash.
1123                                ram2cmos_return:
1124                                
1125                                ;=============================================================================
1126                                
1127                                
1128 7bcc 8e 00 4f                  	lds	#stack_strt	;initialize stack pointer; stack is ready.
1129                                
1130                                ; This is the start of called routines; Ie the stack must be ready.
1131                                
1132                                
1133                                ;=============================================================================
1134                                
1135 7bcf bd 7b f5                  	jsr	cmos_data_test	;go test cmos data.
1136 7bd2 c6 01                     	ldab	#$01		;setup for one flash.
1137 7bd4 bd 7d ca                  	jsr	flash_svc	;flash #7.  cmos data test passed.
1138                                
1139 7bd7 bd 7c 21                  	jsr	cmos_addr_test	;go test cmos addressing.
1140 7bda c6 01                     	ldab	#$01		;setup for one flash.
1141 7bdc bd 7d ca                  	jsr	flash_svc	;flash #8.  cmos address test passed.
1142                                
1143 7bdf ce 28 00                  	ldx	#pia1_sel	;setup to test the pia on the mpu.
1144 7be2 df 50                     	stx	var_1		;var_1 now has pia base address.
1145 7be4 bd 7c c7                  	jsr	pia_test	;go do the test.
1146 7be7 c6 01                     	ldab	#$01		;setup for one flash.
1147 7be9 bd 7d ca                  	jsr	flash_svc	;flash #9.  pia1 the mpu pia test passed.
1148                                
1149                                
1150 7bec ce 75 30                  	ldx	#30000
1151                                
1152                                delay:		;delay flashing for a moment before next pass of tests.
1153                                
1154 7bef 09                        	dex			; should decrement x by 1.
1155 7bf0 26 fd                     	bne	#delay		; delay between passes.
1156 7bf2 7e 78 5a                  	jmp	start		; goto start.
1157                                
1158                                
1159                                ;=============================================================================
1160                                
1161                                
1162                                	; This is start of cmos testing of both data and addressing.
1163                                	; Because the 5101 CMOS Ram is only 4 bits wide; we take some
1164                                	; great pains to see to it that we find conflicting addresses
1165                                	; in the address uniqueness test for this part for a scope loop.
1166                                	; the pain however is well worth the gain for using a scope or
1167                                	; especially an analyzer.
1168                                	;
1169                                	; Note:  The CMOS is assumed to be a unique device at this point as
1170                                	; it has not interfered with any other test.  It most likely
1171                                	; would have messed up some other device test were it not unique.
1172                                
1173                                cmos_data_test:
1174                                
1175                                ;	cmos_data attempts to check that each cell can hold any
1176                                ;	data pattern in the 5101.  address has not been qualified yet.
1177                                
1178                                
1179 7bf5 ce 01 00                  	ldx	#cmos_min
1180                                
1181                                cmos_d_nextadr:
1182 7bf8 86 00                     	ldaa	#$0		;aa will be expected data
1183 7bfa c6 ff                     	ldab	#$ff		;ab will be actual. Init to anything else; we
1184                                				;start at zero so this must get zero on a read
1185 7bfc 20 0b                     	bra	cmos_d_datloop	
1186                                
1187                                cmos_d_errloop:
1188 7bfe 7f ff fe                  	clr	#reset_vector	;failure check in.  Write to read only space.
1189 7c01 f6 78 00                  	ldab	error_action	;sets CCs.
1190 7c04 27 03                     	beq	#cmos_d_datloop	;no flash error.
1191 7c06 7e 7d 29                  	jmp	flash_error	;
1192                                
1193                                cmos_d_datloop:
1194 7c09 84 0f                     	anda	#$0f		;5101 is only 4 bits wide.  Mask unused bits.
1195 7c0b a7 00                     	staa	0,x		;write to the 5101.
1196 7c0d e6 00                     	ldab	0,x		;read from the 5101.
1197 7c0f c4 0f                     	andb	#$0f		;5101 is only 4 bits wide.  Mask unused bits.
1198 7c11 11                        	cba			;compare a and b accumulators.
1199 7c12 26 ea                     	bne	#cmos_d_errloop	;loop on the error till it clears.
1200 7c14 8b 01                     	adda	#$01		;inca on MSB side, lsb 4 bits stay zero.
1201 7c16 84 0f                     	anda	#$0f		;just to be sure.
1202 7c18 26 ef                     	bne	#cmos_d_datloop	;data is 00-FF on FF we roll to 00 indicating
1203                                				;we have checked all data on current address.
1204 7c1a 08                        	inx			;inc x to next addr.
1205 7c1b 8c 02 00                  	cpx	#cmos_max+1	;if past max addr then we are done.
1206 7c1e 26 d8                     	bne	#cmos_d_nextadr	;not done; do next address.
1207                                
1208 7c20 39                        	rts			;return to caller.
1209                                
1210                                ;===========================================================================
1211                                
1212                                cmos_addr_test:
1213 7c21 ce 01 00                  	ldx	#cmos_min		;5101 starting address
1214 7c24 86 00                     	ldaa	#$0		;aa will be expected data
1215 7c26 97 50                     	staa	var_1		;Clear variable located in 6810 used for uniq.
1216 7c28 c6 ff                     	ldab	#$ff		;ab will be actual. Init to anything else; we
1217                                				;start at zero so this must get zero on a read
1218 7c2a 20 0b                     	bra	#cmos_a_datloop
1219                                
1220                                cmos_a_errloop:
1221 7c2c 7f ff fe                  	clr	#reset_vector	;failure check in.  Write to read only space.
1222 7c2f f6 78 00                  	ldab	error_action	;sets CCs.
1223 7c32 27 03                     	beq	#cmos_a_datloop	;no flash error.
1224 7c34 7e 7d 29                  	jmp	flash_error	;
1225                                
1226                                cmos_a_datloop:
1227 7c37 9b 50                     	adda	var_1		;A+M->A var_1 allows us to do uniqueness.
1228 7c39 84 0f                     	anda	#$0f		;5101 is only 4 bits wide.  Mask unused bits.
1229 7c3b a7 00                     	staa	0,x		;write to the 5101.
1230 7c3d e6 00                     	ldab	0,x		;read/verify data.
1231 7c3f c4 0f                     	andb	#$0f		;5101 is only 4 bits wide.  Mask unused bits.
1232 7c41 11                        	cba			;compare a and b accumulators.
1233 7c42 26 e8                     	bne	#cmos_a_errloop	;loop on the error till it clears.
1234 7c44 8b 01                     	adda	#$01		;inca. msb, already has the uniq cnt offset.
1235 7c46 84 0f                     	anda	#$0f		;5101 is only 4 bits wide.  Mask unused bits.
1236 7c48 26 08                     	bne 	cmos_continue	;on 0 we will increment var_1.
1237 7c4a d6 50                     	ldab	var_1		;get current cnt in b.
1238 7c4c cb 01                     	addb	#$01		;inc b (really cnt) used to provide addr uniq.
1239 7c4e c4 0f                     	andb	#$0f		;5101 is only 4 bits wide.  Mask unused bits.
1240 7c50 d7 50                     	stab	var_1		;put new count back in cnt.
1241                                cmos_continue:
1242 7c52 08                        	inx			;inc x to next addr.
1243 7c53 8c 02 00                  	cpx	#cmos_max+1	;if past max addr then we are done.
1244 7c56 26 df                     	bne	#cmos_a_datloop	;not done; do next address.
1245                                
1246                                cmos_addr_uniq:
1247                                
1248                                cmos_uclr:
1249 7c58 ce 01 00                  	ldx	#cmos_min		;Start addr of 5101.
1250 7c5b 86 00                     	ldaa	#$0
1251                                
1252                                cmos_uclr_addr:
1253 7c5d a7 00                     	staa	0,x		;clear 5101.
1254 7c5f 08                        	inx			;inc x to next addr.
1255 7c60 8c 02 00                  	cpx	#cmos_max+1	;if past max addr then we are done.
1256 7c63 26 f8                     	bne	#cmos_uclr_addr	;not done.
1257                                
1258 7c65 ce 01 00                  	ldx	#cmos_min
1259 7c68 86 0f                     	ldaa	#$0f		;pattern to write to 5101.
1260                                
1261                                cmos_uloop:
1262 7c6a e6 00                     	ldab	0,x		;check before writing.
1263 7c6c c4 0f                     	andb	#$0f		;mask out unused bits.
1264 7c6e c1 00                     	cmpb	#$0		;verify loc is zero.	
1265 7c70 26 09                     	bne	cmos_uerror	;go try to loop on error.
1266 7c72 a7 00                     	staa	0,x		;loc was zero; write pattern to loc.
1267 7c74 08                        	inx			;next loc.
1268 7c75 8c 02 00                  	cpx	#cmos_max+1	;check if done.
1269 7c78 26 f0                     	bne	cmos_uloop	;not done.
1270                                
1271 7c7a 39                        	rts			;return to caller.
1272                                
1273                                cmos_uerror:
1274 7c7b df 50                     	stx	var_1		;loc that was in error.
1275 7c7d 6f 00                     	clr	0,x		;clear error loc.
1276 7c7f ce 01 00                  	ldx	#cmos_min	;setup to find location that overwrote
1277                                				;the location just stored in var_1.
1278 7c82 86 0f                     	ldaa	#$0f		;reload a with same data.
1279                                
1280                                cmos_find_loc:
1281                                
1282 7c84 a7 00                     	staa	0,x
1283 7c86 35                        	txs			;hold x in sp for a moment.
1284 7c87 de 50                     	ldx	var_1		;now get fail addr to check.
1285 7c89 e6 00                     	ldab	0,x		;
1286 7c8b 30                        	tsx			;put x held in sp back into x.
1287 7c8c c4 0f                     	andb	#$0f		;mask out unused bits.
1288 7c8e df 52                     	stx	var_2		;Addr in var_2 confilicts with addr in var_1.
1289 7c90 c1 00                     	cmpb	#$0		;check error loc was still zero.  If not,
1290 7c92 26 12                     	bne	cmos_uerr_loop	;then try again.
1291 7c94 08                        	inx			;try next loc.
1292 7c95 9c 50                     	cpx	var_1		;don't need to go past addr in var_1.
1293 7c97 27 1b                     	beq	cmos_unot	;did not find bad address.	
1294                                
1295 7c99 86 0f                     	ldaa	#$0f		;to be safe.
1296                                
1297                                cmos_uerr_lloop:
1298 7c9b 7f ff fe                  	clr	#reset_vector	;failure check in.  Write to read only space.
1299 7c9e f6 78 00                  	ldab	error_action	;sets CCs.
1300 7ca1 27 03                     	beq	#cmos_uerr_loop	;no flash error.
1301 7ca3 7e 7d 29                  	jmp	flash_error	;
1302                                
1303                                cmos_uerr_loop:
1304                                		
1305 7ca6 6f 00                     	clr	0,x		;clear the addr in var_2.
1306 7ca8 de 50                     	ldx	var_1		;address that destroyed data in loc var_2.
1307 7caa a7 00                     	staa	0,x		;write to var_1 should wipe data in var_2 addr.
1308 7cac de 52                     	ldx	var_2		;check we destroyed data var_2 addr.
1309 7cae e6 00                     	ldab	0,x		;read.
1310 7cb0 c4 0f                     	andb	#$0f		;mask unused.
1311 7cb2 26 e7                     	bne	cmos_uerr_lloop	;stay in as long as we are failing.
1312                                
1313                                cmos_unot:
1314 7cb4 c6 03                     	ldab	#$3
1315 7cb6 bd 7e 1a                  	jsr	sflash_svc	;Flash 3 short so we know that the error was 
1316 7cb9 7e 78 5a                  	jmp	start		;not located, we will re-start the test.
1317                                
1318                                ;===========================================================================
1319                                
1320                                	; pia_test is a called routine.
1321                                	; var_1 on entry contains the base enable addr for the pia to test.
1322                                	; On error this call will loop on the error. On Pass it will return.
1323                                	; to the caller (depending on the setting of error_action).
1324                                
1325                                pia_test_err:
1326 7cbc 7f ff fe                  	clr	#reset_vector	;failure check in.  Write to read only space.
1327 7cbf f6 78 00                  	ldab	error_action	;sets CCs.
1328 7cc2 27 03                     	beq	#pia_test	;no flash error.
1329 7cc4 7e 7d 29                  	jmp	flash_error	;
1330                                
1331                                pia_test:
1332 7cc7 de 50                     	ldx	var_1		;x has pia enable base addr.
1333 7cc9 86 00                     	ldaa	#pia_ddr_reg	;access ddr reg.
1334 7ccb a7 01                     	staa	cra_sel,x	;set ddr access.  PIA is now setup.
1335 7ccd 4f                        	clra			;
1336 7cce a7 02                     	staa	pia_reg_b_sel,x	;should clear ddrb reg.
1337 7cd0 86 aa                     	ldaa	#$AA		;test pattern.
1338 7cd2 a7 00                     	staa	pia_reg_a_sel,x	;should write to ddra reg.
1339 7cd4 e6 00                     	ldab	pia_reg_a_sel,x	;should read from ddra reg.
1340 7cd6 11                        	cba			;compare expected in A to actual in B.
1341 7cd7 26 e3                     	bne	#pia_test_err	;loop on error.
1342                                
1343 7cd9 4f                        	clra			;clear a reg to verify ddrb was unique in pia.
1344 7cda e6 02                     	ldab	pia_reg_b_sel,x	;ddrb should still be clear if unique.
1345 7cdc 11                        	cba			;compare expected in A to actual in B.
1346 7cdd 26 dd                     	bne	#pia_test_err	;loop on error.  Not unique.
1347 7cdf 20 0b                     	bra	#pia_loop1	;continue test.
1348                                
1349                                pia_loop1_err:
1350 7ce1 7f ff fe                  	clr	#reset_vector	;failure check in.  Write to read only space.
1351 7ce4 f6 78 00                  	ldab	error_action	;sets CCs.
1352 7ce7 27 03                     	beq	#pia_loop1	;no flash error.
1353 7ce9 7e 7d 29                  	jmp	flash_error	;
1354                                
1355                                pia_loop1:
1356 7cec 86 55                     	ldaa	#$55		;test pattern.
1357 7cee a7 00                     	staa	pia_reg_a_sel,x	;should write to ddra reg.
1358 7cf0 e6 00                     	ldab	pia_reg_a_sel,x	;should read from ddra reg.
1359 7cf2 11                        	cba			;compare expected in A to actual in B.
1360 7cf3 26 ec                     	bne	#pia_loop1_err	;loop on error.
1361 7cf5 20 0b                     	bra	#pia_loop2	;continue test.
1362                                
1363                                pia_loop2_err:
1364 7cf7 7f ff fe                  	clr	#reset_vector	;failure check in.  Write to read only space.
1365 7cfa f6 78 00                  	ldab	error_action	;sets CCs.
1366 7cfd 27 03                     	beq	#pia_loop2	;no flash error.
1367 7cff 7e 7d 29                  	jmp	flash_error	;
1368                                
1369                                pia_loop2:			;start checking ddrb reg.
1370 7d02 4f                        	clra			;
1371 7d03 a7 00                     	staa	pia_reg_a_sel,x	;clear ddra for uniqueness check.
1372 7d05 86 55                     	ldaa	#$55		;test pattern.
1373 7d07 a7 02                     	staa	pia_reg_b_sel,x	;should write to ddrb reg.
1374 7d09 e6 02                     	ldab	pia_reg_b_sel,x	;should read from ddrb reg.
1375 7d0b 11                        	cba			;compare expected in A to actual in B.
1376 7d0c 26 e9                     	bne	#pia_loop2_err	;loop on error.
1377 7d0e 20 0b                     	bra	#pia_loop3	;continue testing.
1378                                
1379                                pia_loop3_err:
1380 7d10 7f ff fe                  	clr	#reset_vector	;failure check in.  Write to read only space.
1381 7d13 f6 78 00                  	ldab	error_action	;sets CCs.
1382 7d16 27 03                     	beq	#pia_loop3	;no flash error.
1383 7d18 7e 7d 29                  	jmp	flash_error	;
1384                                
1385                                pia_loop3:	
1386 7d1b 86 aa                     	ldaa	#$AA		;test pattern.
1387 7d1d a7 02                     	staa	pia_reg_b_sel,x	;should write to ddrb reg.
1388 7d1f e6 02                     	ldab	pia_reg_b_sel,x	;should read from ddrb reg.
1389 7d21 11                        	cba			;compare expected in A to actual in B.
1390 7d22 26 ec                     	bne	#pia_loop3_err	;loop on error.
1391 7d24 e6 00                     	ldab	pia_reg_a_sel,x	;ddra should still be clear.  Set CCs.
1392 7d26 26 cf                     	bne	#pia_loop2_err	;we loop back to 2 to see all writes in loop.
1393                                
1394 7d28 39                        	rts			;If here we passed.  Return to caller.
1395                                
1396                                ;===========================================================================
1397                                
1398                                ;=============================================================================
1399                                ;
1400                                ;	Service type routines are below such as flashing the LEDs.
1401                                ;
1402                                ;=============================================================================
1403                                
1404                                ;===========================================================================
1405                                
1406                                	; flash_error.
1407                                	; This will set the b register to 5 flashes and jmp to
1408                                	; sflash_sp_svc.  This routine does not return, it restarts.
1409                                
1410                                
1411                                flash_error:			;we do not plan to return so we do much.
1412                                				;and the heck with the stack.  It matters not.
1413 7d29 ce 4e 20                  	ldx	#20000		;delay so we can tell the difference.
1414                                				;when looping.
1415                                flash_err_delay:
1416 7d2c 09                        	dex
1417 7d2d 26 fd                     	bne	#flash_err_delay ; Delay to see flashes clearly.
1418                                
1419 7d2f c6 05                     	ldab	#$5		;b now holds the number of times to flash.
1420 7d31 ce 7d 37                  	ldx	#flash_err_ret	;x has return address.
1421 7d34 7e 7d 8d                  	jmp	sflash_sp_svc	;Go flash the light 5 short times.
1422                                				;sflash_sp returns to caller in x.
1423                                flash_err_ret:
1424 7d37 b6 78 00                  	ldaa	error_action	;Find out what to do here.
1425 7d3a 81 00                     	cmpa	#loop_val	;
1426 7d3c 27 08                     	beq	#flash_error_rst	;go restart tests ie: loop.
1427 7d3e 81 02                     	cmpa	#halt_val	;
1428 7d40 27 07                     	beq	#halt_loop	;effectively halt the testing.
1429 7d42 81 01                     	cmpa	#restart_val	;
1430 7d44 27 00                     	beq	#flash_error_rst	;go restart tests.
1431                                				;any other value will currently restart also,
1432                                				;but is not guaranteed to do so in later
1433                                				;revisions.
1434                                flash_error_rst:
1435 7d46 7e 78 5a                  	jmp	start		;flash complete, now restart from scratch.
1436                                
1437                                ;===========================================================================
1438                                
1439                                		;This loop does nothing and is an infinite loop on itself
1440                                		;as there is no halt instruction for the 6800.
1441                                halt_loop:
1442 7d49 7f ff fe                  	clr	#reset_vector	;failure check in.  Write to read only space.
1443                                halt_lp:
1444 7d4c 01                        	nop
1445 7d4d 01                        	nop
1446 7d4e 20 fc                     	bra	#halt_lp	;loop on nothing to simulate a halted program.
1447                                
1448                                
1449                                ;===========================================================================
1450                                
1451                                
1452                                
1453                                ;===========================================================================
1454                                
1455                                flash_sp_svc:
1456                                ;	Attempt to flash the light n times based on contents of ab.
1457                                ;
1458                                ;	On entry x has return address.  We need to store it into the
1459                                ;	sp and then we can restore it.  This routine does not use
1460                                ;	any stack space nor does it push or pull anything to or from
1461                                ;	the stack.  The SP itself is utilized as a holding register.
1462                                ;	This routine may not change the x register prior to the txs
1463                                ;	instruction and may not subsequently change the sp register.
1464                                
1465 7d50 35                        	txs			; x is holding the return address, save in sp.
1466                                
1467                                flash_sp_lp:
1468                                
1469 7d51 ce 28 00                  	ldx	#pia1_sel	;x has pia1 enable base addr.  addr of pia1
1470 7d54 86 38                     	ldaa	#pia_ddr_reg+led_on	;set to select ddra, cra 3,4,5 set.
1471 7d56 a7 01                     	staa	cra_sel,x	;ddra is now selected, cra 3,4,5 now set.
1472 7d58 86 30                     	ldaa	#led_bits	;set bits 4 and 5 for led select in ddr.
1473 7d5a a7 00                     	staa	ddra_sel,x	;setup mask in ddra.
1474 7d5c 86 04                     	ldaa	#pia_out_reg	;bits for CRA to access PRA.
1475 7d5e a7 01                     	staa	cra_sel,x	;set CRA.
1476 7d60 86 30                     	ldaa	#led_bits_on	;try to light Both LEDs.
1477 7d62 a7 00                     	staa	pra_sel,x	;set bits in PRA.
1478 7d64 86 3c                     	ldaa	#pia_out_reg+led_on	;Should be 3C.
1479 7d66 a7 01                     	staa	cra_sel,x	;do it.  Should now be accessing outreg.
1480 7d68 a7 01                     	staa	cra_sel,x	;do it.  Twice to be sure. CA2 should be high.
1481                                
1482 7d6a ce 75 30                  	ldx	#30000		;LED On count.
1483                                
1484                                flash_sp_on:
1485                                
1486 7d6d 09                        	dex			; should decrement x by 1.
1487 7d6e 26 fd                     	bne	#flash_sp_on	; keep on for LED on count. 
1488                                
1489                                ;	setup to turn off now to complete flash.
1490                                
1491                                flash_sp_ofent:			;flash_sp_ofent expects return addr in sp.
1492 7d70 ce 28 00                  	ldx	#pia1_sel	;x has pia1 enable base addr.  addr of pia1
1493 7d73 86 30                     	ldaa	#pia_ddr_reg+led_off	;set to select ddra, cra 2,3,4 set.
1494 7d75 a7 01                     	staa	cra_sel,x	;ddra is now selected, cra 2,3,4 now set.
1495 7d77 86 34                     	ldaa	#pia_out_reg+led_off	;Should be 34.
1496 7d79 a7 01                     	staa	cra_sel,x	;do it.  Should now be accessing outreg.
1497 7d7b a7 01                     	staa	cra_sel,x	;do it.  Twice to be sure. CA2 should be high.
1498 7d7d 86 00                     	ldaa	#led_bits_off	;to reset pa4 pa5 and turn off LEDs.
1499 7d7f a7 00                     	staa	pra_sel,x	;PA4 AND PA5 SHOULD HAVE GONE LOW. LEDs OFF.
1500                                
1501 7d81 ce 75 30                  	ldx	#30000		;LED Off count.
1502                                
1503                                flash_sp_off:
1504 7d84 09                        	dex			; should decrement x by 1.
1505 7d85 26 fd                     	bne	#flash_sp_off	; keep off for LED off count. 
1506 7d87 5a                        	decb
1507 7d88 26 c7                     	bne	#flash_sp_lp	; go till done flashing.
1508                                
1509 7d8a 30                        	tsx			; restore return address from the sp.
1510 7d8b 6e 00                     	jmp	0,x		; return to caller.
1511                                
1512                                ;===========================================================================
1513                                
1514                                sflash_sp_svc:
1515                                ;	Attempt to flash the light n times based on contents of ab.
1516                                ;
1517                                ;	On entry x has return address.  We need to store it into the
1518                                ;	sp and then we can restore it.  This routine does not use
1519                                ;	any stack space nor does it push or pull anything to or from
1520                                ;	the stack.  The SP itself is utilized as a holding register.
1521                                ;	This routine may not change the x register prior to the txs
1522                                ;	instruction and may not subsequently change the sp register.
1523                                
1524 7d8d 35                        	txs			; x is holding the return address, save in sp.
1525                                
1526                                sflash_sp_lp:
1527                                
1528 7d8e ce 28 00                  	ldx	#pia1_sel	;x has pia1 enable base addr.  addr of pia1
1529 7d91 86 38                     	ldaa	#pia_ddr_reg+led_on	;set to select ddra, cra 3,4,5 set.
1530 7d93 a7 01                     	staa	cra_sel,x	;ddra is now selected, cra 3,4,5 now set.
1531 7d95 86 30                     	ldaa	#led_bits	;set bits 4 and 5 for led select in ddr.
1532 7d97 a7 00                     	staa	ddra_sel,x	;setup mask in ddra.
1533 7d99 86 04                     	ldaa	#pia_out_reg	;bits for CRA to access PRA.
1534 7d9b a7 01                     	staa	cra_sel,x	;set CRA.
1535 7d9d 86 30                     	ldaa	#led_bits_on	;try to light Both LEDs.
1536 7d9f a7 00                     	staa	pra_sel,x	;set bits in PRA.
1537 7da1 86 3c                     	ldaa	#pia_out_reg+led_on	;Should be 3C.
1538 7da3 a7 01                     	staa	cra_sel,x	;do it.  Should now be accessing outreg.
1539 7da5 a7 01                     	staa	cra_sel,x	;do it.  Twice to be sure. CA2 should be high.
1540                                
1541 7da7 ce 27 10                  	ldx	#10000		;LED On count.
1542                                
1543                                sflash_sp_on:
1544                                
1545 7daa 09                        	dex			; should decrement x by 1.
1546 7dab 26 fd                     	bne	#sflash_sp_on	; keep on for LED on count. 
1547                                
1548                                ;	setup to turn off now to complete flash.
1549                                
1550                                sflash_sp_ofent:		;sflash_sp_ofent expects return addr in sp.
1551 7dad ce 28 00                  	ldx	#pia1_sel	;x has pia1 enable base addr.  addr of pia1
1552 7db0 86 30                     	ldaa	#pia_ddr_reg+led_off	;set to select ddra, cra 2,3,4 set.
1553 7db2 a7 01                     	staa	cra_sel,x	;ddra is now selected, cra 2,3,4 now set.
1554 7db4 86 34                     	ldaa	#pia_out_reg+led_off	;Should be 34.
1555 7db6 a7 01                     	staa	cra_sel,x	;do it.  Should now be accessing outreg.
1556 7db8 a7 01                     	staa	cra_sel,x	;do it.  Twice to be sure. CA2 should be high.
1557 7dba 86 00                     	ldaa	#led_bits_off	;to reset pa4 pa5 and turn off LEDs.
1558 7dbc a7 00                     	staa	pra_sel,x	;PA4 AND PA5 SHOULD HAVE GONE LOW. LEDs OFF.
1559                                
1560 7dbe ce 27 10                  	ldx	#10000		;LED Off count.
1561                                
1562                                sflash_sp_off:
1563 7dc1 09                        	dex			; should decrement x by 1.
1564 7dc2 26 fd                     	bne	#sflash_sp_off	; keep off for LED off count. 
1565 7dc4 5a                        	decb
1566 7dc5 26 c7                     	bne	#sflash_sp_lp	; go till done flashing.
1567                                
1568 7dc7 30                        	tsx			; restore return address from the sp.
1569 7dc8 6e 00                     	jmp	0,x		; return to caller.
1570                                
1571                                ;===========================================================================
1572                                
1573                                flash_svc:
1574                                ;	attempt to flash the light. n times based on contents of b register.
1575                                
1576                                
1577 7dca d7 58                     	stab	temp		;b has count need to hold b reg temporarily.
1578 7dcc 36                        	psha			; 
1579 7dcd df 56                     	stx	x_place		; setup to push x also.
1580 7dcf 96 56                     	ldaa	x_place		;
1581 7dd1 d6 57                     	ldab	x_place+1	;
1582 7dd3 36                        	psha			; x high onto stack
1583 7dd4 37                        	pshb			; x low onto stack
1584 7dd5 d6 58                     	ldab	temp		; b should now have the flash count again.
1585                                
1586                                flash_svc_lp:
1587 7dd7 ce 28 00                  	ldx	#pia1_sel	;x has pia1 enable base addr.  addr of pia1
1588 7dda 86 38                     	ldaa	#pia_ddr_reg+led_on	;set to select ddra, cra 3,4,5 set.
1589 7ddc a7 01                     	staa	cra_sel,x	;ddra is now selected, cra 3,4,5 now set.
1590 7dde 86 30                     	ldaa	#led_bits	;set bits 4 and 5 for led select in ddr.
1591 7de0 a7 00                     	staa	ddra_sel,x	;setup mask in ddra.
1592 7de2 86 04                     	ldaa	#pia_out_reg	;bits for CRA to access PRA.
1593 7de4 a7 01                     	staa	cra_sel,x	;set CRA.
1594 7de6 86 30                     	ldaa	#led_bits_on	;try to light Both LEDs.
1595 7de8 a7 00                     	staa	pra_sel,x	;set bits in PRA.
1596 7dea 86 3c                     	ldaa	#pia_out_reg+led_on	;Should be 3C.
1597 7dec a7 01                     	staa	cra_sel,x	;do it.  Should now be accessing outreg.
1598 7dee a7 01                     	staa	cra_sel,x	;do it.  Twice to be sure. CA2 should be high.
1599                                
1600 7df0 ce 75 30                  	ldx	#30000		;LED On count.
1601                                
1602                                flash_on:
1603                                
1604 7df3 09                        	dex			; should decrement x by 1.
1605 7df4 26 fd                     	bne	#flash_on	; keep on for LED on count. 
1606                                
1607                                ;	setup to turn off now to complete flash.
1608                                
1609 7df6 ce 28 00                  	ldx	#pia1_sel	;x has pia1 enable base addr.  addr of pia1
1610 7df9 86 30                     	ldaa	#pia_ddr_reg+led_off	;set to select ddra, cra 2,3,4 set.
1611 7dfb a7 01                     	staa	cra_sel,x	;ddra is now selected, cra 2,3,4 now set.
1612 7dfd 86 34                     	ldaa	#pia_out_reg+led_off	;Should be 34.
1613 7dff a7 01                     	staa	cra_sel,x	;do it.  Should now be accessing outreg.
1614 7e01 a7 01                     	staa	cra_sel,x	;do it.  Twice to be sure. CA2 should be high.
1615 7e03 86 00                     	ldaa	#led_bits_off	;to reset pa4 pa5 and turn off LEDs.
1616 7e05 a7 00                     	staa	pra_sel,x	;PA4 AND PA5 SHOULD HAVE GONE LOW. LEDs OFF.
1617                                
1618 7e07 ce 75 30                  	ldx	#30000		;LED Off count.
1619                                
1620                                flash_off:
1621 7e0a 09                        	dex			; should decrement x by 1.
1622 7e0b 26 fd                     	bne	#flash_off	; keep off for LED off count. 
1623 7e0d 5a                        	decb
1624 7e0e 26 c7                     	bne	#flash_svc_lp	; go till done flashing.
1625                                
1626 7e10 33                        	pulb			;restoring x.
1627 7e11 32                        	pula			;restoring x.
1628 7e12 d7 57                     	stab	x_place+1	;restoring x.
1629 7e14 97 56                     	staa	x_place		;restoring x.
1630 7e16 de 56                     	ldx	x_place		;x is now restored.
1631 7e18 32                        	pula			;restore a.
1632 7e19 39                        	rts			; return to caller.
1633                                
1634                                ;===========================================================================
1635                                
1636                                sflash_svc:
1637                                ;	attempt to flash the light. n times based on contents of b register.
1638                                
1639                                
1640 7e1a d7 58                     	stab	temp		;b has count need to hold b reg temporarily.
1641 7e1c 36                        	psha			; 
1642 7e1d df 56                     	stx	x_place		; setup to push x also.
1643 7e1f 96 56                     	ldaa	x_place		; 
1644 7e21 d6 57                     	ldab	x_place+1	;
1645 7e23 36                        	psha			; x high onto stack
1646 7e24 37                        	pshb			; x low onto stack
1647 7e25 d6 58                     	ldab	temp		; b should now have the flash count again.
1648                                
1649                                sflash_svc_lp:
1650 7e27 ce 28 00                  	ldx	#pia1_sel	;x has pia1 enable base addr.  addr of pia1
1651 7e2a 86 38                     	ldaa	#pia_ddr_reg+led_on	;set to select ddra, cra 3,4,5 set.
1652 7e2c a7 01                     	staa	cra_sel,x	;ddra is now selected, cra 3,4,5 now set.
1653 7e2e 86 30                     	ldaa	#led_bits	;set bits 4 and 5 for led select in ddr.
1654 7e30 a7 00                     	staa	ddra_sel,x	;setup mask in ddra.
1655 7e32 86 04                     	ldaa	#pia_out_reg	;bits for CRA to access PRA.
1656 7e34 a7 01                     	staa	cra_sel,x	;set CRA.
1657 7e36 86 30                     	ldaa	#led_bits_on	;try to light Both LEDs.
1658 7e38 a7 00                     	staa	pra_sel,x	;set bits in PRA.
1659 7e3a 86 3c                     	ldaa	#pia_out_reg+led_on	;Should be 3C.
1660 7e3c a7 01                     	staa	cra_sel,x	;do it.  Should now be accessing outreg.
1661 7e3e a7 01                     	staa	cra_sel,x	;do it.  Twice to be sure. CA2 should be high.
1662                                
1663 7e40 ce 75 30                  	ldx	#30000		;LED On count.
1664                                
1665                                sflash_on:
1666                                
1667 7e43 09                        	dex			; should decrement x by 1.
1668 7e44 26 fd                     	bne	#sflash_on	; keep on for LED on count. 
1669                                
1670                                ;	setup to turn off now to complete flash.
1671                                
1672 7e46 ce 28 00                  	ldx	#pia1_sel	;x has pia1 enable base addr.  addr of pia1
1673 7e49 86 30                     	ldaa	#pia_ddr_reg+led_off	;set to select ddra, cra 2,3,4 set.
1674 7e4b a7 01                     	staa	cra_sel,x	;ddra is now selected, cra 2,3,4 now set.
1675 7e4d 86 34                     	ldaa	#pia_out_reg+led_off	;Should be 34.
1676 7e4f a7 01                     	staa	cra_sel,x	;do it.  Should now be accessing outreg.
1677 7e51 a7 01                     	staa	cra_sel,x	;do it.  Twice to be sure. CA2 should be high.
1678 7e53 86 00                     	ldaa	#led_bits_off	;to reset pa4 pa5 and turn off LEDs.
1679 7e55 a7 00                     	staa	pra_sel,x	;PA4 AND PA5 SHOULD HAVE GONE LOW. LEDs OFF.
1680                                
1681 7e57 ce 75 30                  	ldx	#30000		;LED Off count.
1682                                
1683                                sflash_off:
1684 7e5a 09                        	dex			; should decrement x by 1.
1685 7e5b 26 fd                     	bne	#sflash_off	; keep off for LED off count. 
1686 7e5d 5a                        	decb
1687 7e5e 26 c7                     	bne	#sflash_svc_lp	; go till done flashing.
1688                                
1689 7e60 33                        	pulb			;restoring x.
1690 7e61 32                        	pula			;restoring x.
1691 7e62 d7 57                     	stab	x_place+1	;restoring x.
1692 7e64 97 56                     	staa	x_place		;restoring x.
1693 7e66 de 56                     	ldx	x_place		;x is now restored.
1694 7e68 32                        	pula			;restore a.
1695 7e69 39                        	rts			; return to caller.
1696                                
1697                                ;===========================================================================
1698                                
1699 7ff8                           	org	ic17_end-7	; start of 6800 vector table.
1700                                
1701                                	; currently we will point all vectors to start for now.
1702                                	; maybe at some time we will mess with them.
1703                                
1704                                
1705                                	; Currently we will point most vectors to start for now.
1706                                	; Some day we may toy some more with them.
1707                                
1708 7ff8 7d 49                     	fdb	halt_loop	; FFF8,FFF9 IRQ	CURRENTLY NOT USED, HALT.
1709 7ffa 7d 49                     	fdb	halt_loop	; FFFA,FFFB SWI	CURRENTLY NOT USED, HALT.
1710 7ffc 78 47                     	fdb	show_revision	; FFFC,FFFD NMI CLEAR SWITCH (SW 33)
1711 7ffe 78 5a                     	fdb	start		; FFFE,FFFF RESET
1712                                
1713                                
1714                                ;===========================================================================

cmos_a_datloop   7c37 *1226 1218 1223 1244 
cmos_a_errloop   7c2c *1220 1233 
cmos_addr_test   7c21 *1212 1139 
cmos_addr_uniq   7c58 *1246 
cmos_continue    7c52 *1241 1236 
cmos_d_datloop   7c09 *1193 1185 1190 1202 
cmos_d_errloop   7bfe *1187 1199 
cmos_d_nextadr   7bf8 *1181 1206 
cmos_data_test   7bf5 *1173 1135 
cmos_find_loc    7c84 *1280 
cmos_init        7895 *0370 0377 
cmos_max         01ff *0214 0376 0713 1081 1205 1243 1255 1268 
cmos_min         0100 *0213 0368 0719 1087 1179 1213 1249 1258 1276 
cmos_uclr        7c58 *1248 
cmos_uclr_addr   7c5d *1252 1256 
cmos_uerr_lloop  7c9b *1297 1311 
cmos_uerr_loop   7ca6 *1303 1290 1300 
cmos_uerror      7c7b *1273 1265 
cmos_uloop       7c6a *1261 1269 
cmos_unot        7cb4 *1313 1293 
cra_sel          0001 *0224 0587 0591 0595 0596 0609 0611 0612 0954 0958 
                       0962 0963 0976 0978 0979 1334 1471 1475 1479 1480 1494 
                       1496 1497 1530 1534 1538 1539 1553 1555 1556 1589 1593 
                       1597 1598 1611 1613 1614 1652 1656 1660 1661 1674 1676 
                       1677 
crb_sel          0003 *0228 
ddra_sel         0000 *0226 0589 0956 1473 1532 1591 1654 
ddrb_sel         0002 *0230 
delay            7bef *1152 1155 
error_action     7800 *0278 0408 0452 0560 0688 0737 0775 0819 0927 1056 
                       1105 1189 1222 1299 1327 1351 1365 1381 1424 
flash_err_delay  7d2c *1415 1417 
flash_err_ret    7d37 *1423 1420 
flash_error      7d29 *1411 0410 0454 0562 0690 0739 0777 0821 0929 1058 
                       1107 1191 1224 1301 1329 1353 1367 1383 
flash_error_rst  7d46 *1434 1426 1430 
flash_off        7e0a *1620 1622 
flash_on         7df3 *1602 1605 
flash_sp_lp      7d51 *1467 1507 
flash_sp_ofent   7d70 *1491 0348 
flash_sp_off     7d84 *1503 1505 
flash_sp_on      7d6d *1484 1487 
flash_sp_svc     7d50 *1455 0427 0647 0754 0794 1016 1122 
flash_svc        7dca *1573 1137 1141 1147 
flash_svc_lp     7dd7 *1586 1624 
halt_loop        7d49 *1441 1428 1708 1709 
halt_lp          7d4c *1443 1446 
halt_val         0002 *0249 1427 
ic17_end         7fff *0206 1699 
ic17_strt        7800 *0205 0272 
ic20_end         77ff *0208 
ic20_strt        7000 *0207 
irq_vector       fff8 *0243 
led_1_bit        0020 *0236 
led_2_bit        0010 *0237 
led_bits         0030 *0240 0588 0955 1472 1531 1590 1653 
led_bits_off     0000 *0242 0613 0980 1498 1557 1615 1678 
led_bits_on      0030 *0241 0592 0959 1476 1535 1594 1657 
led_off          0030 *0239 0608 0610 0975 0977 1493 1495 1552 1554 1610 
                       1612 1673 1675 
led_on           0038 *0238 0586 0594 0953 0961 1470 1478 1529 1537 1588 
                       1596 1651 1659 
loop_val         0000 *0247 0279 1425 
nmi_vector       fffc *0245 
pass             7888 *0352 
pass_return      7890 *0357 0354 
pia1_mask        2803 *0215 
pia1_sel         2800 *0216 0585 0607 0952 0974 1143 1469 1492 1528 1551 
                       1587 1609 1650 1672 
pia2_mask        3003 *0217 
pia2_sel         3000 *0218 
pia3_mask        2403 *0219 
pia3_sel         2400 *0220 
pia4_mask        2203 *0221 
pia4_sel         2200 *0222 
pia_ddr_reg      0000 *0233 0586 0608 0953 0975 1333 1470 1493 1529 1552 
                       1588 1610 1651 1673 
pia_loop1        7cec *1355 1347 1352 
pia_loop1_err    7ce1 *1349 1360 
pia_loop2        7d02 *1369 1361 1366 
pia_loop2_err    7cf7 *1363 1376 1392 
pia_loop3        7d1b *1385 1377 1382 
pia_loop3_err    7d10 *1379 1390 
pia_out_reg      0004 *0234 0590 0594 0610 0957 0961 0977 1474 1478 1495 
                       1533 1537 1554 1592 1596 1612 1655 1659 1675 
pia_reg_a_sel    0000 *0223 1338 1339 1357 1358 1371 1391 
pia_reg_b_sel    0002 *0227 1336 1344 1373 1374 1387 1388 
pia_test         7cc7 *1331 1145 1328 
pia_test_err     7cbc *1325 1341 1346 
pra_sel          0000 *0225 0593 0614 0960 0981 1477 1499 1536 1558 1595 
                       1616 1658 1679 
prb_sel          0002 *0229 
ram1_aed_dec     790c *0495 0500 
ram1_aed_floop   7949 *0558 0575 
ram1_aed_found   7954 *0564 0545 0561 
ram1_aed_inc     791a *0507 0514 
ram1_aed_passed  79a3 *0630 0518 
ram1_aed_return  79b8 *0648 0646 
ram1_aed_test    7907 *0491 
ram1_aed_unot    7965 *0577 0551 
ram1_au0_ckdone  78fe *0469 0466 
ram1_au0_done    7907 *0476 0471 
ram1_au0_err     78df *0450 0462 0464 
ram1_au0_loop    78ea *0456 0448 0453 0467 0474 
ram1_au0_part    78da *0446 
ram1_au_nxt_adr  7934 *0539 0548 
ram1_au_nxt_dat  7930 *0535 0550 
ram1_d_datlp     78c1 *0412 0404 0409 0418 
ram1_d_errlp     78b6 *0406 0416 
ram1_d_nextadr   78b2 *0401 0422 
ram1_d_return    78d9 *0428 0426 
ram1_data        78af *0394 
ram1_find_loc    7929 *0529 0510 
ram1_max         007f *0210 0421 0470 0492 0493 0513 0637 0659 0681 0711 
                       0731 1032 
ram1_min         0000 *0209 0268 0392 0399 0447 0458 0459 0461 0463 0654 
                       0674 0705 0723 1038 
ram1_set_loop    79a8 *0633 0638 
ram1_u_clr       79bd *0656 0660 
ram1_u_test      79c5 *0662 
ram1_zflash      7967 *0582 0622 
ram1_zflash_off  799a *0618 0620 
ram1_zflash_on   7983 *0600 0603 
ram1cmos_chk     7a10 *0722 
ram1cmos_chklp   7a13 *0725 0732 
ram1cmos_clr     79fc *0708 0712 
ram1cmos_err     7a1f *0735 0727 
ram1cmos_errlp   7a2a *0741 0738 0746 
ram1cmos_lp      7a07 *0715 0733 
ram1cmos_pass    7a34 *0749 0720 
ram1cmos_reent   7a17 *0729 0747 
ram1cmos_return  7a3c *0755 0753 
ram1cmos_uniq    79f7 *0704 
ram1ram2_err     79e2 *0686 0678 
ram1ram2_errlp   79ed *0692 0689 0697 
ram1ram2_unxt    79f7 *0700 0670 
ram1ram2u_chk    79d3 *0673 
ram1ram2u_chklp  79d6 *0676 0682 0684 
ram1ram2u_lp     79ca *0666 0671 
ram1ram2u_reent  79da *0680 0698 
ram2_aed_dec     7a9e *0862 0867 
ram2_aed_floop   7adb *0925 0942 
ram2_aed_found   7ae6 *0931 0912 0928 
ram2_aed_inc     7aac *0874 0881 
ram2_aed_passed  7b35 *0999 0885 
ram2_aed_return  7b4a *1017 1015 
ram2_aed_test    7a99 *0858 
ram2_aed_unot    7af7 *0944 0918 
ram2_au0_ckdone  7a90 *0836 0833 
ram2_au0_done    7a99 *0843 0838 
ram2_au0_err     7a71 *0817 0829 0831 
ram2_au0_loop    7a7c *0823 0815 0820 0834 0841 
ram2_au0_part    7a6c *0813 
ram2_au_nxt_adr  7ac6 *0906 0915 
ram2_au_nxt_dat  7ac2 *0902 0917 
ram2_d_datlp     7a53 *0779 0771 0776 0785 
ram2_d_errlp     7a48 *0773 0783 
ram2_d_nextadr   7a44 *0768 0789 
ram2_d_return    7a6b *0795 0793 
ram2_data        7a41 *0761 
ram2_find_loc    7abb *0896 0877 
ram2_max         00ff *0212 0663 0788 0837 0859 0860 0880 1006 1030 1050 
                       1079 1099 
ram2_min         0080 *0211 0669 0759 0766 0814 0825 0826 0828 0830 1024 
                       1042 1073 1091 
ram2_set_loop    7b3a *1002 1007 
ram2_zflash      7af9 *0949 0989 
ram2_zflash_off  7b2c *0985 0987 
ram2_zflash_on   7b15 *0967 0970 
ram2cmos_chk     7ba0 *1090 
ram2cmos_chklp   7ba3 *1093 1100 
ram2cmos_clr     7b8c *1076 1080 
ram2cmos_err     7baf *1103 1095 
ram2cmos_errlp   7bba *1109 1106 1114 
ram2cmos_lp      7b97 *1083 1101 
ram2cmos_pass    7bc4 *1117 1088 
ram2cmos_reent   7ba7 *1097 1115 
ram2cmos_return  7bcc *1123 1121 
ram2cmos_uniq    7b87 *1072 
ram2ram1_chk     7b63 *1041 
ram2ram1_chklp   7b66 *1044 1051 
ram2ram1_clr     7b4f *1027 1031 
ram2ram1_err     7b72 *1054 1046 
ram2ram1_errlp   7b7d *1060 1057 1065 
ram2ram1_lp      7b5a *1034 1052 
ram2ram1_pass    7b87 *1068 1039 
ram2ram1_reent   7b6a *1048 1066 
ram2ram1_uniq    7b4a *1023 
reset_vector     fffe *0246 0407 0451 0559 0687 0736 0774 0818 0926 1055 
                       1104 1188 1221 1298 1326 1350 1364 1380 1442 
restart_val      0001 *0248 1429 
rev_x_lp         7854 *0304 0306 
revision_lp      7851 *0302 0308 
revision_ret     784f *0300 0298 
revision_val     0002 *0250 0286 0297 
sflash_off       7e5a *1683 1685 
sflash_on        7e43 *1665 1668 
sflash_sp_lp     7d8e *1526 1566 
sflash_sp_ofent  7dad *1550 
sflash_sp_off    7dc1 *1562 1564 
sflash_sp_on     7daa *1543 1546 
sflash_sp_svc    7d8d *1514 0299 0356 0386 1421 
sflash_svc       7e1a *1636 1315 
sflash_svc_lp    7e27 *1649 1687 
show_revision    7847 *0295 1710 
stack_strt       004f *0257 1128 
start            785a *0310 0624 0992 1156 1316 1435 1711 
start_return     78a1 *0381 0346 
start_return1    78aa *0387 0384 
swi_vector       fffa *0244 
temp             0058 *0265 1577 1584 1640 1647 
temp_0           0000 *0268 0499 0504 0505 0532 0537 0542 0547 0567 0572 
                       0866 0871 0872 0899 0904 0909 0914 0934 0939 
var_1            0050 *0261 1144 1215 1227 1237 1240 1274 1284 1292 1306 
                       1332 
var_2            0052 *0262 1288 1308 
var_3            0054 *0263 
x_place          0056 *0264 1579 1580 1581 1628 1629 1630 1642 1643 1644 
                       1691 1692 1693 


Number of errors 0
Number of warnings 0
