
  Assembling mpu200.asm
0001                                ;
0002                                ; Questions Comments etc... On this program may be directed to the
0003                                ; author at the following address (If you wish a reply please send a SASE)
0004                                ;
0005                                ; Dallas E. Overturf
0006                                ; 267 Main St
0007                                ; Ashland, MA 01721 (USA)
0008                                ;
0009                                ; e-mail:  overturf@ultranet.com
0010                                ;
0011                                ; Comments from the Author:
0012                                ;
0013                                ; If you decide to make your own version of the code either by patching
0014                                ; the binary or by changing the source; please be considerate and patch
0015                                ; patch the revision byte to a value of 01, 02, or 03 to indicate that the
0016                                ; copy is a hacked up copy.  I will not use revisions 01, 02, or 03 in a
0017                                ; released copy.  The first released copy will be revision 04.
0018                                ; If you modify the source; then please keep the Modification History 
0019                                ; and or Bug history sections updated as appropriate.
0020                                ;
0021                                ; The code:  This code was not written for efficiency and was done in
0022                                ; my spare time.  No doubt there are things I did that I could have done
0023                                ; better. It does work the way I intended it to so I'm not planning
0024                                ; on re-writing it!  If you submit a bug to me that I deem to be a valid
0025                                ; bug; I will probably fix it; if it can be reasonably fixed (my opinion).
0026                                ;
0027                                ; If you come up with something "great" you want added to this code I may
0028                                ; be willing to consider doing it if it seems reasonable (my opinion).
0029                                ; If you should take the time to improve upon it feel free to send me
0030                                ; a copy :)
0031                                ;
0032                                ;		Happy Pinballing!
0033                                ;					Dallas...
0034                                ;
0035                                ;
0036                                ; Modification history
0037                                ;
0038                                ; 12-10-92:  DEO  Rev 4.0. Initial Release to public domain.
0039                                ;		  
0040                                ;
0041                                ;
0042                                ; End Modification History
0043                                ; 
0044                                ; Rev 4.0 removed copyright comments. Still at 4.0
0045                                ;
0046                                ; Bug History / Status:
0047                                ;
0048                                ; 06-15-93:  DEO Rev 4.0.  The digits test did not work when actually
0049                                ; tested on a bally machine live (7 or 6 digit game) though it works
0050                                ; in my test jig Rev 3.0 same.  Need to retry with live mpu and live display.
0051                                ; Notes:  pia_test_3: if takes last error leaves LED on solid.
0052                                ; 11-28-96 Fixed by Oring led_off with the
0053                                ; cra ddr select value; see notes at pia_test3.
0054                                ;
0055                                ; Thoughts on additional tests:
0056                                ; A full pia test may be possible by making some special loopback cables
0057                                ; for the J2 and J3 connectors.  Also need to try out interrupts as well.
0058                                ; Possibly this should be a new test in a different prom; suggestions are;
0059                                ; Check interupts, then displays, then do full PIA test using some sort of
0060                                ; loopbacks.  We may be able to put out bad pia PA/PB lines in the displays
0061                                ; as well as flash a code for them?  Need to look at schematics.
0062                                ;
0063                                ; Testing Notes:
0064                                ;
0065                                ;	This test prom is placed into socket U6 to be used.
0066                                ;	Note socket U6 must be jumpered to match the prom type used.
0067                                ;	If this prom code is put into a 2732 it may be used in a U6
0068                                ;	socket that is jumpered as a 2716.
0069                                ;
0070                                ;	If this prom code is put into a 2532 EPROM; then U6 jumpering
0071                                ;	must be for a 9332 or 2532.
0072                                ;
0073                                ;	Special note on Bally AS2518-17 MPUs.  If the board is jumpered
0074                                ;	for a single 2732 to run the game in a socket other than U6; then
0075                                ;	the test prom should be run in that socket.
0076                                ;
0077                                ;	The test prom should be in the socket that will be enabled by
0078                                ;	an address of FFFE.  (the reset vector of the 6800).
0079                                ;
0080                                ;
0081                                ;	Programming the code into an EPROM:
0082                                ;	For a 2716 just program it in normal (IE: start address is 0000).
0083                                ;	If your burner requires an end address, it is 07FF.
0084                                ;
0085                                ;	For a 2732 or a 2532 the start address is 0800 (this means 0000-07FF
0086                                ;	remain blank.  If your burner requires an end address, it is 0FFF.
0087                                ;	(note in this case you are using the 2732 as a 2716)
0088                                ;
0089                                ;	Note:  If the binary file of this program is larger than 2048 bytes;
0090                                ;	and the file starts at address 0000; then you will need to give your
0091                                ;	prom programmer a starting address within the binary file as well to
0092                                ;	start taking data from.  In this case you need to give it address
0093                                ;	5800 which will be the offset (in hexadecimal) of the start of code
0094                                ;	in the binary file. (This is for a 2732 or 2532)
0095                                ;	You may use such a 2732 but not a 2532 in a U6  socket jumpered for
0096                                ;	either a 2732 or for a 2716 provided that only the upper half of
0097                                ;	the prom is programmed.  A 2532 must be jumpered as a 2532.
0098                                ;	Remember that the 6800's boot vector is in upper memory; thus
0099                                ;	this prom is written in upper memory and currently does not
0100                                ;	exceed the size of a 2716.  Thus it is good on both -17 and -35 mpus.
0101                                ;
0102                                ;
0103                                ;	It is recommended that you verify the prom in a known good board
0104                                ;	prior to attempting to use it on a bad board!
0105                                ;
0106                                ;	Things that may keep you from comming up and working correctly
0107                                ;	on the game rom that are untested in this game.
0108                                ;	INTERRUPTS!!  This test program specifically does not test program
0109                                ;	interrupts (the IRQ lines on the 6800 and PIAs).
0110                                ;
0111                                ;
0112                                ;	Some basic suggestions when trouble shooting a board:
0113                                ;
0114                                ;	If the test prom does not work at all; any remaning game rom in
0115                                ;	U1,U2,U3,U5 should also be removed.  This will help prove that
0116                                ;	there is not a bad game rom on the board.  If this test prom can
0117                                ;	get through it's set of tests on your mpu, and your game rom cannot
0118                                ;	flash the LED at least three times; then it is recommended that
0119                                ;	you try a different set of KNOWN GOOD game rom in your mpu to
0120                                ;	verify that your game rom are good.  Also it is recommended that
0121                                ;	you verify that the jumpers on the board are properly configured
0122                                ;	for the type of prom that you are using; especially in the case of
0123                                ;	a board that you have never seen working before.
0124                                ;	Note that if the Bally game rom turns off the LED this indicates
0125                                ;	that they have passed a checksum test and are likely to be good.
0126                                ;	If they cannot turn off the LED and this test prom passes; they
0127                                ;	are likely bad or a signal is bad at one of the game rom sockets
0128                                ;	they use, other than at socket U6.  Also verify jumpers match
0129                                ;	the prom you are using if you changed them to use the test prom.
0130                                ;
0131                                ;	With regards to this test prom:
0132                                ;	To get the initial "two short flashes" indicating the program is
0133                                ;	active, the only essential "normally" socketed chips on the board
0134                                ;	are as follows:  U9 (6800 processor) U11 (6820 or 6821) PIA and
0135                                ;	this test prom.
0136                                ;
0137                                ;	"Normally" socketed chips are:  U1 through U11 inclusive.
0138                                ;
0139                                ;	The first four flashes only require the following "normally"
0140                                ;	socketed chips in the board; The 6800 processor at U9, the 6810
0141                                ;	Static Ram in U7 and the U11 the (6820 or 6821) PIA.  U9 is in
0142                                ;	actuality only required to see the LED FLASH in this case.  It
0143                                ;	is not otherwise tested till much later.
0144                                ;	
0145                                ;	U8 the 5101 is additionally required to get through seven flashes.
0146                                ;
0147                                ;	U10 is additionally required to get through ten flashes.
0148                                ;	Note:  if not running MPU 200 tests you will also see flashes 
0149                                ;	11 and 12 occur; they are dummy flashes for consistency in this case.
0150                                ;	(so I don't have to re-document things!)
0151                                ;
0152                                ;	U13 is required to get through 12 flashes STERN MPU 200 only and
0153                                ;	only if test_mpu_200 is set to 01.  If it is set to 00 then
0154                                ;	flashes 11 and 12 will occur as dummy flashes.  Note that
0155                                ;	the dummy flashes are the flashes with a short "LED ON"
0156                                ;	time as opposed to the longer normal flashes.  This will
0157                                ;	allow the user to recognize when he is or is not really
0158                                ;	testing U13.
0159                                ;
0160                                ;	With the above in mind; if the board fails you may wish to remove
0161                                ;	all normally socketed chips not needed for the current failing test.
0162                                ;	example:  You do not get the two short flashes indicating the board
0163                                ;	is running or the LED stays on.  Remove all but the test chip in U6,
0164                                ;	U9, and U11.  If you still do not get the short flashes you have 
0165                                ;	elimiated many possible causes such as a chip being mistakenly
0166                                ;	selected or bad.  If you then do get the two short flashes with the
0167                                ;	excess chips out; you now have some idea that on of the chips removed
0168                                ;	is bad or being mistakenly selected.
0169                                ;
0170                                ; 
0171                                ;	This prom is intended to loop on errors and continue if the error
0172                                ;	goes away.  Thus it is not usefull for running overnight to see
0173                                ;	if there is a single intermittent error, as if the error goes away
0174                                ;	there will be no indication of it as the test will continue
0175                                ;	(note you could do this with a logic analzer attached).
0176                                ;	Note:  This action is affected by the setting of the "error_action"
0177                                ;	byte, described later.
0178                                ;
0179                                ;	Since the program in the prom must go over the same bus to the
0180                                ;	mpu as anything else on the board it is not very usefull for
0181                                ;	trouble shooting shorts on a data line or address line (EXCEPT
0182                                ;	with a logic analyzer and this listing) as the test program 
0183                                ;	probably will not be able to run.
0184                                ;
0185                                ;	This test program was designed with the intent of finding problems
0186                                ;	that are due to the battery corroding on the board.  This normally
0187                                ;	means an OPEN (broken) etch or bad connection within a socket.
0188                                ;	
0189                                ;	It is also designed to deal with LED on solid type problems; however
0190                                ;	to use this in most LED on solid conditions you will need to have
0191                                ;	a 24 channel logic analyzer at your disposal (8 data, 16 address)
0192                                ;	and of course this listing so you can see what went wrong.
0193                                ;
0194                                ;	This program checks the main address/data paths on Bally MPUs:
0195                                ; 	AS-2518-17, AS-2518-35, and AS-2518-133.
0196                                ;	
0197                                ;	Further it also will run on STERN MPU 100 and STERN MPU 200 MPUs.
0198                                ;
0199                                ;	Assuming the program code can be read out of the prom:
0200                                ;
0201                                ;	This prom will loop on errors and continue if the error
0202                                ;	goes away.  Thus it is not usefull for running overnight to see
0203                                ;	if there is a single intermittent error, as if the error goes away
0204                                ;	there will be no indication of it as the test will continue
0205                                ;	(note you could do this with a logic analzer attached).
0206                                ;	Note:  This is the default setup of the program.  This can
0207                                ;	be change by changing the "error_action" byte.  See below.
0208                                ;
0209                                ;
0210                                ;	Since the program in the prom must go over the same bus to the
0211                                ;	mpu as anything else on the board it is not very usefull for
0212                                ;	trouble shooting shorts on a data line or address line (EXCEPT
0213                                ;	with a logic analyzer and this listing) as the test program 
0214                                ;	probably will not be able to run.
0215                                ;
0216                                ;	The design of this test prom was for three main purposes:
0217                                ;
0218                                ;	1.  Allow troubleshooting of bus problems relatively quickly
0219                                ;		and easily using a 24 channel logic analyzer.  
0220                                ;
0221                                ;	2.  Also attempt to actively loop on an error so that the error
0222                                ;		may be more easily seen using an osciloscope or logic probe.
0223                                ;
0224                                ;	3.  Attempt (when possible) to be able to give the user a more 
0225                                ;		definitive visual clue to what was wrong with the bus.
0226                                ;		Ie:  data and or control was bad or the address lines
0227                                ;		are bad.
0228                                ;		Note:  The data test is always first for a part followed
0229                                ;		by addressing tests.  The initial data test will not fail
0230                                ;		(normally)due to an open address line to a component under
0231                                ;		test.
0232                                ;		It will fail due to a bad data line, or a bad control
0233                                ;		line.  Control lines are chip selects; R/W and Power/Ground.
0234                                ;		Thus if you pass the data test and fail the first addressing
0235                                ;		test you know you will most likely be looking for a bad
0236                                ;		address line.  If you fail a component uniqueness test
0237                                ;		then you are looking for a bad address/control line
0238                                ;		to one of the components that failed.
0239                                ;
0240                                ;
0241                                ;		Most problems on the bally MPU are due to corrosion from the
0242                                ;		battery (which normally results in open etches/pins).
0243                                ;		In most cases these problems involve U7, U8, and U11 and
0244                                ;		sometimes U6 as they are nearest the battery.  
0245                                ;		Problems involving the U11 PIA cannot easily be diagnosed
0246                                ;		without a logic	analyzer due to the fact that flashing the 
0247                                ;		LED requires the U11 PIA.  If the U6 socket is suspect due
0248                                ;		to corrosion you should check continuity of all pins back
0249                                ;		back to the processor, and control signals to their origins.
0250                                ;		Also verify that you have power and ground connections to U6. 
0251                                ;		
0252                                ;
0253                                ;
0254                                ;	Note:  Upon start of the program there will be two short flashes.
0255                                ;	This is done as a sanity check so that the user can see that the 
0256                                ;	actual test code has in fact started to run or is re-running.
0257                                ;
0258                                ;	Note:  for those using a logic analyzer the following occurs prior
0259                                ;	to seeing the two sanity check flashes:
0260                                ;
0261                                ;	Four data patterns are written out immediately after reset;
0262                                ;	they are: 00, FF, 55, and AA are written to address 0000.  
0263                                ;	They are immediately followed by four reads from the following
0264                                ;	addresses:  0000, FFFF, 5555, and AAAA.  (data here is random and 
0265                                ;	of no interest.)
0266                                ;	This is to allow analyzer users to verify basic data and address bus
0267                                ;	integrity.  If either is being held down or up; it should be
0268                                ;	immediately visable here using an analyzer.  The next thing that
0269                                ;	occurs will be the two short flashes that act as a sanity check for
0270                                ;	the user to verify that the program is running followed by the first
0271                                ;	test.
0272                                ;
0273                                ;
0274                                ;	The "error_action" byte settings located at program address 5800 or
0275                                ;	physical EPROM addresses 0000 (for 2716) or 0800 for (2732/2532).
0276                                ;
0277                                ;	If set to "restart_val" (02):
0278                                ;	Then all errors will, after writing to error_check in; jmp to an 
0279                                ;	error_flash routine which is responsible for flashing the LED 5
0280                                ;	times quickly and then restarting the test (based on further decode
0281                                ;	of the data) from the beginning.   This setting may be usefull for
0282                                ;	looking at intermittent problems.
0283                                ;
0284                                ;	If set to "halt_val":
0285                                ;	Then all errors will, after writing to error_check in; jmp to an 
0286                                ;	error_flash routine which is responsible for flashing the LED 5
0287                                ;	times quickly and then the 6800 processor will be put into an
0288                                ;	infinite do nothing loop (simulates a halt) that does absolutely 
0289                                ;	nothing.  This would allow the user to see that the test failed 
0290                                ;	an overnight run.  Since the test is no longer running the normal
0291                                ;	tests; the LED will not be flashing.
0292                                ;
0293                                ;	If set to loop_val (00):  
0294                                ;	The test will not flash five times nor will it restart.  Instead it
0295                                ;	attempts to loop on any error found until the error goes away.
0296                                ;	This setting is the most usefull for trouble shooting with a scope
0297                                ;	or logic probe if a logic analyzer is unavailble.  It is also fine
0298                                ;	for using a logic analyzer as well.
0299                                ;
0300                                ;
0301                                ;	The error_action byte will by default, be set to 00 (loop_val)
0302                                ;	when the EPROM is made.  The user may wish to make an archival
0303                                ;	copy of this prom and or set this byte to whatever he/she desires.
0304                                ;	It may be preferrable to keep two copies of the test prom handy;
0305                                ; 	each with a different setting of this byte.
0306                                ;
0307                                ;
0308                                ;	Error Check In Feature:   (For use with a logic analyzer)
0309                                ;
0310                                ;	On an error the program will attempt to write to the reset_vector
0311                                ;	of the 6800 (Address FFFE) in an attempt to allow triggering of
0312                                ;	an analyzer on an intermittent error.  This is known as the
0313                                ;	"error check in" location, and is READ ONLY.  Set the anlyzer to
0314                                ;	End trace on any write to address FFFE.  Data should be
0315                                ;	set to a don't care state.  The data you see is of no interest.
0316                                ;	The only thing that counts is that you do a write to address FFFE.
0317                                ;	You should be able to see what failed shortly before the error
0318                                ;	check in location is written.
0319                                ;
0320                                ;	Another good qualifier to use for any trace if you have more than 24
0321                                ;	channels available, is to trace on the address and or data you
0322                                ;	are interested in and qualify it with reset being false.
0323                                ;	Note:  Both Write (R/W) and Reset are low true signals; thus a
0324                                ;	logic "1" high indicates you are reading or not reset respectively;
0325                                ;	a 0 (low) would indicate you are writing or reseting respectively.
0326                                ;
0327                                ;
0328                                ;	
0329                                ;		Current # of tests/flashes and their meaning:
0330                                ;
0331                                ;		(The short double flash at start does NOT count as a flash.)
0332                                ;
0333                                ;		Note:  A flash indicates that a test passed, prior to a flash,
0334                                ;		you are running the testing associated with that flash.
0335                                ;		Thus seeing two short flashes at the start and not the "first"
0336                                ;		flash would indicate you are failing the U7 data test.
0337                                ;
0338                                ;
0339                                ;		All tests below will attempt to loop on an error; assuming
0340                                ;		the error_action byte is set to loop_val (00).
0341                                ;			
0342                                ;		0.  Two short flashes of LED indicate program start. **
0343                                ;		    Whether it be from power up or from the test finishing
0344                                ;		    a pass and simply looping back to the start.
0345                                ;
0346                                ;		    ** Note:  Will be preceeded by short flashes indicating
0347                                ;		    the Revision Number of the program if switch 33 is pushed.
0348                                ;			
0349                                ;		If the program successfully started you will see two short
0350                                ;		flashes prior to the start of the first test.
0351                                ;		Note:  In counting the number of flashes do not count these
0352                                ;		two short flashes.  They simply mean the program is active
0353                                ;		and also indicate the start of the program.  Every time the
0354                                ;		program loops through 10 flashes successfully, you should
0355                                ;		again see these two short flashes. 
0356                                ;
0357                                ;		The test program will run forever and these two short
0358                                ;		flashes can be used to identify the start of another pass
0359                                ;		as well as indicate that the program has not gone haywire
0360                                ;		due to some problem; watch for them!
0361                                ;
0362                                ;		The only other time short flashes are used currently is:
0363                                ;
0364                                ;		1.  If switch 33 is pushed as described above.
0365                                ;		
0366                                ;		2.  For an error report (based on the "error_action byte;
0367                                ;		described previously) 
0368                                ;
0369                                ;		3.  During certain tests as described in the test descriptions
0370                                ;		below, all indicate an error and all will be 10 flashes.
0371                                ;
0372                                ;
0373                                ;		If the LED did not blink twice you should suspect that the
0374                                ;		program is not running.   
0375                                ;
0376                                ;		If it did blink two short times then you should now
0377                                ;		be running test 1.  If the test passes succesfully; 
0378                                ;		you should see the first real flash.
0379                                ;
0380                                ;
0381                                ;		Flash 1.  U7 data test passed:
0382                                ;			All data patterns checked at all locations
0383                                ;			in the 6810.
0384                                ;
0385                                ;			Note:  As this is the first test run, any failure
0386                                ;			can get hit here.  An open address line to a ram,
0387                                ;			may cause this test to fail if it is floating
0388                                ;			at a border line state.  Indications of this would
0389                                ;			be failing data/address changing during different
0390                                ;			passes through this test.  If the address line is
0391                                ;			floating steadily high or steadily low then this
0392                                ;			problem will normally be caught in the address tests.
0393                                ;
0394                                ;			Probable cause of failure:  almost anything at this
0395                                ;			point.  Check data lines, U7 enables, and R/W line 
0396                                ;			at U7 and finally check address lines.  Enables on U7
0397                                ;			should be active as well as R/W (error_action = loop).
0398                                ;			Data and address can most easily be checked via a 
0399                                ;			logic analyzer or may be ohmed out to the 6800 
0400                                ;			processor.
0401                                ;			
0402                                ;			Now running test 2.
0403                                ;
0404                                ;		Flash 2. The first of two U7 address uniqueness tests passed.
0405                                ;			All addresses checked in u7 for uniqness to
0406                                ;			u7_min address and u7_min+1 address.
0407                                ;
0408                                ;
0409                                ;			Note:  This is a weird way to do it but it is done
0410                                ;			before address equal data test since due to the lack
0411                                ;			of any stack space (we cannot trust U7 yet) and due
0412                                ;			to lack of an extra register in the 6800 we cannot
0413                                ;			get into an error loop from address equal data
0414                                ;			until we have two "trusted" bytes in the 6810.
0415                                ;			This will catch almost any address uniqness problem
0416                                ;			at the 6810, except possibly a bad 6810.  That should
0417                                ;			be caught by the address equal data test that follows.
0418                                ;
0419                                ;			Probable cause of failure is a faulty address line.
0420                                ;
0421                                ;			Now running test 3.
0422                                ;
0423                                ;		3.  Flash 3.  Address equal data test of U7.  passed.
0424                                ;			This is the second address uniqueness test of U7.
0425                                ;
0426                                ;			A loop is entered on failure.
0427                                ;			Now writing zeroes to all of 5101 verify 6810 is
0428                                ;			not touched.  If test fails check 6810 enable circuit
0429                                ;			followed by checking for short between 5101 enable
0430                                ;			signals and 6810 enable circuit.  Also verify
0431                                ;			R/W line is not shorted to 6810 enable circuitry.
0432                                ;			This test also looks for an error if it cannot find
0433                                ;			it, it will short flash the LED 10 times and re-start.
0434                                ;
0435                                ;			Probable cause of failure:  
0436                                ;			Open or shorted address line to U7.
0437                                ;
0438                                ;			Now running test 4.
0439                                ;
0440                                ;		4.  Flash 4.  U7 uniq from U8 test 1 of 2 passed.
0441                                ;
0442                                ;			Write 00 to 5101 check 6810 untouched.
0443                                ;
0444                                ;			Probable cause of failure:
0445                                ;			Check 6810 enable circuit followed by checking
0446                                ;			for short between 5101 enable signals and 6810
0447                                ;			enable circuit.  Also verify
0448                                ;			R/W line is not shorted to 6810 enable circuitry.
0449                                ;			Possible though unlikely, data line shorted.
0450                                ;
0451                                ;			Now running test 5.
0452                                ;
0453                                ;		5.  Flash 5.  U7 uniq from U8 test 2 of 2 passed.
0454                                ;
0455                                ;			Write FF to 5101 check 6810 untouched.
0456                                ;
0457                                ;			Probable cause of failure:
0458                                ;			open or shorted chip selects feeding U7 an or U8.
0459                                ;			Check U7 an U8 enable circuits followed by checking
0460                                ;			for short between the U7 and U8 chip selects.
0461                                ;			Also verify R/W line is not shorted to 6810 enable 
0462                                ;			circuitry.  Possible though unlikely shorted data line.
0463                                ;
0464                                ;			Now running test 6.
0465                                ;
0466                                ;		6.  Flash 6.  U8 data test passed.
0467                                ;
0468                                ;			Check all data patterns to U8 CMOS RAM.
0469                                ;			on the error.  If it is unsuccessfull; the error
0470                                ;			routine will short flash the LED 10 times and the
0471                                ;			program will attempt to restart itself from scratch.
0472                                ;
0473                                ;			Probable cause of failure:
0474                                ;			Open data line, open or shorted chip select or 
0475                                ;			open or shorted R/W line to U8 CMOS RAM.
0476                                ;
0477                                ;			Now running test 7.
0478                                ;
0479                                ;		7.  Flash 7.  U8 address uniqueness test passed.
0480                                ;
0481                                ;			All addresses checked on 5101.  Test passed.
0482                                ;
0483                                ;			Note:  The address uniqueness section of this test
0484                                ;			will attempt to find the conflicting address to loop
0485                                ;			on the error.  If it is unsuccessfull; the error
0486                                ;			routine will short flash the LED 10 times and the
0487                                ;			program will attempt to restart itself from scratch.
0488                                ;
0489                                ;			Probable cause of error:  open address line,
0490                                ;			open or shorted chip select to U8.
0491                                ;
0492                                ;			Now running test 8.
0493                                ;
0494                                ;		8.  Flash 8.  U11 PIA DDR test passed.
0495                                ;			Check data direction registers A,B in U11 PIA.
0496                                ;			Simple data patterns of $55 and $AA are used.  Verify
0497                                ;			that the two registers can be uniquely addressed
0498                                ;			within the PIA.
0499                                ;
0500                                ;			Probable cause of failure:
0501                                ;			Open address, enable, Data, R/W or reset line to PIA.
0502                                ;
0503                                ;			Now running test 9.
0504                                ;
0505                                ;		9.  Flash 9.  U10 PIA DDR test passed.
0506                                ;			Check data direction registers A,B in U10 PIA.
0507                                ;			Simple data patterns of $55 and $AA are used.  Verify
0508                                ;			that the two registers can be uniquely addressed
0509                                ;			within the PIA.
0510                                ;
0511                                ;			Probable cause of failure:
0512                                ;			Open address, enable, Data, R/W or reset line to PIA.
0513                                ;
0514                                ;			Now running test 10.
0515                                ;
0516                                ;		10. Flash 10.  Check that we can address U11 and U10 uniquely.
0517                                ;			We write $55 to the ddra in U11 and $AA to ddra in
0518                                ;			U10.  We then read back U11 and make sure it still
0519                                ;			has $55.  Loop entered on failure.
0520                                ;
0521                                ;			Probable cause of failure:  Pin 22 of PIA Open or:
0522                                ;			Open address, enable, Data, R/W or reset line to 
0523                                ;			either U10 or U11.
0524                                ;
0525                                ;			Now runing test 11.
0526                                ;			
0527                                ;		11.  Flash 11.  U13 data test passed.  MPU 200 ONLY.
0528                                ;			Note: location test_mpu_200 must be set to 01.
0529                                ;			to run this test.
0530                                ;
0531                                ;			Note: location test_mpu_200 must be set to 01 to run.
0532                                ;			If set to 00 this test is not run; however a short
0533                                ;			flash will occur as flash 11 indicating that it was
0534                                ;			not run.
0535                                ;
0536                                ;			Check all data patterns to U13 CMOS RAM.
0537                                ;
0538                                ;			Probable cause of failure:
0539                                ;			Open data line, open or shorted chip select or 
0540                                ;			open or shorted R/W line to U13 CMOS RAM.
0541                                ;
0542                                ;			Now running test 12.
0543                                ;
0544                                ;		12.  Flash 12.  U13 addr uniqueness test passed. MPU 200 ONLY.
0545                                ;
0546                                ;			All addresses checked on U13 CMOS RAM.
0547                                ;
0548                                ;			Note: location test_mpu_200 must be set to 01 to run.
0549                                ;			If set to 00 this test is not run; however a short
0550                                ;			flash will occur as flash 12 indicating that it was
0551                                ;			not run.
0552                                ;
0553                                ;
0554                                ;			Note:  The address uniqueness section of this test
0555                                ;			will attempt to find the conflicting address to loop
0556                                ;			on the error.  If it is unsuccessfull; the error
0557                                ;			routine will short flash the LED 10 times and the
0558                                ;			program will attempt to restart itself from scratch.
0559                                ;
0560                                ;			Probable cause of error:  open address line,
0561                                ;			open or shorted chip select to U8.
0562                                ;
0563                                ;			The test at this time has finished and will loop back
0564                                ;			to the start and indicate this by two short flashes.
0565                                ;
0566                                ;           10 Quick Flashes on the tests that indicate this function
0567                                ;			occur because an error loop aka scope loop was entered
0568                                ;           and the error loop determined the failure stopped occuring.
0569                                ;           This is typical of intermittent signals or signals on "the edge".
0570                                ;			Maybe you pressed on the board or probed an iff signal.
0571                                ;
0572                                ;
0573                                ;		Note:  All of the above "Probable cause" suggestions assume
0574                                ;			that you have  "Known Good" Parts in the sockets.
0575                                ;			If you do not; you would be well advised to change
0576                                ;			the part in most cases before looking for opens or
0577                                ;			shorts in the board. 
0578                                ;			Also in the case of sockets U6, U7, U8, and U11 in
0579                                ;			particular; verify that the socket(s) are not 
0580                                ;			corroded from the NiCad battery leaking.  If a 
0581                                ;			socket looks bad; replace it with a good one.
0582                                ;
0583                                ;
0584                                ;		Program re-start may be accomplished by activating the
0585                                ;		switch 33 pushbutton at any time.  This will cause
0586                                ;		a Non-Maskable Interrupt whose vector points back to
0587                                ;		"show_revision".  Show_revision will cause the LED
0588                                ;		To blink n times rapidly to correspond with the revision
0589                                ;		number of the program.  This will be followed by a wait
0590                                ;		of 2-3 seconds.  After which the program will restart.
0591                                ;		Program restart can be recognized by its two short flashes.
0592                                ;		
0593                                ;
0594                                ;
0595                                ;Power on or a "forced" reset (you ground and release reset on 6800)
0596                                ;Sanity Check: (2 short flashes).
0597                                ;flash #1.  U7 data bits are unique.
0598                                ;flash #2.  U7 addresses unique part 1.
0599                                ;flash #3.  U7 addr uniq part 2. U7 is good.
0600                                ;flash #4.  Writing U8 did not affect U7.
0601                                ;flash #5.  U7/U8 uniq. Stack is now useable.
0602                                ;flash #6.  U8 data bits are unique.
0603                                ;flash #7.  U8 addresses are unique.
0604                                ;flash #8.  ddra/b reg in u11 basically checked.
0605                                ;flash #9.  ddra/b reg in u10 basically checked.
0606                                ;flash #10. U10 and U11 are unique.
0607                                ;flash #11. MPU 200 only. U13 data bits unique. (short flash if not run)
0608                                ;flash #12. MPU 200 only. U13 addresses unique. (short flash if not run)
0609                                ;A short display test now occurs that does NOT use interrupts!
0610                                ;Start over from beginning at sanity check flashes. 
0611                                
0612 0001                           yes		equ	$1	;
0613 0000                           no		equ	$0	;
0614 5800                           u6_strt		equ	$5800	;start addr = 0 for bally level 17 mpu for U6.
0615 5fff                           u6_end		equ	$5FFF	;end addr = ffff for bally level 17 mpu for U6.
0616 5000                           u2_strt		equ	$5000	;start addr = 0 for bally level 17 mpu for U2.
0617 57ff                           u2_end		equ	$57FF	;end addr = ffff for bally level 17 mpu for U2.
0618 0000                           u7_min		equ	$0	;low addr for 6810.
0619 007f                           u7_max		equ	$7F	;high addr for 6810.
0620 0200                           u8_min		equ	$200	;low addr for 5101.
0621 02ff                           u8_max		equ	$2FF	;high addr for 5101.
0622 0093                           u11_mask	equ	%0000000010010011	;mask for u11 PIA. 93x
0623 0090                           u11_sel		equ	%0000000010010000	;addr enable for u11 PIA. 90x
0624 008b                           u10_mask	equ	%0000000010001011	;mask for u10 PIA.8Bx
0625 0088                           u10_sel		equ	%0000000010001000	;addr enable for u10 PIA. 88x
0626 0200                           u13_min		equ	$200	;low addr for 5101. U13 is STERN MPU 200
0627 02ff                           u13_max		equ	$2FF	;high addr for 5101. U13 is STERN MPU 200
0628 0038                           led_on		equ	$38  ;should turn on LED.
0629 0030                           led_off		equ	$30  ;should turn off LED.
0630 0001                           cra_sel		equ	$01  ;control register A.
0631 0003                           crb_sel		equ	$03  ;control register B.
0632 0000                           pia_reg_a_sel	equ	$00  ;Register A slections in PIA.  For DDRA and PRA
0633 0002                           pia_reg_b_sel	equ	$02  ;Register B slections in PIA.  For DDRB and PRB
0634 0000                           pia_ddr_reg	equ	%00000000 ; access output reg access.
0635 0004                           pia_out_reg	equ	%00000100 ; access data direction reg access.
0636 000f                           player_latches	equ	$0F	;players 1-4.  status/match not included.
0637 00ff                           digit_bcd_bits	equ	$FF	;PA0-7. BCD bits for all players.
0638 fff8                           irq_vector	equ	$FFF8	; FFF8,FFF9  IRQ interrupt.
0639 fffa                           swi_vector	equ	$FFFA	; FFFA,FFFB SWI	interrupt.
0640 fffc                           nmi_vector	equ	$FFFC	; FFFC,FFFD NMI CLEAR SWITCH (SW 33).
0641 fffe                           reset_vector	equ	$FFFE	; FFFE,FFFF RESET vector.
0642 0000                           loop_val	equ	$0	; see error_action settings, or flash_error.
0643 0001                           restart_val	equ	$1	; see error_action settings, or flash_error.
0644 0002                           halt_val	equ	$2	; see error_action settings, or flash_error.
0645 001f                           blank_time	equ	$1F	; toggling blanking for RC network R30/C18.
0646 0004                           revision_val	equ	4	; Revision.
0647 004f                           stack_strt	equ	$4F	; stack will be from 4f to 0, with the
0648                                ;				; top $30 locations reserved for variables.
0649                                ;
0650                                ; THE FOLLOWING LOCATIONS ARE RESERVED IN THE 6810 AS PROGRAM VARIABLES
0651                                ; THEY MAY NOT BE ACCESSED UNTIL AFTER WE HAVE DECIDED THE 6810 IS OK.
0652                                ;
0653                                ; Variable region exists from addr $50 to addr $7f.
0654 0050                           var_1		equ	$50	; two bytes for first variable in call
0655 0052                           var_2		equ	$52	; two bytes for second variable in call
0656 0054                           var_3		equ	$54	; two bytes for third variable in call
0657 0056                           x_place		equ	$56	; two bytes for allowing push of x.
0658 0058                           temp		equ	$58	; two bytes used for local temp storage.
0659 005a                           disp_bcd	equ	$5A	; two bytes for display info.
0660 005c                           blank_cnt	equ	$5C	; current blanking status.
0661 005e                           disp_cnt	equ	$5E	; for looping.
0662                                
0663                                ; define  some important space for address uniqness testing of 6810 RAM.
0664 0000                           temp_0		equ	u7_min	; two bytes of space at 00 and 01 in RAM.
0665                                
0666                                
0667                                
0668 5800                           	org 	u6_strt		;start of program.
0669                                
0670                                ;	Note:  "error_action" is intended to always be at u6_strt
0671                                ;	for convenience and is the first byte of u6.  The next byte will
0672                                ;	be the test_mpu_200 variable.  If set to #no (zero) we do not run
0673                                ;	U13 tests.  If set to #yes (one) we run u13 tests.  Default of the
0674                                ;	code unless modified shall be to not run u13 tests.  Thus we will
0675                                ;	run on all Bally AS-2518-xx and both Stern MPU 100/200 less the 
0676                                ;	U13 test.  Note to allow conitinued additions to this test, if the
0677                                ;	MPU 200 tests are disabled the test will still flash as if it passed;
0678                                ;	however the flash will be a short flash when disabled instead of the
0679                                ;	normal longer flash.  This will allow us to always associate a given
0680                                ;	flash with a specific test.  The next byte contains the revision 
0681                                ;	number.  Then a few bytes which contain a copyright notice.
0682                                
0683                                
0684                                error_action:
0685 5800 00                        	fcb	#loop_val	;set to 00 will cause 5 flashes on error and
0686                                				;restart.  set to non-zero will allow loop
0687                                 				;on error.  See description of error_action.
0688                                
0689                                test_mpu_200:
0690 5801 01                        	fcb	#yes	;This byte decides if we run mpu 200 tests.
0691                                				;If no; then we do not run U13 specific tests.
0692                                revision:
0693 5802 04                        	fcb	#revision_val	;Put rev in rom also in case we want to know.
0694                                
0695                                
0696                                ;		Now put in my copyright notice.
0697                                copyright:
0698 5803 20 57 52 49 54 54         	fcc	" WRITTEN 1992 BY DALLAS E. OVERTURF "
          45 4e 20 31 39 39
          32 20 42 59 20 44
          41 4c 4c 41 53 20
          45 2e 20 4f 56 45
          52 54 55 52 46 20
0699                                
0700 5827 20 4d 59 20 42 41         	fcc	" MY BALLY/STERN TEST PROM "
          4c 4c 59 2f 53 54
          45 52 4e 20 54 45
          53 54 20 50 52 4f
          4d 20
0701                                
0702                                ;	A Non Maskable Interrupt (switch 33) will restart at show_revision.
0703                                
0704                                show_revision:
0705                                
0706 5841 ce 75 30                  	ldx	#30000		;wait a moment prior to flashing rev.
0707                                wait_rev:
0708 5844 09                        	dex			;dec count.
0709 5845 26 fd                     	bne	wait_rev	;keep waiting.
0710                                
0711 5847 c6 04                     	ldab	#revision_val	;b now has revision.
0712 5849 ce 58 4f                  	ldx	#revision_ret	;x has return address.
0713 584c 7e 5d 4b                  	jmp	sflash_sp_svc	;go flash the rev.
0714                                revision_ret:
0715 584f 86 02                     	ldaa	#2		;two times will be a very long wait.
0716                                revision_lp:
0717 5851 ce 75 30                  	ldx	#30000		;long wait.
0718                                rev_x_lp:
0719 5854 09                        	dex			;dec wait count
0720 5855 26 fd                     	bne	rev_x_lp	;
0721 5857 4a                        	deca			;dec loop count.
0722 5858 26 f7                     	bne	#revision_lp	;branch if not done or fall through to start.
0723                                
0724                                start:
0725                                	;1st write and or read some data and address patterns to see
0726                                	;that the bus is ok on the analyzer.
0727                                
0728 585a ce 00 00                  	ldx	#$0000		;An address to write to write to. = 0000.
0729 585d 86 00                     	ldaa	#$00		;some data to write= 00.
0730 585f a7 00                     	staa	0,x		;unchecked data only to look at bus.
0731 5861 43                        	coma			;some data to write= FF.
0732 5862 a7 00                     	staa	0,x		;unchecked data only to look at bus.
0733 5864 86 55                     	ldaa	#$55		;some data to write= 55.
0734 5866 a7 00                     	staa	0,x		;unchecked data only to look at bus.
0735 5868 43                        	coma			;some data to write= AA.
0736 5869 a7 00                     	staa	0,x		;unchecked data only to look at bus.
0737 586b ce 00 00                  	ldx	#$0000		;address pattern to read from.
0738 586e a6 00                     	ldaa	0,x		;read address, don't care about data.
0739 5870 ce ff ff                  	ldx	#$FFFF		;address pattern to read from.
0740 5873 a6 00                     	ldaa	0,x		;read address, don't care about data.
0741 5875 ce 55 55                  	ldx 	#$5555		;address pattern to read from.
0742 5878 a6 00                     	ldaa	0,x		;read address, don't care about data.
0743 587a ce aa aa                  	ldx 	#$AAAA		;address pattern to read from.
0744 587d a6 00                     	ldaa	0,x		;read address, don't care about data.
0745                                
0746                                	;Now turn off LED so we know we are running code.
0747                                
0748 587f ce 00 90                  	ldx	#u11_sel	;x has u11 enable base addr.
0749 5882 86 30                     	ldaa	#led_off	;aa set to enable CA2 as output, LED off.
0750 5884 a7 01                     	staa	cra_sel,x	;LED should turn off now.
0751 5886 a7 01                     	staa	cra_sel,x	;again in case b5 in cra must be set first.
0752                                
0753 5888 ce 7f bc                  	ldx	#32700		;hold off so we can see the LED is off.
0754                                
0755                                start_delay:
0756 588b 09                        	dex
0757 588c 26 fd                     	bne	#start_delay
0758                                
0759                                pass:
0760                                
0761 588e ce 58 96                  	ldx	#pass_return	;x has return address.
0762 5891 c6 02                     	ldab	#2		;flash count.  Double quick blink so we know
0763 5893 7e 5d 4b                  	jmp	sflash_sp_svc	;we are in code and where start is on a pass.
0764                                pass_return:
0765                                
0766 5896 ce 00 00                  	ldx	#u7_min		; Start addr of 6810.
0767 5899 86 00                     	ldaa	#$0
0768                                u7_data:
0769                                
0770                                ;	u7_data attempts to check that each address can hold any data
0771                                ;	pattern in the 6810.  Address uniqueness has not been qualified yet.
0772                                
0773                                
0774 589b ce 00 00                  	ldx	#u7_min
0775                                
0776                                u7_d_nextadr:
0777 589e 86 00                     	ldaa	#$0		;aa will be expected data
0778 58a0 c6 ff                     	ldab	#$ff		;ab will be actual. Init to anything else; we
0779                                				;start at zero so this must get zero on a read
0780 58a2 20 0b                     	bra	#u7_d_datloop	;
0781                                
0782                                u7_d_errloop:
0783 58a4 7f ff fe                  	clr	#reset_vector	;failure check in.  Write to read only space.
0784 58a7 f6 58 00                  	ldab	error_action	;sets CCs.
0785 58aa 27 03                     	beq	#u7_d_datloop	;no flash error.
0786 58ac 7e 5c 90                  	jmp	flash_error	;
0787                                
0788                                u7_d_datloop:
0789 58af a7 00                     	staa	0,x		;write to the 6810.
0790 58b1 e6 00                     	ldab	0,x		;read from the 6810.
0791 58b3 11                        	cba			;compare a and b accumulators.
0792 58b4 26 ee                     	bne	#u7_d_errloop	;loop on the error till it clears.
0793 58b6 4c                        	inca			;increment a.
0794 58b7 26 f6                     	bne	#u7_d_datloop	;data is 00-FF on FF we roll to 00 indicating
0795                                				;we have checked all data on current address.
0796 58b9 08                        	inx			;inc x to next addr.
0797 58ba 8c 00 80                  	cpx	#u7_max+1	;if past max addr then we are done.
0798 58bd 26 df                     	bne	#u7_d_nextadr	;not done; do next address.
0799 58bf c6 01                     	ldab	#$1		;flash #1.  U7 data bits are unique.
0800                                
0801 58c1 ce 58 c7                  	ldx	#u7_d_return	;x now has return address.
0802 58c4 7e 5d 2a                  	jmp	#flash_sp_svc	;go flash, then fall through to next test.
0803                                u7_d_return:			;This label must be here to return.
0804                                
0805                                ;===========================================================================
0806                                
0807                                ;	This test will verify that locations zero and one in u7 are unique
0808                                ;	from all other locations in u7.  Thus we will have identified two
0809                                ;	bytes of memory that can be used as stack space or temp storage in
0810                                ;	the full u7 address uniqueness test which is an address equal data
0811                                ;	test.
0812                                ;	By using all data patterns we verify that there is no data line(s)
0813                                ;	shorted to an address line which would later confuse things for the
0814                                ;	four addresses in question.  Probably most address uniqueness problems
0815                                ;	will be caught here; however we will do adress equal data test later
0816                                ;	to be very safe.  Note:  Between this test and the u7_data_test; we
0817                                ;	really should not see data shorted to an address.
0818                                
0819                                
0820 58c7 4f                        	clra			;aa holds pattern to write.  patterns. 00-FF.
0821                                u7_au0_part:
0822 58c8 ce 00 02                  	ldx	#u7_min+2
0823 58cb 20 0b                     	bra	#u7_au0_loop
0824                                
0825                                u7_au0_err:
0826 58cd 7f ff fe                  	clr	#reset_vector	;failure check in.  Write to read only space.
0827 58d0 f6 58 00                  	ldab	error_action	;sets CCs.
0828 58d3 27 03                     	beq	#u7_au0_loop	;no flash error.
0829 58d5 7e 5c 90                  	jmp	flash_error	;
0830                                
0831                                u7_au0_loop:
0832 58d8 5f                        	clrb			;to clear temp locs. We need some temp space.
0833 58d9 d7 00                     	stab	u7_min		;temp loc 0.  Part of temp_0.  Used for
0834 58db d7 01                     	stab	u7_min+1	;temp loc 1.  Part of temp_0.  Future storage.
0835 58dd a7 00                     	staa	0,x		;write test data to all other u7 locations.
0836 58df d6 00                     	ldab	u7_min		;temp loc 0.  This will set CCs.
0837 58e1 26 ea                     	bne	u7_au0_err	;loop on error.
0838 58e3 d6 01                     	ldab	u7_min+1	;temp loc 1.  This will set CCs.
0839 58e5 26 e6                     	bne	u7_au0_err	;loop on error.
0840 58e7 4c                        	inca			;inc aa to next data pattern.
0841 58e8 27 02                     	beq	#u7_au0_ckdone
0842 58ea 20 ec                     	bra	#u7_au0_loop	;Do next data pattern.
0843                                
0844                                u7_au0_ckdone:
0845 58ec 8c 00 7f                  	cpx	#u7_max		; check if really done.
0846 58ef 27 04                     	beq	u7_au0_done	; yes we are really done.
0847 58f1 08                        	inx	
0848 58f2 4f                        	clra			; Start pattern at 00 again.
0849 58f3 20 e3                     	bra	#u7_au0_loop	;not done continue looping.
0850                                
0851                                u7_au0_done:
0852 58f5 c6 01                     	ldab	#$1		;flash #2.  U7 addresses unique part 1.
0853                                				;we don't call flash_svc yet till we check
0854                                				;that all addresses are unique which occurs
0855                                				;next.
0856 58f7 ce 58 fd                  	ldx	#u7_au0_return	;x has return address.
0857 58fa 7e 5d 2a                  	jmp	#flash_sp_svc	;go flash.
0858                                u7_au0_return:			;This label must be here to return.
0859                                
0860 58fd ce 4e 20                  	ldx	#20000		; since we passed hold off a bit so we can 
0861                                				; see the next flash occur for next test.
0862                                u7_au0_delay:
0863 5900 09                        	dex
0864 5901 26 fd                     	bne	#u7_au0_delay
0865                                
0866                                
0867                                ;===========================================================================
0868                                
0869                                ;	U7 Address Equal Data test.  Final adress uniqness test of u7.
0870                                ;	It is not expected that this test will normally fail except
0871                                ;	in the case of a bad 6810 or an intermittent board.  However
0872                                ;	this test can loop on error in case strange circumstances are
0873                                ;	encountered, and we fail due to something other than a bad 6810.
0874                                
0875                                u7_aed_test:
0876 5903 86 7f                     	ldaa	#u7_max
0877 5905 ce 00 7f                  	ldx	#u7_max
0878                                u7_aed_dec:
0879 5908 a7 00                     	staa	0,x		;write pattern to address.
0880 590a 4a                        	deca			;next pattern.
0881 590b 09                        	dex			;next address.
0882 590c 8c 00 01                  	cpx	#temp_0+1	;leave our two byte space alone!
0883 590f 26 f7                     	bne	u7_aed_dec	;done if equal else continue.
0884                                
0885                                ;	U7 should now be completely address equal data less first two locs.
0886                                
0887 5911 86 02                     	ldaa	#temp_0+2	;1st address in range we write to.
0888 5913 ce 00 02                  	ldx	#temp_0+2	;1st address in range we write to.
0889                                u7_aed_inc:
0890 5916 e6 00                     	ldab	0,x		;read 1st address.
0891 5918 11                        	cba			;compare expected in a, to actual in b.
0892 5919 26 0a                     	bne	u7_aed_find_loc	;Try to find the conflict to loop on error.
0893 591b 4c                        	inca			;next pattern.
0894 591c 08                        	inx			;next address.
0895 591d 8c 00 80                  	cpx	#u7_max+1	;done when we reach u7_max.
0896 5920 26 f4                     	bne	u7_aed_inc	;continue if not done or fall through and pass.
0897                                
0898                                ;	U7 should now be completely address equal data, less first two locs.
0899                                
0900 5922 7e 59 72                  	jmp	u7_aed_passed	;no error, we passed.
0901                                
0902                                ;	On entry x is the location in error found as follows:
0903                                ;	The routine prior to this is expected to write data from max to
0904                                ;	min addresses and then do the check from min to max so that 
0905                                ;	temp_0 - 1 will be the highest address needed to find the error.
0906                                ;	If this policy is not adhered to then this routine's ability to
0907                                ;	localize the error will be compromised.
0908                                ;	Note:  Temp_0 occupies the first two bytes of u7 thus it MUST BE
0909                                ;	gauranteed to to be uniqe to u7 prior to using this routine.
0910                                
0911                                u7_aed_find_loc:
0912                                
0913 5925 4f                        	clra			;
0914 5926 a7 00                     	staa	0,x		;clear error location.
0915 5928 df 00                     	stx	temp_0		;store away error loc for now.
0916 592a 86 aa                     	ldaa	#$AA		;Compliment of first pattern.  We do two.
0917                                
0918                                u7_aed_next_dat:
0919 592c 43                        	coma			;compliment so 1st patter will be 55.
0920 592d ce 00 02                  	ldx	#temp_0+2	;initial loc we write to
0921                                
0922                                u7_aed_next_adr:
0923 5930 a7 00                     	staa	0,x		;write to location then check error loc.
0924 5932 35                        	txs			;store x in sp for now.
0925 5933 de 00                     	ldx	temp_0		;get error loc into x.
0926 5935 e6 00                     	ldab	0,x		;check it.  This will set CCs.
0927 5937 30                        	tsx			;restore x from sp. This will not change CCs.
0928 5938 26 16                     	bne	u7_aed_found	;we will now go and try to loop on the error.
0929 593a 08                        	inx			;next address.
0930 593b 9c 00                     	cpx	temp_0		;If >= temp_0, we've not yet found the problem.
0931 593d 2d f1                     	blt	u7_aed_next_adr	;continue to next addr.
0932 593f 81 aa                     	cmpa	#$AA		;if AA then we are done.
0933 5941 26 e9                     	bne	u7_aed_next_dat	;if only 55 then we need to do AA still.
0934 5943 20 1c                     	bra	u7_aed_unot	;If here we could not isolate the error.
0935                                				;in such a case let them know.
0936                                	
0937                                ;	u7_f_loop expects the bad address in temp_0 and conflict addr in x.
0938                                ;	data written to find error will be in aa still.  aa has the data.
0939                                ;	Note:  we enter at found:  we loop to found_lp.  This allows us to
0940                                ;	see the problem occur immediately before error check in.
0941                                u7_aed_foundlp:
0942 5945 7f ff fe                  	clr	#reset_vector	;failure check in.  Write to read only space.
0943 5948 f6 58 00                  	ldab	error_action	;sets CCs.
0944 594b 27 03                     	beq	#u7_aed_found	;no flash error.
0945 594d 7e 5c 90                  	jmp	flash_error	;Set to flash on error.
0946                                
0947                                u7_aed_found:			;This is initial entry point.
0948 5950 35                        	txs			;hold x in sp.	
0949 5951 5f                        	clrb
0950 5952 de 00                     	ldx	temp_0		;x has error loc.
0951 5954 e7 00                     	stab	0,x		;clear error loc.
0952 5956 30                        	tsx			;restore x.
0953 5957 a7 00                     	staa	0,x		;write to x, we expect to overwrite error loc.
0954 5959 35                        	txs			;hold x in sp.
0955 595a de 00                     	ldx	temp_0		;x has error loc.
0956 595c e6 00                     	ldab	0,x		;this will set CCs.
0957 595e 30                        	tsx			;restore x.  This does not affect CCs.
0958 595f 26 e4                     	bne	u7_aed_foundlp	;if not equal we are seeing the error.
0959                                
0960                                u7_aed_unot:
0961                                
0962 5961 c6 0a                     	ldab	#10		;setup to flash 10 times so we know that
0963                                				;we could not locate the error.
0964                                				;We will restart.
0965 5963 fe 59 69                  	ldx	u7_aedf_return	;x now has return address.
0966 5966 7e 5d 4b                  	jmp	sflash_sp_svc	;Let them know we cannot isolate error.
0967                                u7_aedf_return:
0968                                
0969 5969 ce 4e 20                  	ldx	#20000		;delay count.
0970                                
0971                                u7_aed_delay:
0972 596c 09                        	dex
0973 596d 26 fd                     	bne	#u7_aed_delay
0974 596f 7e 58 5a                  	jmp	start		;There was an error so restart from scratch.
0975                                
0976                                
0977                                ;	The next test expects that u7 has addr equal data pattern in it.
0978                                ;	make it so.
0979                                
0980                                u7_aed_passed:
0981 5972 86 00                     	ldaa	#u7_min
0982 5974 ce 00 00                  	ldx	#u7_min
0983                                set_loop:
0984 5977 a7 00                     	staa	0,x
0985 5979 08                        	inx			;next address.
0986 597a 4c                        	inca			;next pattern.
0987 597b 8c 00 80                  	cpx	#u7_max+1	;if equal then we are done.
0988 597e 26 f7                     	bne	#set_loop	;go write pattern.
0989                                
0990                                ;	U7 should now be completely address equal data.
0991                                
0992 5980 c6 01                     	ldab	#$1		;flash #3.  U7 addr uniq part 2. U7 is good.
0993                                				;we don't call flash svc yet till we check
0994                                				;the 5101 addressing; as we want to check 
0995                                				;that the 5101 addressing does not affect
0996                                				;the 6810 at U7.
0997 5982 ce 59 88                  	ldx	#u7_aed_return	;x now has return address.
0998 5985 7e 5d 2a                  	jmp	#flash_sp_svc	;go flash.
0999                                u7_aed_return:
1000                                
1001                                ;	No delay loop is needed here.  We can see the LED just fine.
1002                                
1003                                ;===========================================================================
1004                                
1005                                ;	Verify that writing to u8 does not write to u7.
1006                                
1007                                u7u8_uniq:
1008 5988 ce 00 00                  	ldx	#u7_min		; start of u7.
1009 598b 86 00                     	ldaa	#$0		; zero to clear.
1010                                
1011                                u7u8_clr:			; setup u7 data to known 00 is simplest.
1012 598d a7 00                     	staa	0,x		; clear u7.
1013 598f 08                        	inx
1014 5990 8c 00 80                  	cpx	#u7_max+1	; check if done.
1015 5993 26 f8                     	bne	#u7u8_clr	; continue or fall through.
1016 5995 8e 02 ff                  	lds	#u8_max		; high addr of device we are checking against.
1017                                				; sp grows from high to low.
1018                                u7u8_lp:
1019 5998 86 ff                     	ldaa	#$FF		; Any pattern besides zero will do here.
1020 599a 36                        	psha			; This will write a byte to u8.
1021 599b 30                        	tsx			; x now has a copy of sp+1. sp is unchanged.
1022 599c 8c 02 00                  	cpx	#u8_min		; because got sp+1 this is a straight cmpare.
1023 599f 27 24                     	beq	#u7u8_pass	; if done then pass.
1024                                
1025                                u7u8_chk:
1026 59a1 ce 00 00                  	ldx	#u7_min		; Setup to check out u7, it should still be 00.
1027                                
1028                                u7u8_chklp:
1029 59a4 e6 00                     	ldab	0,x		; read device location.  This will set CCs.
1030 59a6 26 08                     	bne	#u7u8_err	; if not zero goto error routine.
1031                                
1032                                u7u8_reent:			; if error goes away in errloop then re-enter.
1033 59a8 08                        	inx			; inc x.
1034 59a9 8c 00 80                  	cpx	#u7_max+1	; check if done.
1035 59ac 26 f6                     	bne	#u7u8_chklp	; loop if not done
1036 59ae 20 e8                     	bra	#u7u8_lp	; current did not overwrite, next u8 address.
1037                                
1038                                u7u8_err:
1039 59b0 7f ff fe                  	clr	#reset_vector	;failure check in.  Write to read only space.
1040 59b3 f6 58 00                  	ldab	error_action	;sets CCs.
1041 59b6 27 03                     	beq	#u7u8_errlp	;no flash error.
1042 59b8 7e 5c 90                  	jmp	flash_error	;
1043                                
1044                                u7u8_errlp:
1045 59bb 6f 00                     	clr	0,x		; clear overwritten location.
1046 59bd 34                        	des			; sp will always be fail addr+1. fix it.
1047 59be 36                        	psha			; write to suspect location.
1048 59bf e6 00                     	ldab	0,x		; check for failure.  This sets CCs.
1049 59c1 26 f8                     	bne	#u7u8_errlp	; continue to loop on error if failing.
1050 59c3 20 e3                     	bra	#u7u8_reent	;failure not solid;continue.
1051                                
1052                                u7u8_pass:
1053                                
1054 59c5 c6 01                     	ldab	#$1		;flash #4.  u7 is unique from other devices.
1055                                
1056 59c7 ce 59 cd                  	ldx	#u7u8_return	;x now has return address.
1057 59ca 7e 5d 2a                  	jmp	#flash_sp_svc	;go flash.
1058                                u7u8_return:
1059                                
1060 59cd ce 4e 20                  	ldx	#20000		; since we passed hold off a bit so we can 
1061                                				; see the next flash occur for next test.
1062                                u7u8_delay:
1063 59d0 09                        	dex
1064 59d1 26 fd                     	bne	#u7u8_delay ; Delay to see flash.
1065                                
1066                                ;===========================================================================
1067                                
1068 59d3 8e 00 4f                  	lds	#stack_strt	;initialize the stack for use.
1069                                
1070                                ;	This will be the first time we use the stack.  We shall hope
1071                                ;	that it is in good enough shape to use!
1072                                
1073 59d6 bd 5c c6                  	jsr	one_flash	;flash #5.  U7/U8 uniq. Stack is now useable.
1074                                				;note: U7 has not been proven unique against
1075                                				;U10 at this point.  Will not likely matter.
1076                                
1077 59d9 ce 4e 20                  	ldx	#20000		; since we passed hold off a bit so we can 
1078                                u78_s_delay:
1079 59dc 09                        	dex			; see the next flash occur for next test.
1080 59dd 26 fd                     	bne	#u78_s_delay
1081                                
1082                                ;===========================================================================
1083                                
1084                                	; From this point we will call (jsr) the rest of the tests
1085                                	; for convenience.  The only thing not specifically tested against
1086                                	; the stack is U10.  We have to flash through U11 so it has by nature,
1087                                	; been tested.  U10 has in theory been prove unique to the stack
1088                                	; by virtue of the fact nothing else has interfered with anything
1089                                	; at this point.
1090                                
1091                                ;===========================================================================
1092                                
1093                                do_calls:
1094                                
1095                                ; Test U8 data.
1096                                
1097 59df bd 5a 5d                  	jsr	u8_data_test	;
1098 59e2 bd 5c c6                  	jsr	one_flash	;flash #6.  U8 data bits are unique.
1099                                
1100                                ;===========================================================================
1101                                
1102                                ; Test U8 addressing unique.
1103                                
1104 59e5 bd 5a 89                  	jsr	u8_address_test	;
1105 59e8 bd 5c c6                  	jsr	one_flash	;flash #7.  U8 addresses are unique.
1106                                
1107                                ;===========================================================================
1108                                
1109                                ; Test U11 pia.
1110                                
1111 59eb ce 00 90                  	ldx	#u11_sel	;u11 enable base address.
1112 59ee df 50                     	stx	var_1		;passed argument.
1113 59f0 bd 5b f6                  	jsr	pia_test	;go test u11 pia.
1114 59f3 bd 5c c6                  	jsr	one_flash	;flash #8.  U11 PIA has been checked.
1115                                
1116                                ;===========================================================================
1117                                
1118                                ; Test bally/stern U10 pia.
1119                                
1120 59f6 ce 00 88                  	ldx	#u10_sel	;u10 enable base address.
1121 59f9 df 50                     	stx	var_1		;passed argument.
1122 59fb bd 5b f6                  	jsr	pia_test	;go test u10 pia.
1123 59fe bd 5c c6                  	jsr	one_flash	;flash #9.  U10 PIA has been checked.
1124                                
1125                                ;===========================================================================
1126                                
1127                                ; Test bally/stern u10 and u11 pia's are uniquely addressable.
1128                                
1129 5a01 ce 00 90                  	ldx	#u11_sel	;u11 enable base address.
1130 5a04 df 50                     	stx	var_1		;this will be pia1 in pia_uniq test.
1131 5a06 ce 00 88                  	ldx	#u10_sel	;u10 enable base address.
1132 5a09 df 52                     	stx	var_2		;this will be pia2 in pia_uniq test.
1133 5a0b bd 5c 65                  	jsr	pia_uniq	;test that two pia's are uniquely addressed.
1134 5a0e bd 5c c6                  	jsr	one_flash	;flash #10. U10 and U11 are unique.
1135                                
1136                                ; Check to see if we are supposed to run the U13 test on the Stern MPU200.
1137 5a11 b6 58 01                  	ldaa	test_mpu_200	;get status byte and check if mpu200 enabled.
1138 5a14 81 01                     	cmpa	#yes
1139 5a16 27 1f                     	beq	run_mpu_200	;Do not run MPU 200 tests.
1140                                
1141                                fake_flash_11:	
1142                                
1143 5a18 ce 4e 20                  	ldx	#20000		;delay to differentiate from two flash start
1144                                fake_11a:			;of test marker.
1145 5a1b 09                        	dex			;
1146 5a1c 26 fd                     	bne	fake_11a	;
1147                                
1148 5a1e c6 01                     	ldab	#1		;One flash.
1149 5a20 bd 5c fc                  	jsr	sflash_svc	;flash #11.  Short "fake" flash.
1150                                
1151 5a23 ce 13 88                  	ldx	#5000		;delay to differentiate from two flash start
1152                                fake_11b:			;of test marker.
1153 5a26 09                        	dex			;
1154 5a27 26 fd                     	bne	fake_11b	;
1155                                
1156                                fake_flash_12:
1157                                	
1158 5a29 c6 01                     	ldab	#1		;One flash.
1159 5a2b bd 5c fc                  	jsr	sflash_svc	;flash #12.  Short "fake" flash.
1160                                
1161 5a2e ce 4e 20                  	ldx	#20000		;delay to differentiate from two flash start
1162                                fake_12:			;of test marker.
1163 5a31 09                        	dex			;
1164 5a32 26 fd                     	bne	fake_12		;
1165 5a34 7e 5a 43                  	jmp	past_mpu_200	;skip mpu200 u13 tests.
1166                                
1167                                
1168                                run_mpu_200:		;mpu 200 tests are the U13 tests.
1169                                
1170                                ;===========================================================================
1171                                ; Test U13 data.   STERN MPU 200 only test.
1172                                
1173 5a37 bd 5b 24                  	jsr	u13_data_test	;
1174 5a3a bd 5c c6                  	jsr	one_flash	;flash #11.  U13 data bits unique.
1175                                
1176                                
1177                                ;===========================================================================
1178                                
1179                                ; Test U13 addressing unique.  STERN MPU 200 only test.
1180                                
1181 5a3d bd 5b 50                  	jsr	u13_addr_test
1182 5a40 bd 5c c6                  	jsr	one_flash	;flash #12.  U13 addresses unique.
1183                                
1184                                ;===========================================================================
1185                                
1186                                past_mpu_200:
1187                                
1188                                ;===========================================================================
1189                                
1190 5a43 7e 58 5a                  	jmp	start		;For now we are done; start all over again.
1191 5a46 bd 5a 49                  	jsr	display_test	;Run display test.
1192                                
1193                                ;===========================================================================
1194                                
1195                                
1196                                ; This is a short digits test.  Visual mode only for the fun of it.
1197                                ; We should see digits regardless of the state of the interrupts.
1198                                ; Beware that this test does not use interrpts and is only an indication
1199                                ; of the data path to the displays.
1200                                
1201                                display_test:
1202 5a49 ce 00 02                  	ldx	#2		;run the digits through twice.
1203                                digit_lp:
1204 5a4c c6 00                     	ldab	#00
1205                                digit_lp1:
1206 5a4e bd 5d 6c                  	jsr	display_svc	;pump out digits onto player displays.
1207 5a51 cb 10                     	addb	#$10		;BCD data is on high nibble!  Inc B reg.
1208 5a53 c1 a0                     	cmpb	#$A0		;max digit is nine; done if 10.
1209 5a55 26 f7                     	bne	digit_lp1	;continue if not 10.
1210 5a57 09                        	dex			;check count in x.
1211 5a58 26 f2                     	bne	digit_lp	;
1212                                
1213                                ;===========================================================================
1214                                
1215                                ;	End of testing; restart the test from the beginning.
1216                                
1217 5a5a 7e 58 5a                  	jmp	start		;For now we are done; start all over again.
1218                                
1219                                ;===========================================================================
1220                                
1221                                
1222                                ;	This is the start of all common routines.
1223                                
1224                                
1225                                	; This is the U8 test.  It will verify data and address uniqueness.
1226                                	; because the 5101 CMOS Ram is only 4 bits wide; we take some
1227                                	; great pains to see to it that we find conflicting addresses
1228                                	; in the address uniqueness test for this part so we can loop on
1229                                	; error.  The pain however is well worth the gain
1230                                	; as it may make using a scope easier; and certainly makes things
1231                                	; crystal clear on a logic analyzer.
1232                                
1233                                u8_data_test:
1234                                
1235                                ;	u8_data attempts to check that each cell can hold any
1236                                ;	data pattern in the 5101.  address has not been qualified yet.
1237                                
1238                                
1239 5a5d ce 02 00                  	ldx	#u8_min
1240                                
1241                                u8_d_nextadr:
1242 5a60 86 00                     	ldaa	#$0		;aa will be expected data
1243 5a62 c6 ff                     	ldab	#$ff		;ab will be actual. Init to anything else; we
1244                                				;start at zero so this must get zero on a read
1245 5a64 20 0b                     	bra	u8_d_datloop	
1246                                
1247                                u8_d_errloop:
1248 5a66 7f ff fe                  	clr	#reset_vector	;failure check in.  Write to read only space.
1249 5a69 f6 58 00                  	ldab	error_action	;sets CCs.
1250 5a6c 27 03                     	beq	#u8_d_datloop	;no flash error.
1251 5a6e 7e 5c 90                  	jmp	flash_error	;
1252                                
1253                                u8_d_datloop:
1254 5a71 84 f0                     	anda	#$f0		;5101 is only 4 bits wide.  Mask unused bits.
1255 5a73 a7 00                     	staa	0,x		;write to the 5101.
1256 5a75 e6 00                     	ldab	0,x		;read from the 5101.
1257 5a77 c4 f0                     	andb	#$f0		;5101 is only 4 bits wide.  Mask unused bits.
1258 5a79 11                        	cba			;compare a and b accumulators.
1259 5a7a 26 ea                     	bne	#u8_d_errloop	;loop on the error till it clears.
1260 5a7c 8b 10                     	adda	#$10		;inca on MSB side, lsb 4 bits stay zero.
1261 5a7e 84 f0                     	anda	#$f0		;just to be sure.
1262 5a80 26 ef                     	bne	#u8_d_datloop	;data is 00-FF on FF we roll to 00 indicating
1263                                				;we have checked all data on current address.
1264 5a82 08                        	inx			;inc x to next addr.
1265 5a83 8c 03 00                  	cpx	#u8_max+1	;if past max addr then we are done.
1266 5a86 26 d8                     	bne	#u8_d_nextadr	;not done; do next address.
1267                                
1268 5a88 39                        	rts			;return to caller.
1269                                
1270                                
1271                                u8_address_test:
1272 5a89 ce 02 00                  	ldx	#u8_min		;5101 starting address
1273 5a8c 86 00                     	ldaa	#$0		;aa will be expected data
1274 5a8e 97 50                     	staa	var_1		;Clear variable located in 6810 used for uniq.
1275 5a90 c6 ff                     	ldab	#$ff		;ab will be actual. Init to anything else; we
1276                                				;start at zero so this must get zero on a read
1277 5a92 20 0b                     	bra	#u8_a_datloop
1278                                
1279                                u8_a_errloop:
1280 5a94 7f ff fe                  	clr	#reset_vector	;failure check in.  Write to read only space.
1281 5a97 f6 58 00                  	ldab	error_action	;sets CCs.
1282 5a9a 27 03                     	beq	#u8_a_datloop	;no flash error.
1283 5a9c 7e 5c 90                  	jmp	flash_error	;
1284                                
1285                                u8_a_datloop:
1286 5a9f 9b 50                     	adda	var_1		;A+M->A var_1 allows us to do uniqueness.
1287 5aa1 84 f0                     	anda	#$f0		;5101 is only 4 bits wide.  Mask unused bits.
1288 5aa3 a7 00                     	staa	0,x		;write to the 5101.
1289 5aa5 e6 00                     	ldab	0,x		;read/verify data.
1290 5aa7 c4 f0                     	andb	#$f0		;5101 is only 4 bits wide.  Mask unused bits.
1291 5aa9 11                        	cba			;compare a and b accumulators.
1292 5aaa 26 e8                     	bne	#u8_a_errloop	;loop on the error till it clears.
1293 5aac 8b 10                     	adda	#$10		;inca. msb, already has the uniq cnt offset.
1294 5aae 84 f0                     	anda	#$f0		;5101 is only 4 bits wide.  Mask unused bits.
1295 5ab0 26 08                     	bne 	#u8_continue	;on 0 we will increment var_1.
1296 5ab2 d6 50                     	ldab	var_1		;get current cnt in b.
1297 5ab4 cb 10                     	addb	#$10		;inc b (really cnt) used to provide addr uniq.
1298 5ab6 c4 f0                     	andb	#$f0		;5101 is only 4 bits wide.  Mask unused bits.
1299 5ab8 d7 50                     	stab	var_1		;put new count back in cnt.
1300                                u8_continue:
1301 5aba 08                        	inx			;inc x to next addr.
1302 5abb 8c 03 00                  	cpx	#u8_max+1	;if past max addr then we are done.
1303 5abe 26 df                     	bne	#u8_a_datloop	;not done; do next address.
1304                                
1305                                u8_addr_uniq:
1306                                
1307                                u8_uclr:
1308 5ac0 ce 02 00                  	ldx	#u8_min		;Start addr of 5101.
1309 5ac3 86 00                     	ldaa	#$0
1310                                
1311                                u8_uclr_addr:
1312 5ac5 a7 00                     	staa	0,x		;clear 5101.
1313 5ac7 08                        	inx			;inc x to next addr.
1314 5ac8 8c 03 00                  	cpx	#u8_max+1	;if past max addr then we are done.
1315 5acb 26 f8                     	bne	#u8_uclr_addr	;not done.
1316                                
1317 5acd ce 02 00                  	ldx	#u8_min
1318 5ad0 86 f0                     	ldaa	#$f0		;pattern to write to 5101.
1319                                
1320                                u8_uloop:
1321 5ad2 e6 00                     	ldab	0,x		;check before writing.
1322 5ad4 c4 f0                     	andb	#$f0		;mask out unused bits.
1323 5ad6 c1 00                     	cmpb	#$0		;verify loc is zero.	
1324 5ad8 26 09                     	bne	u8_uerror	;go try to loop on error.
1325 5ada a7 00                     	staa	0,x		;loc was zero; write pattern to loc.
1326 5adc 08                        	inx			;next loc.
1327 5add 8c 03 00                  	cpx	#u8_max+1	;check if done.
1328 5ae0 26 f0                     	bne	u8_uloop	;not done.
1329                                
1330 5ae2 39                        	rts			;return to caller.
1331                                
1332                                
1333                                u8_uerror:
1334 5ae3 df 50                     	stx	var_1		;loc that was in error.
1335 5ae5 6f 00                     	clr	0,x		;clear error loc.
1336 5ae7 ce 02 00                  	ldx	#u8_min		;setup to find location that overwrote
1337                                				;the location just stored in var_1.
1338 5aea 86 f0                     	ldaa	#$f0		;reload a with same data.
1339                                
1340                                u8_find_loc:
1341                                
1342 5aec a7 00                     	staa	0,x
1343 5aee 35                        	txs			;hold x in sp for a moment.
1344 5aef de 50                     	ldx	var_1		;now get fail addr to check.
1345 5af1 e6 00                     	ldab	0,x		;
1346 5af3 30                        	tsx			;put x held in sp back into x.
1347 5af4 c4 f0                     	andb	#$f0		;mask out unused bits.
1348 5af6 df 52                     	stx	var_2		;Addr in var_2 confilicts with addr in var_1.
1349 5af8 c1 00                     	cmpb	#$0		;check error loc was still zero.  If not,
1350 5afa 26 12                     	bne	u8_uerr_loop	;then try again.
1351 5afc 08                        	inx			;try next loc.
1352 5afd 9c 50                     	cpx	var_1		;don't need to go past addr in var_1.
1353 5aff 27 1b                     	beq	u8_unot		;did not find bad address.	
1354                                
1355 5b01 86 f0                     	ldaa	#$f0		;to be safe.
1356                                
1357                                ;	Note:  we enter at u8_uerr_loop, we loop to checkin.  This allows us to
1358                                ;	see the problem occur immediately before error check in.
1359                                u8_checkin_lp:
1360 5b03 7f ff fe                  	clr	#reset_vector	;failure check in.  Write to read only space.
1361 5b06 f6 58 00                  	ldab	error_action	;sets CCs.
1362 5b09 27 03                     	beq	#u8_uerr_loop	;no flash error.
1363 5b0b 7e 5c 90                  	jmp	flash_error	;Set to flash on error.
1364                                
1365                                u8_uerr_loop:
1366 5b0e 6f 00                     	clr	0,x		;clear the addr in var_2.
1367 5b10 de 50                     	ldx	var_1		;address that destroyed data in loc var_2.
1368 5b12 a7 00                     	staa	0,x		;write to var_1 should wipe data in var_2 addr.
1369 5b14 de 52                     	ldx	var_2		;check we destroyed data in var_2 addr.
1370 5b16 e6 00                     	ldab	0,x		;read the data in var_2 addr.
1371 5b18 c4 f0                     	andb	#$f0		;mask unused.
1372 5b1a 26 e7                     	bne	#u8_checkin_lp	;stay in as long as we are failing.
1373                                
1374                                u8_unot:
1375 5b1c c6 0a                     	ldab	#10
1376 5b1e bd 5c fc                  	jsr	sflash_svc	;Flash 10 times short so we know the error was 
1377 5b21 7e 58 5a                  	jmp	start		;not located, we will re-start the test.
1378                                
1379                                
1380                                	; This is the Stern u13 test.  It will verify data and address 
1381                                	; uniqueness.  because the 5101 CMOS Ram is only 4 bits wide; we take
1382                                	; some great pains to see to it that we find conflicting addresses
1383                                	; in the address uniqueness test for this part so we can loop on
1384                                	; error.  The pain however is well worth the gain
1385                                	; as it may make using a scope easier; and certainly makes things
1386                                	; crystal clear on a logic analyzer.
1387                                	; Note: this test should only be run if a Stern MPU-200 is being
1388                                	; tested.  It should not be called when testing Bally MPUs or
1389                                	; when testing Stern MPU-100 MPUs.
1390                                	; U13 is occupies the same address space as U8.  U8 uses data bits
1391                                	; 4 - 7 while U13 uses data bits 0 - 3.
1392                                
1393                                u13_data_test:
1394                                
1395                                ;	u13_data attempts to check that each cell can hold any
1396                                ;	data pattern in the 5101.  address has not been qualified yet.
1397                                
1398                                
1399 5b24 ce 02 00                  	ldx	#u13_min
1400                                
1401                                u13_d_nextadr:
1402 5b27 86 00                     	ldaa	#$0		;aa will be expected data
1403 5b29 c6 ff                     	ldab	#$ff		;ab will be actual. Init to anything else; we
1404                                				;start at zero so this must get zero on a read
1405 5b2b 20 0b                     	bra	u13_d_datloop	
1406                                
1407                                u13_d_errloop:
1408 5b2d 7f ff fe                  	clr	#reset_vector	;failure check in.  Write to read only space.
1409 5b30 f6 58 00                  	ldab	error_action	;sets CCs.
1410 5b33 27 03                     	beq	#u13_d_datloop	;no flash error.
1411 5b35 7e 5c 90                  	jmp	flash_error	;
1412                                
1413                                u13_d_datloop:
1414 5b38 84 0f                     	anda	#$0f		;5101 is only 4 bits wide.  Mask unused bits.
1415 5b3a a7 00                     	staa	0,x		;write to the 5101.
1416 5b3c e6 00                     	ldab	0,x		;read from the 5101.
1417 5b3e c4 0f                     	andb	#$0f		;5101 is only 4 bits wide.  Mask unused bits.
1418 5b40 11                        	cba			;compare a and b accumulators.
1419 5b41 26 ea                     	bne	#u13_d_errloop	;loop on the error till it clears.
1420 5b43 8b 01                     	adda	#$01		;inca on MSB side, lsb 4 bits stay zero.
1421 5b45 84 0f                     	anda	#$0f		;just to be sure.
1422 5b47 26 ef                     	bne	#u13_d_datloop	;data is 00-FF on FF we roll to 00 indicating
1423                                				;we have checked all data on current address.
1424 5b49 08                        	inx			;inc x to next addr.
1425 5b4a 8c 03 00                  	cpx	#u13_max+1	;if past max addr then we are done.
1426 5b4d 26 d8                     	bne	#u13_d_nextadr	;not done; do next address.
1427                                
1428 5b4f 39                        	rts			;return to caller.
1429                                
1430                                
1431                                u13_addr_test:
1432 5b50 ce 02 00                  	ldx	#u13_min	;5101 starting address
1433 5b53 86 00                     	ldaa	#$0		;aa will be expected data
1434 5b55 97 50                     	staa	var_1		;Clear variable located in 6810 used for uniq.
1435 5b57 c6 ff                     	ldab	#$ff		;ab will be actual. Init to anything else; we
1436                                				;start at zero so this must get zero on a read
1437 5b59 20 0b                     	bra	#u13_a_datloop
1438                                
1439                                u13_a_errloop:
1440 5b5b 7f ff fe                  	clr	#reset_vector	;failure check in.  Write to read only space.
1441 5b5e f6 58 00                  	ldab	error_action	;sets CCs.
1442 5b61 27 03                     	beq	#u13_a_datloop	;no flash error.
1443 5b63 7e 5c 90                  	jmp	flash_error	;
1444                                
1445                                u13_a_datloop:
1446 5b66 9b 50                     	adda	var_1		;A+M->A var_1 allows us to do uniqueness.
1447 5b68 84 0f                     	anda	#$0f		;5101 is only 4 bits wide.  Mask unused bits.
1448 5b6a a7 00                     	staa	0,x		;write to the 5101.
1449 5b6c e6 00                     	ldab	0,x		;read/verify data.
1450 5b6e c4 0f                     	andb	#$0f		;5101 is only 4 bits wide.  Mask unused bits.
1451 5b70 11                        	cba			;compare a and b accumulators.
1452 5b71 26 e8                     	bne	#u13_a_errloop	;loop on the error till it clears.
1453 5b73 8b 01                     	adda	#$01		;inca. msb, already has the uniq cnt offset.
1454 5b75 84 0f                     	anda	#$0f		;5101 is only 4 bits wide.  Mask unused bits.
1455 5b77 26 08                     	bne 	#u13_continue	;on 0 we will increment var_1.
1456 5b79 d6 50                     	ldab	var_1		;get current cnt in b.
1457 5b7b cb 01                     	addb	#$01		;inc b (really cnt) used to provide addr uniq.
1458 5b7d c4 0f                     	andb	#$0f		;5101 is only 4 bits wide.  Mask unused bits.
1459 5b7f d7 50                     	stab	var_1		;put new count back in cnt.
1460                                u13_continue:
1461 5b81 08                        	inx			;inc x to next addr.
1462 5b82 8c 03 00                  	cpx	#u13_max+1	;if past max addr then we are done.
1463 5b85 26 df                     	bne	#u13_a_datloop	;not done; do next address.
1464                                
1465                                u13_addr_uniq:
1466                                
1467                                u13_uclr:
1468 5b87 ce 02 00                  	ldx	#u13_min	;Start addr of 5101.
1469 5b8a 86 00                     	ldaa	#$0
1470                                
1471                                u13_uclr_addr:
1472 5b8c a7 00                     	staa	0,x		;clear 5101.
1473 5b8e 08                        	inx			;inc x to next addr.
1474 5b8f 8c 03 00                  	cpx	#u13_max+1	;if past max addr then we are done.
1475 5b92 26 f8                     	bne	#u13_uclr_addr	;not done.
1476                                
1477 5b94 ce 02 00                  	ldx	#u13_min
1478 5b97 86 0f                     	ldaa	#$0f		;pattern to write to 5101.
1479                                
1480                                u13_uloop:
1481 5b99 e6 00                     	ldab	0,x		;check before writing.
1482 5b9b c4 0f                     	andb	#$0f		;mask out unused bits.
1483 5b9d c1 00                     	cmpb	#$0		;verify loc is zero.	
1484 5b9f 26 09                     	bne	u13_uerror	;go try to loop on error.
1485 5ba1 a7 00                     	staa	0,x		;loc was zero; write pattern to loc.
1486 5ba3 08                        	inx			;next loc.
1487 5ba4 8c 03 00                  	cpx	#u13_max+1	;check if done.
1488 5ba7 26 f0                     	bne	u13_uloop	;not done.
1489                                
1490 5ba9 39                        	rts			;return to caller.
1491                                
1492                                
1493                                u13_uerror:
1494 5baa df 50                     	stx	var_1		;loc that was in error.
1495 5bac 6f 00                     	clr	0,x		;clear error loc.
1496 5bae ce 02 00                  	ldx	#u13_min		;setup to find location that overwrote
1497                                				;the location just stored in var_1.
1498 5bb1 86 0f                     	ldaa	#$0f		;reload a with same data.
1499                                
1500                                u13_find_loc:
1501                                
1502 5bb3 a7 00                     	staa	0,x
1503 5bb5 35                        	txs			;hold x in sp for a moment.
1504 5bb6 de 50                     	ldx	var_1		;now get fail addr to check.
1505 5bb8 e6 00                     	ldab	0,x		;
1506 5bba 30                        	tsx			;put x held in sp back into x.
1507 5bbb c4 0f                     	andb	#$0f		;mask out unused bits.
1508 5bbd df 52                     	stx	var_2		;Addr in var_2 confilicts with addr in var_1.
1509 5bbf c1 00                     	cmpb	#$0		;check error loc was still zero.  If not,
1510 5bc1 26 12                     	bne	u13_uerr_loop	;then try again.
1511 5bc3 08                        	inx			;try next loc.
1512 5bc4 9c 50                     	cpx	var_1		;don't need to go past addr in var_1.
1513 5bc6 27 1b                     	beq	u13_unot	;did not find bad address.	
1514                                
1515 5bc8 86 0f                     	ldaa	#$0f		;to be safe.
1516                                
1517                                ;	Note:  we enter at u13_uerr_loop, we loop to checkin.  This allows us to
1518                                ;	see the problem occur immediately before error check in.
1519                                u13_checkin_lp:
1520 5bca 7f ff fe                  	clr	#reset_vector	;failure check in.  Write to read only space.
1521 5bcd f6 58 00                  	ldab	error_action	;sets CCs.
1522 5bd0 27 03                     	beq	#u13_uerr_loop	;no flash error.
1523 5bd2 7e 5c 90                  	jmp	flash_error	;Set to flash on error.
1524                                
1525                                u13_uerr_loop:
1526 5bd5 6f 00                     	clr	0,x		;clear the addr in var_2.
1527 5bd7 de 50                     	ldx	var_1		;address that destroyed data in loc var_2.
1528 5bd9 a7 00                     	staa	0,x		;write to var_1 should wipe data in var_2 addr.
1529 5bdb de 52                     	ldx	var_2		;check we destroyed data in var_2 addr.
1530 5bdd e6 00                     	ldab	0,x		;read the data in var_2 addr.
1531 5bdf c4 0f                     	andb	#$0f		;mask unused.
1532 5be1 26 e7                     	bne	#u13_checkin_lp	;stay in as long as we are failing.
1533                                
1534                                u13_unot:
1535 5be3 c6 0a                     	ldab	#10
1536 5be5 bd 5c fc                  	jsr	sflash_svc	;Flash 10 times short so we know the error was 
1537 5be8 7e 58 5a                  	jmp	start		;not located, we will re-start the test.
1538                                
1539                                
1540                                
1541                                
1542                                	; This pretty much completes addr uniqueness except for
1543                                	; the pia's selection and rom selection.
1544                                	; Writing to a PIA could, in theory cause a write
1545                                	; to the 6810 or the 5101; though this is highly unlikely,
1546                                	; there for we will not test it.
1547                                
1548                                ;===========================================================================
1549                                
1550                                
1551                                	; This is the PIA test for U10 and U11.  U11 is already pretty
1552                                	; much known to work at this point as we have been using
1553                                	; it to flash the LED.  U10 has never been touched however; nor
1554                                	; do we know that they are unique yet.
1555                                
1556                                
1557                                	; pia_test is a called routine.
1558                                	; var_1 on entry contains the base enable addr for the pia to test.
1559                                	; On error this call will loop on the error. On Pass it will return.
1560                                	; to the caller.
1561                                
1562                                pia_err:
1563 5beb 7f ff fe                  	clr	#reset_vector	;failure check in.  Write to read only space.
1564 5bee f6 58 00                  	ldab	error_action	;sets CCs.
1565 5bf1 27 03                     	beq	#pia_test	;no flash error.
1566 5bf3 7e 5c 90                  	jmp	flash_error	;
1567                                
1568                                pia_test:
1569 5bf6 de 50                     	ldx	var_1		;x has pia enable base addr.
1570 5bf8 86 00                     	ldaa	#pia_ddr_reg	;access ddr reg.
1571 5bfa 8a 30                     	oraa	#led_off	;fix bug where LED stays on in pia_test3
1572 5bfc a7 01                     	staa	cra_sel,x	;set ddr access.  PIA is now setup.
1573 5bfe 4f                        	clra			;
1574 5bff a7 02                     	staa	pia_reg_b_sel,x	;should clear ddrb reg.
1575 5c01 86 aa                     	ldaa	#$AA		;test pattern.
1576 5c03 a7 00                     	staa	pia_reg_a_sel,x	;should write to ddra reg.
1577 5c05 e6 00                     	ldab	pia_reg_a_sel,x	;should read from ddra reg.
1578 5c07 11                        	cba			;compare expected in A to actual in B.
1579 5c08 26 e1                     	bne	#pia_err	;loop on error.
1580                                
1581 5c0a 4f                        	clra			;clear a reg to verify ddrb was unique in pia.
1582 5c0b e6 02                     	ldab	pia_reg_b_sel,x	;ddrb should still be clear if unique.
1583 5c0d 11                        	cba			;compare expected in A to actual in B.
1584 5c0e 26 e6                     	bne	#pia_test	;loop on error.  Not unique.
1585 5c10 20 0b                     	bra	#pia_test_1
1586                                
1587                                pia_err_1:
1588 5c12 7f ff fe                  	clr	#reset_vector	;failure check in.  Write to read only space.
1589 5c15 f6 58 00                  	ldab	error_action	;sets CCs.
1590 5c18 27 03                     	beq	#pia_test_1	;no flash error.
1591 5c1a 7e 5c 90                  	jmp	flash_error	;
1592                                
1593                                pia_test_1:
1594                                
1595 5c1d 86 55                     	ldaa	#$55		;test pattern.
1596 5c1f a7 00                     	staa	pia_reg_a_sel,x	;should write to ddra reg.
1597 5c21 e6 00                     	ldab	pia_reg_a_sel,x	;should read from ddra reg.
1598 5c23 11                        	cba			;compare expected in A to actual in B.
1599 5c24 26 ec                     	bne	#pia_err_1	;loop on error.
1600 5c26 20 0b                     	bra	#pia_test_2
1601                                
1602                                pia_err_2:
1603 5c28 7f ff fe                  	clr	#reset_vector	;failure check in.  Write to read only space.
1604 5c2b f6 58 00                  	ldab	error_action	;sets CCs.
1605 5c2e 27 03                     	beq	#pia_test_2	;no flash error.
1606 5c30 7e 5c 90                  	jmp	flash_error	;
1607                                
1608                                pia_test_2:			;start checking drb reg.
1609 5c33 4f                        	clra			;
1610 5c34 a7 00                     	staa	pia_reg_a_sel,x	;clear ddra for uniqueness check.
1611 5c36 86 55                     	ldaa	#$55		;test pattern.
1612 5c38 a7 02                     	staa	pia_reg_b_sel,x	;should write to ddrb reg.
1613 5c3a e6 02                     	ldab	pia_reg_b_sel,x	;should read from ddrb reg.
1614 5c3c 11                        	cba			;compare expected in A to actual in B.
1615 5c3d 26 e9                     	bne	#pia_err_2	;loop on error.
1616 5c3f 20 0b                     	bra	#pia_test_3
1617                                
1618                                pia_err_3:
1619 5c41 7f ff fe                  	clr	#reset_vector	;failure check in.  Write to read only space.
1620 5c44 f6 58 00                  	ldab	error_action	;sets CCs.
1621 5c47 27 03                     	beq	#pia_test_3	;no flash error.
1622 5c49 7e 5c 90                  	jmp	flash_error	;
1623                                
1624                                pia_test_3:	
1625 5c4c 86 aa                     	ldaa	#$AA		;test pattern.
1626 5c4e a7 02                     	staa	pia_reg_b_sel,x	;should write to ddrb reg.
1627 5c50 e6 02                     	ldab	pia_reg_b_sel,x	;should read from ddrb reg.
1628 5c52 11                        	cba			;compare expected in A to actual in B.
1629 5c53 26 ec                     	bne	#pia_err_3	;loop on error.
1630 5c55 e6 00                     	ldab	pia_reg_a_sel,x	;ddra should still be clear. Sets CCs.
1631 5c57 26 cf                     	bne	#pia_err_2	;ddra/b not unique loop to err_2 to see writes.
1632                                				;Note:  This error will leave LED ON if cra
1633                                				;was not loaded with ddra sel OR'd w/ led_off.
1634                                				;Problem was cra set to CA2 input which is
1635                                				;pulled up on the board thus turning ON!
1636                                				;Now OR'd with led_off at start of pia_test.
1637 5c59 39                        	rts			;If here we passed.  Return to caller.
1638                                
1639                                ;===========================================================================
1640                                
1641                                	;this test tests that two pia'pia's are uniquely addressable.
1642                                	;var_1 contains the addr of the first pia to check.
1643                                	;var_2 contains the addr of the second pia to check.
1644                                	;on error this test loops.
1645                                	;on Pass this test returns to the caller.
1646                                
1647                                pia_uniq_err:
1648 5c5a 7f ff fe                  	clr	#reset_vector	;failure check in.  Write to read only space.
1649 5c5d f6 58 00                  	ldab	error_action	;sets CCs.
1650 5c60 27 03                     	beq	#pia_uniq	;no flash error.
1651 5c62 7e 5c 90                  	jmp	flash_error	;
1652                                
1653                                pia_uniq:
1654 5c65 de 50                     	ldx	var_1		;x has pia1 enable base addr.
1655 5c67 86 00                     	ldaa	#pia_ddr_reg	;access ddr reg.
1656 5c69 a7 01                     	staa	cra_sel,x	;set ddr access.  PIA is now setup.
1657 5c6b 4f                        	clra			;
1658 5c6c a7 00                     	staa	pia_reg_a_sel,x	;should clear ddra reg in pia1.
1659 5c6e a7 02                     	staa	pia_reg_b_sel,x	;should clear ddrb reg in pia1.
1660                                
1661 5c70 de 52                     	ldx	var_2		;x has pia2 enable base addr.
1662 5c72 86 00                     	ldaa	#pia_ddr_reg	;access ddr reg.
1663 5c74 a7 01                     	staa	cra_sel,x	;set ddr access.  PIA is now setup.
1664                                
1665 5c76 86 aa                     	ldaa	#$AA		;test pattern.
1666 5c78 a7 00                     	staa	pia_reg_a_sel,x	;write one pattern to ddra in pia2.
1667 5c7a a7 02                     	staa	pia_reg_b_sel,x	;write one pattern to ddrb in pia2.
1668 5c7c 86 55                     	ldaa	#$55		;test pattern.
1669 5c7e a7 00                     	staa	pia_reg_a_sel,x	;write one pattern to ddra in pia2.
1670 5c80 a7 02                     	staa	pia_reg_b_sel,x	;write one pattern to ddrb in pia2.
1671                                
1672 5c82 de 50                     	ldx	var_1		;x has pia1 enable base addr.
1673 5c84 4f                        	clra			;
1674 5c85 e6 00                     	ldab	pia_reg_a_sel,x	;ddra reg in pia1 should still be zero.
1675 5c87 11                        	cba			;compare expected in A to actual in B.
1676 5c88 26 d0                     	bne	#pia_uniq_err	;loop on error.
1677 5c8a e6 02                     	ldab	pia_reg_b_sel,x	;ddrb reg in pia1 should still be zero.
1678 5c8c 11                        	cba			;compare expected in A to actual in B.
1679 5c8d 26 cb                     	bne	#pia_uniq_err	;loop on error.
1680                                
1681 5c8f 39                        	rts			;return to caller.
1682                                
1683                                
1684                                	;This completes the checking of the PIA for now.
1685                                	;The PIA testing currently only attempts to verify the
1686                                	;two data direction registers ddra and ddrb.
1687                                
1688                                ;===========================================================================
1689                                
1690                                ;		The following are support routines.
1691                                
1692                                
1693                                ;===========================================================================
1694                                
1695                                	; flash_error.
1696                                	; This will set the b register to 5 flashes and jmp to sflash_sp_svc.
1697                                	; This routine does not return, it restarts.
1698                                
1699                                
1700                                flash_error:			;Currently we do not return so we do much.
1701                                				;and the heck with the stack.  It matters not.
1702 5c90 ce 4e 20                  	ldx	#20000		;delay so we can tell the difference.
1703                                				;when looping.
1704                                flash_err_delay:
1705 5c93 09                        	dex
1706 5c94 26 fd                     	bne	#flash_err_delay ; Delay to see flashes clearly.
1707                                
1708 5c96 c6 05                     	ldab	#$5		;b now holds the number of times to flash.
1709 5c98 ce 5c 9e                  	ldx	#flash_err_ret	;x has return address.
1710 5c9b 7e 5d 4b                  	jmp	sflash_sp_svc	;Go flash the light 5 short times.
1711                                				;sflash_sp returns to our caller.
1712                                flash_err_ret:
1713 5c9e b6 58 00                  	ldaa	error_action	;Find out what to do here.
1714 5ca1 81 02                     	cmpa	#halt_val	;
1715 5ca3 27 07                     	beq	#halt_loop	;effectively halt the testing.
1716 5ca5 81 01                     	cmpa	#restart_val	;
1717 5ca7 27 00                     	beq	#flash_error_rst	;go restart tests.
1718                                				;any other value will currently restart also,
1719                                				;but is not guaranteed to do so in later
1720                                				;revisions.
1721                                flash_error_rst:
1722 5ca9 7e 58 5a                  	jmp	start		;flash complete, now restart from scratch.
1723                                
1724                                ;===========================================================================
1725                                
1726                                		;This loop does nothing and is an infinite loop on itself
1727                                		;as there is no halt instruction for the 6800.
1728                                
1729                                halt_loop:
1730 5cac 7f ff fe                  	clr	#reset_vector	;failure check in.  Write to read only space.
1731                                halt_lp:
1732 5caf 01                        	nop
1733 5cb0 01                        	nop
1734 5cb1 20 fc                     	bra	#halt_lp	;loop on nothing to simulate a halted program.
1735                                
1736                                ;===========================================================================
1737                                		;common_return will allow us to save some space rather
1738                                		;than repeat code for the restore/rts of some calls.
1739                                		;It also makes us consistent.
1740                                
1741                                common_return:
1742                                
1743 5cb3 33                        	pulb			;restoring x.
1744 5cb4 32                        	pula			;restoring x.
1745 5cb5 d7 57                     	stab	x_place+1	;restoring x.
1746 5cb7 97 56                     	staa	x_place		;restoring x.
1747 5cb9 de 56                     	ldx	x_place		;x is now restored.
1748 5cbb 33                        	pulb			;restore b.
1749 5cbc 32                        	pula			;restore a.
1750 5cbd 39                        	rts			;return to caller.
1751                                
1752                                ;===========================================================================
1753                                
1754                                one_sflash:
1755                                
1756 5cbe 37                        	pshb			;save b register.
1757                                
1758 5cbf c6 01                     	ldab	#$1		;b now holds the number of times to flash.
1759 5cc1 bd 5c fc                  	jsr	sflash_svc	;Go flash the light.
1760                                
1761 5cc4 33                        	pulb			;restore b register.
1762 5cc5 39                        	rts			;return to caller.
1763                                
1764                                ;===========================================================================
1765                                
1766                                	; one_flash is a called routine.  It will flash the led
1767                                	; N number of times based on the value in the b register.
1768                                	; there are no passed parameters.
1769                                one_flash:
1770                                
1771 5cc6 37                        	pshb			;save b register.
1772                                
1773 5cc7 c6 01                     	ldab	#$1		;b now holds the number of times to flash.
1774 5cc9 bd 5c ce                  	jsr	flash_svc	;Go flash the light.
1775                                
1776 5ccc 33                        	pulb			;restore b register.
1777 5ccd 39                        	rts			;return to caller.
1778                                
1779                                ;===========================================================================
1780                                
1781                                	; flash_svc:
1782                                	; flash the LED N times based on contents of b register.
1783                                	; Registers are preserved.
1784                                
1785                                flash_svc:
1786                                
1787 5cce 36                        	psha			;Save A.
1788 5ccf 37                        	pshb			;Save B.
1789 5cd0 d7 58                     	stab	temp		;b has count need to hold b reg temporarily.
1790 5cd2 df 56                     	stx	x_place		; setup to push x also.
1791 5cd4 96 56                     	ldaa	x_place		; 
1792 5cd6 d6 57                     	ldab	x_place+1	;
1793 5cd8 36                        	psha			; x high onto stack
1794 5cd9 37                        	pshb			; x low onto stack
1795 5cda d6 58                     	ldab	temp		; b should now have the flash count again.
1796                                
1797                                flash_loop:
1798                                
1799 5cdc ce 00 90                  	ldx	#u11_sel	;x has u11 enable base addr.
1800 5cdf 86 38                     	ldaa	#led_on		;aa set to enable CA2 as output, LED on.
1801 5ce1 a7 01                     	staa	cra_sel,x	;LED should turn on now.
1802 5ce3 ce 75 30                  	ldx	#30000		;LED On count.
1803                                
1804                                flash_on:
1805                                
1806 5ce6 09                        	dex			; should decrement x by 1.
1807 5ce7 26 fd                     	bne	#flash_on	; keep on for LED on count. 
1808                                
1809                                ;	setup to turn off now to complete flash.
1810                                
1811 5ce9 ce 00 90                  	ldx	#u11_sel	;x has u11 enable base addr.
1812 5cec 86 30                     	ldaa	#led_off	;aa set to enable CA2 as output, LED on.
1813 5cee a7 01                     	staa	cra_sel,x	;LED should turn off now.
1814 5cf0 ce 75 30                  	ldx	#30000		;LED Off count.
1815                                
1816                                flash_off:
1817 5cf3 09                        	dex			;should decrement x by 1.
1818 5cf4 26 fd                     	bne	#flash_off	;keep off for LED off count. 
1819 5cf6 5a                        	decb
1820 5cf7 26 e3                     	bne	#flash_loop	;go till done flashing.
1821                                
1822 5cf9 7e 5c b3                  	jmp	common_return	;common return routine to save some space.
1823                                				;and also keep things simple.
1824                                
1825                                ;===========================================================================
1826                                
1827                                	; sflash_svc:
1828                                	; same as flash_svc except this does short flashes.
1829                                	; flash the LED N times based on contents of b register.
1830                                	; Registers are preserved.
1831                                
1832                                
1833                                sflash_svc:
1834                                
1835 5cfc 36                        	psha			;Save A.
1836 5cfd 37                        	pshb			;Save B.
1837 5cfe d7 58                     	stab	temp		;b has count need to hold b reg temporarily.
1838 5d00 df 56                     	stx	x_place		; setup to push x also.
1839 5d02 96 56                     	ldaa	x_place		; 
1840 5d04 d6 57                     	ldab	x_place+1	;
1841 5d06 36                        	psha			; x high onto stack
1842 5d07 37                        	pshb			; x low onto stack
1843 5d08 d6 58                     	ldab	temp		; b should now have the flash count again.
1844                                
1845                                sflash_loop:
1846                                
1847 5d0a ce 00 90                  	ldx	#u11_sel	;x has u11 enable base addr.
1848 5d0d 86 38                     	ldaa	#led_on		;aa set to enable CA2 as output, LED on.
1849 5d0f a7 01                     	staa	cra_sel,x	;LED should turn on now.
1850 5d11 ce 23 28                  	ldx	#9000		;LED On count.
1851                                
1852                                sflash_on:
1853                                
1854 5d14 09                        	dex			; should decrement x by 1.
1855 5d15 26 fd                     	bne	#sflash_on	; keep on for LED on count. 
1856                                
1857                                ;	setup to turn off now to complete flash.
1858                                
1859 5d17 ce 00 90                  	ldx	#u11_sel	;x has u11 enable base addr.
1860 5d1a 86 30                     	ldaa	#led_off	;aa set to enable CA2 as output, LED on.
1861 5d1c a7 01                     	staa	cra_sel,x	;LED should turn off now.
1862 5d1e ce 55 f0                  	ldx	#22000		;LED Off count.
1863                                
1864                                sflash_off:
1865 5d21 09                        	dex			; should decrement x by 1.
1866 5d22 26 fd                     	bne	#sflash_off	; keep off for LED off count. 
1867 5d24 5a                        	decb
1868 5d25 26 e3                     	bne	#sflash_loop	; go till done flashing.
1869                                
1870 5d27 7e 5c b3                  	jmp	common_return	;common return routine to save some space.
1871                                				;and also keep things simple.		
1872                                
1873                                ;===========================================================================
1874                                
1875                                	; flash_sp_svc
1876                                	; flash the LED N times based on contents of b register.
1877                                	; On Entry this routine expects the return address in x.
1878                                	;
1879                                	; This routine should be used prior to stack availability.
1880                                	; flash_svc is a called routine that should be used once 
1881                                	; the stack has been tested good if you need to save registers.
1882                                	; This routine does not save any registers!!
1883                                
1884                                flash_sp_svc:
1885                                
1886 5d2a 35                        	txs			; Hold return address in sp.
1887                                
1888                                flash_sp_loop:
1889                                
1890 5d2b ce 00 90                  	ldx	#u11_sel	;x has u11 enable base addr.
1891 5d2e 86 38                     	ldaa	#led_on		;aa set to enable CA2 as output, LED on.
1892 5d30 a7 01                     	staa	cra_sel,x	;LED should turn on now.
1893 5d32 ce 75 30                  	ldx	#30000		;LED On count.
1894                                
1895                                flash_sp_on:
1896                                
1897 5d35 09                        	dex			; should decrement x by 1.
1898 5d36 26 fd                     	bne	#flash_sp_on	; keep on for LED on count. 
1899                                
1900                                ;	setup to turn off now to complete flash.
1901                                
1902 5d38 ce 00 90                  	ldx	#u11_sel	;x has u11 enable base addr.
1903 5d3b 86 30                     	ldaa	#led_off	;aa set to enable CA2 as output, LED on.
1904 5d3d a7 01                     	staa	cra_sel,x	;LED should turn off now.
1905 5d3f ce 75 30                  	ldx	#30000		;LED Off count.
1906                                
1907                                flash_sp_off:
1908 5d42 09                        	dex			;should decrement x by 1.
1909 5d43 26 fd                     	bne	#flash_sp_off	;keep off for LED off count. 
1910 5d45 5a                        	decb
1911 5d46 26 e3                     	bne	#flash_sp_loop	;go till done flashing.
1912 5d48 30                        	tsx			;restore return address from sp.
1913 5d49 6e 00                     	jmp	0,x		;return to caller.
1914                                
1915                                ;===========================================================================
1916                                
1917                                	; sflash_sp_svc
1918                                	; flash the LED N times based on contents of b register.
1919                                	; On Entry this routine expects the return address in x.
1920                                	;
1921                                	; This routine should be used prior to stack availability.
1922                                	; sflash_svc is a called routine that should be used once 
1923                                	; the stack has been tested good if you need to save registers.
1924                                	; This routine does not save any registers!!
1925                                
1926                                sflash_sp_svc:
1927                                
1928 5d4b 35                        	txs			; Hold return address in sp.
1929                                
1930                                sflash_sp_loop:
1931                                
1932 5d4c ce 00 90                  	ldx	#u11_sel	;x has u11 enable base addr.
1933 5d4f 86 38                     	ldaa	#led_on		;aa set to enable CA2 as output, LED on.
1934 5d51 a7 01                     	staa	cra_sel,x	;LED should turn on now.
1935 5d53 ce 23 28                  	ldx	#9000		;LED On count.
1936                                
1937                                sflash_sp_on:
1938                                
1939 5d56 09                        	dex			; should decrement x by 1.
1940 5d57 26 fd                     	bne	#sflash_sp_on	; keep on for LED on count. 
1941                                
1942                                ;	setup to turn off now to complete flash.
1943                                
1944 5d59 ce 00 90                  	ldx	#u11_sel	;x has u11 enable base addr.
1945 5d5c 86 30                     	ldaa	#led_off	;aa set to enable CA2 as output, LED on.
1946 5d5e a7 01                     	staa	cra_sel,x	;LED should turn off now.
1947 5d60 ce 55 f0                  	ldx	#22000		;LED Off count.
1948                                
1949                                sflash_sp_off:
1950 5d63 09                        	dex			; should decrement x by 1.
1951 5d64 26 fd                     	bne	#sflash_sp_off	; keep off for LED off count. 
1952 5d66 5a                        	decb
1953 5d67 26 e3                     	bne	#sflash_sp_loop	; go till done flashing.
1954 5d69 30                        	tsx			;restore return address to x.
1955 5d6a 6e 00                     	jmp	0,x		;return to caller.
1956                                
1957                                
1958                                	;display_svc displays a digit in all player displays.
1959                                	;currently we do not do the match/ball in play display
1960                                	;aka status display.  On entry B hold the digit value.
1961                                	;registers are preserved.
1962                                
1963                                display_svc:
1964                                ;	attempt to display digits in displays.
1965                                
1966 5d6c 36                        	psha			;save A reg.
1967 5d6d 37                        	pshb			;save B reg.
1968 5d6e d7 58                     	stab	temp		;b holds value to display. IE: 0-9.
1969 5d70 df 56                     	stx	x_place		; setup to push x also.
1970 5d72 96 56                     	ldaa	x_place		;
1971 5d74 d6 57                     	ldab	x_place+1	;
1972 5d76 36                        	psha			; x high onto stack
1973 5d77 37                        	pshb			; x low onto stack
1974 5d78 d6 58                     	ldab	temp		; display value should be restored.
1975 5d7a 53                        	comb			; compliment BCD to the display.
1976                                
1977 5d7b ce 00 90                  	ldx	#u11_sel	;x has u11 enable base addr.
1978 5d7e 86 30                     	ldaa	#led_off	;aa set to enable U11 CA2 as output.
1979 5d80 8a 00                     	oraa	#pia_ddr_reg	;add in ddr sel.  Note we keep the LED off!
1980 5d82 a7 01                     	staa	cra_sel,x	;CA2 is now low; selecting ddra.
1981 5d84 86 ff                     	ldaa	#$FF		;setup to enable PA0-PA7 out.
1982 5d86 a7 00                     	staa	pia_ddr_reg,x	;PA0-PA7 of U11 now enabled as outputs.
1983 5d88 86 00                     	ldaa	#$00		;All digit strobes (Negated) ignore match/stat.
1984                                				;Note: A $C0 would shut off the left digits. 
1985 5d8a a7 00                     	staa	pia_reg_a_sel,x	;set digit strobes; match status display off.
1986                                
1987                                	;set blanking by setting CA2 LOW to enable displays to latch data.
1988                                
1989 5d8c ce 00 88                  	ldx	#u10_sel	;x has u10 enable base addr.
1990 5d8f 86 30                     	ldaa	#led_off	;aa set to enable U10 CA2 as output.
1991 5d91 8a 00                     	oraa	#pia_ddr_reg	;add in ddr sel.
1992 5d93 a7 01                     	staa	cra_sel,x	;CA2 is now low and blanking; selecting ddra.
1993 5d95 86 ff                     	ldaa	#$FF		;setup to enable PA0-PA7 out.
1994 5d97 a7 00                     	staa	pia_ddr_reg,x	;PA0-PA7 U10 enabled. BCD and player latches.
1995 5d99 c4 f0                     	andb	#$F0		;Guarantee BCD data is valid in high nibble.
1996 5d9b ca 0f                     	orab	#$0F		;BCD with latches cleared.
1997 5d9d e7 00                     	stab	pia_reg_a_sel,x	;BCD from b reg now ouputing at U10 PA4-7.
1998 5d9f c4 f0                     	andb	#$F0		;BCD with latches set.
1999 5da1 e7 00                     	stab	pia_reg_a_sel,x	;player latches go high.
2000 5da3 ca 0f                     	orab	#$0F		;ready to reset player latches.
2001 5da5 e7 00                     	stab	pia_reg_a_sel,x	;BCD with latches cleared.
2002 5da7 86 38                     	ldaa	#led_on		;aa set to enable U10 CA2 as output.
2003 5da9 a7 01                     	staa	cra_sel,x	;CA2 high, blanking off, data now on displays.
2004                                
2005 5dab 86 1f                     	ldaa	#blank_time	;loops before toggle blank for RC network.
2006 5dad 97 5c                     	staa	blank_cnt	;Serves as a counter for now.
2007 5daf df 56                     	stx	x_place		;holding x pointing to U10.
2008 5db1 ce 27 10                  	ldx	#10000		;pause in an attempt to delay to see digits.
2009                                display_lp:
2010                                
2011 5db4 7a 00 5c                  	dec	blank_cnt	;
2012 5db7 26 0e                     	bne	display_lp2	;go around and continue.  No blank this time.
2013 5db9 df 58                     	stx	temp		;storing count.
2014 5dbb de 56                     	ldx	x_place		;restore x pointing to U10.
2015 5dbd 86 30                     	ldaa	#led_off	;set to blank.
2016 5dbf a7 01                     	staa	cra_sel,x	;CA2 now low; blanking is on.
2017 5dc1 86 38                     	ldaa	#led_on		;set to not blank.
2018 5dc3 a7 01                     	staa	cra_sel,x	;CA2 now high; blanking is off displays on.
2019 5dc5 de 58                     	ldx	temp		;restore count into x.
2020                                
2021                                display_lp2:
2022                                
2023 5dc7 7d 00 5c                  	tst	blank_cnt	;
2024 5dca 26 04                     	bne	display_lp3	;
2025 5dcc 86 1f                     	ldaa	#blank_time	;loops before toggle blank for RC network.
2026 5dce 97 5c                     	staa	blank_cnt	;reloading blank_count.
2027                                display_lp3:
2028                                
2029 5dd0 09                        	dex			;dec count in x
2030 5dd1 26 e1                     	bne	display_lp	;delay if x not zero.
2031                                
2032                                	;set blanking to turn off displays prior to exiting.
2033                                
2034 5dd3 ce 00 88                  	ldx	#u10_sel	;x has u10 enable base addr.
2035 5dd6 86 30                     	ldaa	#led_off	;aa set to enable U10 CA2 as output.
2036 5dd8 8a 00                     	oraa	#pia_ddr_reg	;add in ddr sel.
2037 5dda a7 01                     	staa	cra_sel,x	;CA2 is now low; selecting ddra.
2038                                
2039 5ddc ce 13 88                  	ldx	#5000		;pause to see that we blanked succesfully.
2040                                display_lp1:
2041                                
2042 5ddf 09                        	dex
2043 5de0 26 fd                     	bne	display_lp1	;delay if x not zero.
2044                                
2045 5de2 7e 5c b3                  	jmp	common_return	;common return routine to save some space.
2046                                				;and also keep things simple.
2047                                
2048                                
2049                                ;===========================================================================
2050                                
2051                                	; Vector setup for various interrupts should they occur.
2052                                
2053 5ff8                           	org	u6_end-7	; start of 6800 vector table.
2054                                
2055                                	; Point unused interrupts to halt_loop.
2056                                	; Some day we may toy some more with them given a reason.
2057                                
2058 5ff8 5c ac                     	fdb	halt_loop	; FFF8,FFF9 IRQ	CURRENTLY NOT USED HERE.
2059 5ffa 5c ac                     	fdb	halt_loop	; FFFA,FFFB SWI	CURRENTLY NOT USED HERE.
2060 5ffc 58 41                     	fdb	show_revision	; FFFC,FFFD NMI CLEAR SWITCH (SW 33).
2061 5ffe 58 5a                     	fdb	start		; FFFE,FFFF RESET.
2062                                
2063                                ;===========================================================================

blank_cnt        005c *0660 2006 2011 2023 2026 
blank_time       001f *0645 2005 2025 
common_return    5cb3 *1741 1822 1870 2045 
copyright        5803 *0697 
cra_sel          0001 *0630 0750 0751 1572 1656 1663 1801 1813 1849 1861 
                       1892 1904 1934 1946 1980 1992 2003 2016 2018 2037 
crb_sel          0003 *0631 
digit_bcd_bits   00ff *0637 
digit_lp         5a4c *1203 1211 
digit_lp1        5a4e *1205 1209 
disp_bcd         005a *0659 
disp_cnt         005e *0661 
display_lp       5db4 *2009 2030 
display_lp1      5ddf *2040 2043 
display_lp2      5dc7 *2021 2012 
display_lp3      5dd0 *2027 2024 
display_svc      5d6c *1963 1206 
display_test     5a49 *1201 1191 
do_calls         59df *1093 
error_action     5800 *0684 0784 0827 0943 1040 1249 1281 1361 1409 1441 
                       1521 1564 1589 1604 1620 1649 1713 
fake_11a         5a1b *1144 1146 
fake_11b         5a26 *1152 1154 
fake_12          5a31 *1162 1164 
fake_flash_11    5a18 *1141 
fake_flash_12    5a29 *1156 
flash_err_delay  5c93 *1704 1706 
flash_err_ret    5c9e *1712 1709 
flash_error      5c90 *1700 0786 0829 0945 1042 1251 1283 1363 1411 1443 
                       1523 1566 1591 1606 1622 1651 
flash_error_rst  5ca9 *1721 1717 
flash_loop       5cdc *1797 1820 
flash_off        5cf3 *1816 1818 
flash_on         5ce6 *1804 1807 
flash_sp_loop    5d2b *1888 1911 
flash_sp_off     5d42 *1907 1909 
flash_sp_on      5d35 *1895 1898 
flash_sp_svc     5d2a *1884 0802 0857 0998 1057 
flash_svc        5cce *1785 1774 
halt_loop        5cac *1729 1715 2058 2059 
halt_lp          5caf *1731 1734 
halt_val         0002 *0644 1714 
irq_vector       fff8 *0638 
led_off          0030 *0629 0749 1571 1812 1860 1903 1945 1978 1990 2015 
                       2035 
led_on           0038 *0628 1800 1848 1891 1933 2002 2017 
loop_val         0000 *0642 0685 
nmi_vector       fffc *0640 
no               0000 *0613 
one_flash        5cc6 *1769 1073 1098 1105 1114 1123 1134 1174 1182 
one_sflash       5cbe *1754 
pass             588e *0759 
pass_return      5896 *0764 0761 
past_mpu_200     5a43 *1186 1165 
pia_ddr_reg      0000 *0634 1570 1655 1662 1979 1982 1991 1994 2036 
pia_err          5beb *1562 1579 
pia_err_1        5c12 *1587 1599 
pia_err_2        5c28 *1602 1615 1631 
pia_err_3        5c41 *1618 1629 
pia_out_reg      0004 *0635 
pia_reg_a_sel    0000 *0632 1576 1577 1596 1597 1610 1630 1658 1666 1669 
                       1674 1985 1997 1999 2001 
pia_reg_b_sel    0002 *0633 1574 1582 1612 1613 1626 1627 1659 1667 1670 
                       1677 
pia_test         5bf6 *1568 1113 1122 1565 1584 
pia_test_1       5c1d *1593 1585 1590 
pia_test_2       5c33 *1608 1600 1605 
pia_test_3       5c4c *1624 1616 1621 
pia_uniq         5c65 *1653 1133 1650 
pia_uniq_err     5c5a *1647 1676 1679 
player_latches   000f *0636 
reset_vector     fffe *0641 0783 0826 0942 1039 1248 1280 1360 1408 1440 
                       1520 1563 1588 1603 1619 1648 1730 
restart_val      0001 *0643 1716 
rev_x_lp         5854 *0718 0720 
revision         5802 *0692 
revision_lp      5851 *0716 0722 
revision_ret     584f *0714 0712 
revision_val     0004 *0646 0693 0711 
run_mpu_200      5a37 *1168 1139 
set_loop         5977 *0983 0988 
sflash_loop      5d0a *1845 1868 
sflash_off       5d21 *1864 1866 
sflash_on        5d14 *1852 1855 
sflash_sp_loop   5d4c *1930 1953 
sflash_sp_off    5d63 *1949 1951 
sflash_sp_on     5d56 *1937 1940 
sflash_sp_svc    5d4b *1926 0713 0763 0966 1710 
sflash_svc       5cfc *1833 1149 1159 1376 1536 1759 
show_revision    5841 *0704 2060 
stack_strt       004f *0647 1068 
start            585a *0724 0974 1190 1217 1377 1537 1722 2061 
start_delay      588b *0755 0757 
swi_vector       fffa *0639 
temp             0058 *0658 1789 1795 1837 1843 1968 1974 2013 2019 
temp_0           0000 *0664 0882 0887 0888 0915 0920 0925 0930 0950 0955 
test_mpu_200     5801 *0689 1137 
u10_mask         008b *0624 
u10_sel          0088 *0625 1120 1131 1989 2034 
u11_mask         0093 *0622 
u11_sel          0090 *0623 0748 1111 1129 1799 1811 1847 1859 1890 1902 
                       1932 1944 1977 
u13_a_datloop    5b66 *1445 1437 1442 1463 
u13_a_errloop    5b5b *1439 1452 
u13_addr_test    5b50 *1431 1181 
u13_addr_uniq    5b87 *1465 
u13_checkin_lp   5bca *1519 1532 
u13_continue     5b81 *1460 1455 
u13_d_datloop    5b38 *1413 1405 1410 1422 
u13_d_errloop    5b2d *1407 1419 
u13_d_nextadr    5b27 *1401 1426 
u13_data_test    5b24 *1393 1173 
u13_find_loc     5bb3 *1500 
u13_max          02ff *0627 1425 1462 1474 1487 
u13_min          0200 *0626 1399 1432 1468 1477 1496 
u13_uclr         5b87 *1467 
u13_uclr_addr    5b8c *1471 1475 
u13_uerr_loop    5bd5 *1525 1510 1522 
u13_uerror       5baa *1493 1484 
u13_uloop        5b99 *1480 1488 
u13_unot         5be3 *1534 1513 
u2_end           57ff *0617 
u2_strt          5000 *0616 
u6_end           5fff *0615 2053 
u6_strt          5800 *0614 0668 
u78_s_delay      59dc *1078 1080 
u7_aed_dec       5908 *0878 0883 
u7_aed_delay     596c *0971 0973 
u7_aed_find_loc  5925 *0911 0892 
u7_aed_found     5950 *0947 0928 0944 
u7_aed_foundlp   5945 *0941 0958 
u7_aed_inc       5916 *0889 0896 
u7_aed_next_adr  5930 *0922 0931 
u7_aed_next_dat  592c *0918 0933 
u7_aed_passed    5972 *0980 0900 
u7_aed_return    5988 *0999 0997 
u7_aed_test      5903 *0875 
u7_aed_unot      5961 *0960 0934 
u7_aedf_return   5969 *0967 0965 
u7_au0_ckdone    58ec *0844 0841 
u7_au0_delay     5900 *0862 0864 
u7_au0_done      58f5 *0851 0846 
u7_au0_err       58cd *0825 0837 0839 
u7_au0_loop      58d8 *0831 0823 0828 0842 0849 
u7_au0_part      58c8 *0821 
u7_au0_return    58fd *0858 0856 
u7_d_datloop     58af *0788 0780 0785 0794 
u7_d_errloop     58a4 *0782 0792 
u7_d_nextadr     589e *0776 0798 
u7_d_return      58c7 *0803 0801 
u7_data          589b *0768 
u7_max           007f *0619 0797 0845 0876 0877 0895 0987 1014 1034 
u7_min           0000 *0618 0664 0766 0774 0822 0833 0834 0836 0838 0981 
                       0982 1008 1026 
u7u8_chk         59a1 *1025 
u7u8_chklp       59a4 *1028 1035 
u7u8_clr         598d *1011 1015 
u7u8_delay       59d0 *1062 1064 
u7u8_err         59b0 *1038 1030 
u7u8_errlp       59bb *1044 1041 1049 
u7u8_lp          5998 *1018 1036 
u7u8_pass        59c5 *1052 1023 
u7u8_reent       59a8 *1032 1050 
u7u8_return      59cd *1058 1056 
u7u8_uniq        5988 *1007 
u8_a_datloop     5a9f *1285 1277 1282 1303 
u8_a_errloop     5a94 *1279 1292 
u8_addr_uniq     5ac0 *1305 
u8_address_test  5a89 *1271 1104 
u8_checkin_lp    5b03 *1359 1372 
u8_continue      5aba *1300 1295 
u8_d_datloop     5a71 *1253 1245 1250 1262 
u8_d_errloop     5a66 *1247 1259 
u8_d_nextadr     5a60 *1241 1266 
u8_data_test     5a5d *1233 1097 
u8_find_loc      5aec *1340 
u8_max           02ff *0621 1016 1265 1302 1314 1327 
u8_min           0200 *0620 1022 1239 1272 1308 1317 1336 
u8_uclr          5ac0 *1307 
u8_uclr_addr     5ac5 *1311 1315 
u8_uerr_loop     5b0e *1365 1350 1362 
u8_uerror        5ae3 *1333 1324 
u8_uloop         5ad2 *1320 1328 
u8_unot          5b1c *1374 1353 
var_1            0050 *0654 1112 1121 1130 1274 1286 1296 1299 1334 1344 
                       1352 1367 1434 1446 1456 1459 1494 1504 1512 1527 1569 
                       1654 1672 
var_2            0052 *0655 1132 1348 1369 1508 1529 1661 
var_3            0054 *0656 
wait_rev         5844 *0707 0709 
x_place          0056 *0657 1745 1746 1747 1790 1791 1792 1838 1839 1840 
                       1969 1970 1971 2007 2014 
yes              0001 *0612 0690 1138 


Number of errors 0
Number of warnings 0
