The old version is the version I did with Larry McDaniel.
The Instruction Register (IR) is responsible for receiving the instruction and breaking it up to decide what registers to use, for defining constants, and other things. It is a complex component with many parts to it.
The main part to the IR is the D-flip flop (DFF) that has a reset and an enable signal. The front of the DFF is an AO-22 (and-or gate). The Accusim simulation of the D-flip flop is here. The cell form was broken into 3 different parts (AO-22, buffer, and the DFF) and was assembled (unpeeked),(peeked). The MachTA simualtion of the D-flip flop is here.
Other parts were simpler. The Design Architect (DA) of the parts are INVERTER, BUFFER, NAND GATE, andTRI-STATE GATE.
The simulations of the parts in Accusim are here: INVERTER, BUFFER, NAND GATE, and TRI-STATE GATE.
The cell form from IC Station is as follows: INVERTER, BUFFER, NAND, TRI-STATE.
The MachTA simulations is as follows: INVERTER, BUFFER, NAND GATE, TRI-STATE GATE.
The DA schematic of the IR has all the parts wired together. The Accusim simulation of the IR is in parts: Part 1, Part 2, Part 3. The cell of the IR is quite large (unpeeked)(peeked) with some empty space.
To test the IR cell a dofile and a test vector file. The simulation results: Part 1, Part 2.
This version I did myself over Christmas 2000. Due to time restrictions we were unable to assemble the chip during the class. So a second class was added to assemble the parts.
I decided to redo the IR to save space on the SRC II chip. When I redid it I had reduced the IR in size by about 25%. They were the same in height, but not in length. This change due to the size of the D-flip flop. The orinial was 220 by 120 lambda, by I had changed it to 175 by 175 lambda. I also broke the DFF into four separate parts; AO-22, buffer, and the DFF in half to two separate parts.
The new cells of the DFF are here: (unpeeked)(peeked).
The other parts were changed to make them as tall as possible to save space so they could be placed closer together: INVERTER, BUFFER, NAND, TRI-STATE GATE.
The Instruction Register was redone in IC Station (unpeeked) (peeked). While there is still some space left it still is a major reduction from the old IR.
The IR was tested with the same dofile and test vector file as above. The simulation results for all parts was the same in both Accusim and MachTA.
