We decided to make the SRC a 2-bus instead of just a 1-bus architecture. We also decided to add new functions to the SRC, such as: XOR, XNOR, SWAP, .
The 2-bus had different time steps and affected the architecture of serveral parts: IR, Register File, Memory Interface, Control Unit, and ALU. The new functions added would affect the ALU and the control unit only.
The new ALU has a 32-bit XOR gate added to it. The control logic was changed to accomidate the new logic, and more logic was added after the 4:1 mux to control the output with the XOR function.
The new register file inputs from one bus and outputs to another. It has another set of two 4:16 mux(s) to allow outputs of two different sets of outputs from the Instruction Register.
The new IR has two sets of controls now to handle the Register File. This is to allow faster control for the SRC.
The new MI breaks the connection bewteen the input and output bus. That is the only major change to it.
The new CU has completely changed all of the functions in the control signal encoder section. It also modified some of the logic in the other 2 areas.
Assembly of the new SRC connects all of the parts together and uses the new 2-bus configuration. Then a symbol was created and placed in the final SRC to be tested. It was tested with all of the original programs from the regular SRC, as well as several new programs. The test was run using a dofile to set up signals and traces. (Adding Program) (Division Program) (Average Program and the RAM that goes with it) (Line Program and the RAM that goes with it) (Allother Program)
Results: Adding Results, Division Results (Part A)(Part B)(Part C), Average Results (Part A)(Part B), Line Program Results (Part A)(Part B), Allother Results (Part A)(Part B).
