The CCL is used for branch conditions and such. It loads from the bus and the IR to determine if a shift should occur or not. (schematic)
The SCL is used when a shift is being done in the ALU. It controls how many shifts are done and when the shift is complete. It contains full-adders, and D-flip flops. (schematic)
The ALU is responsible for most functions: adding, subtracting, incrementing by 4, shifting, and functions, or functions, as well as inverting data.
It has an A-control which can load the number from the bus or load a four. It also has a B-control which can load a number from the bud also it can invert the number from the bus.
The ALU has an adder which can add the two values from the bus. It also subtracts by adding the inverted from B-control to A-control. The adder is nothing but 32-full-adders.
The ALU has a shifter that can shift left, right, or circular. It just has one direction for left and one for right which just connects the bit to its corresponding left or right.
The ALU can AND or OR values from the bus but they are just 32-bit OR and AND gates.
The output of the ALU is controlled by a 4 to 1 mux. It decides which value from the adder, shifter, OR and AND gates is outputted to the bus.
The entire ALU is controlled by control logic that decides everything that the ALU does.
The complete ALU (schematic) shows the connections for all of the ALU parts.
A dofile test of the ALU is done by loading values into A and B and then setting each option high and read the output.
The ALU also has registers to hold the values for A and B inputs, and the output C.
The Register File holds values given to it. There are 32 registers and each register holds 32 bits. It is controlled by two 4:16 mux(s). It recieves and outputs values to the bus.
To test the register file a dofile was used. The complete test is here however, a zoomed in version of two sections, one for inputting data and one for outputting data to the bus. This test loads in values for each register and then outputs them back onto the bus.
Both the memory interface and the program counter and Instruction Register were provided by the instructor.
The control unit is a major part of the SRC. It tells all of the other parts what to do and when to do it. The hanging wires in the schematic are linked to their corresponding parts through name nets on the wires. The control signal encoder was the only wiring that we had to do.
All of the parts were assembled together (schematic) and tested. Then a symbol for it was created and placed in the main SRC with the memory and tested by running sample programs that were created to test all functions.
The dofile loads the traces for the signals, then runs the signals from the memory to begin the test.
The adder test is a simple program that adds two numbers together. It loads values into r1 and r2 then stores them in r3. It then sends the value to memory then reloads it into r4. The complete add test is here: ADDER TEST.
The division program is a program to divide one number by another and display the answer and remainder. The results of the division program are here: Part A, Part B.
The average program averages numbers together by reading how many numbers there are, then adding the numbers and dividing them. The numbers are read from the RAM and loaded into the SRC. The results of the register files are here: Part A, Part B.
The line program loads values from the RAM like the average program. It takes two known points on the line, then the X-value from the third and computes the Y-value. The results of the line program are here: Part A, Part B.
The allother program tests all the remaining functions the the other programs did not. The results are here: Part A, Part B.
