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NAND GATE
Definition: A combination of a NOT function and an AND function in a binary circuit that has two or more inputs and one output.

> The output is logic 0 only if all inputs are logic 1;
it is logic 1 if any input is logic 0.
Circuit Function
A CMOS NAND gate requires two series pull-down NMOS transistors connected to ground and two parallel pull-up PMOS transistors connected to the supply voltage. Only when there are two low inputs will the output go low (that is 00, 01, 10 gives a 1 and 11 gives a 0 output). Metal connects to the output and polysilicon as the input. If out-put metal layer from one gate connects to the next gate then the layer must be changed to polysilicon by inserting a contact between the metal and polysilicon layers.
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