|
Brian (Qiang)
Chen |
|
Cupertino, CA |
Phone:
(408) 480-7408 E-mail: [email protected] |
EXPERIENCE
Synopsys, Mountain View, CA (Apr. 2008 –
Present)
Research & Development Engineer
* Design for Manufacturing (DFM) flow optimization
o Research opportunities to optimize the overall Design for Manufacturing (DFM) flow with particular emphasis on design links using metrics such as performance, power, throughput, and mask costs
o Validate hypotheses from the research by building prototype flows and developing inter-tool links
o Productize new features in tools with various other R&D teams
Advanced Micro Devices, Inc.,
Member of Technical Staff (Aug. 2006 – Apr. 2008)
Senior Device Technology Engineer (Sep. 2003 – Aug. 2006)
* SPICE model extraction for active/passive devices used in advanced SOI technologies
o Varactor models for 45nm SOI technologies
o BSIMPD/BSIMSOI models for 90nm, 65nm, 45nm, 32nm technologies (both as individual contributor and project lead)
* Development of SPICE modeling infrastructure and methodologies
o Evaluation of PSP-SOI compact model developed by ASU & NXP
o Methodology for accurate off-current modeling in FB SOI MOSFETs
o SRAM-specific SPICE model extraction methodology
o Methodology for speculative SOI SPICE model extraction using self-heating free device targets
o Methodology and algorithm for self-heating free I-V data extraction including body current
o Holistic Idlow analysis methodology
o Methodology for device DC target QA for speculative (i.e., “guess”) model generation
o A priori hysteresis (“history effect”) modeling methodology
o Analysis of body current’s impact on hysteresis and its modeling
o Analysis of analog device characteristics
o Revelation of deficiency of using median I-V files for analog model extraction
o Analysis of self-heating option’s impact on ring oscillator Delay-Icc correlation
o Implementation of Indirect Body Initialization technique for ring oscillator simulation
o Evaluation of double-gate MOSFET compact models developed by UC Berkeley
* Device characterization (DC/AC/Transient)
o Improvement of component current/capacitance measurement
o S-parameter measurement
o Interim bench measurement gate-keeper, coordinating bench data collection and performing data QA, conversion and debugging to support modeling work
* Modeling and characterization automation
* Test chip development for various technologies
* Technology benchmarking and prediction
* Statistical modeling
Postdoctoral Fellow
* Compact modeling and simulations of QM effects in nanoscale devices
* Development of compact voltage-current, voltage-capacitance models of double-gate MOSFETs
Georgia
Institute of Technology,
Graduate Research Assistant at
* Developed physical, compact, analytical subthreshold swing and threshold voltage models for undoped double-gate (DG) MOSFETs
* Developed an original, scale-length based threshold voltage variation analysis technique, and performed comprehensive analysis of process variations
* Investigated overall impact of high-k gate dielectrics on DG MOSFET scaling
* Projected scaling limits of DG MOSFETs based on electrostatic integrity and process tolerance requirements
* Developed a physical via blockage model with applications to system-level a priori predictions
* Guest lecturer for a graduate level class “Gigascale Integration”
Korona
Semiconductor Company,
Engineer - Lead Engineer
* Performed process integration, parametric analysis, and yield analysis
* Managed lithography section
* Established fab floor Computer Integrated Manufacturing (CIM) computer network and developed prototype WIP tracking system
* Participated in furnace acceptance and responsible for control system maintenance
Mikron
Corporation,
Interning Engineer
* Developed Si* reactive ion etching (RIE) processes and simulation tools
S.-Petersburg
Electrotechnical U.,
Graduate Research Assistant in Quantum Optoelectronics Laboratory
* Performed analytical modeling of excitonic absorption in semiconductors
S.-Petersburg
Electrotechnical U.,
Undergraduate Research Assistant
in Quantum Optoelectronics Laboratory
*
Studied modulated electro-optical phenomena in
semiconductors
*
Developed data analysis and parameter extraction
software for Deep Level Transient Spectroscopy (DLTS)
HONORS
*
Spotlight Award for ‘Pioneering and establishing extraction, modeling, and simulation
methodology of MOSFET parasitic capacitances in Spice/CAD modeling-design flow,’
Advanced Micro Devices, Inc., May 2008
*
Spotlight Award for ‘Participation on the team that demonstrated and implemented a novel
methodology for improving SRAM bit cell SPICE model accuracy and correlation to
Silicon,’ Advanced Micro Devices, Inc., Feb. 2008
*
Member of Phase I Winning Team at Copper Design
Contest by Semiconductor Research Corporation, U.S., 2000
*
Diploma with Honors, S.-Petersburg Electrotechnical
University, Russia, 1996
*
Government Fellowship to Study in Soviet Union
(later Russia), China, 1989 – 1996
PROFESSIONAL ACTIVITIES
* Session Chair & Member of Technical Program Committee, IEEE Custom Integrated Circuit Conference, 2007-2008
* Member, Compact Model Council, Model QA sub-committee, 2007-2008
* Member, Compact Model Council, Surface-potential SOI model sub-committee, 2008
* Session Chair & Member of Technical Review Committee, Workshop on Compact Modeling, 2007-2008
*
Reviewer for IEEE
Transactions on Electron Devices (on the “Golden List” of reviewers since 2003)
*
Reviewer for Solid-State
Electronics, IEE Electronics Letters, IEE
Proceedings – Circuits, Devices, and Systems
TECHNICAL EXPERTISE & SKILLS
*
MOSFET device physics & circuit
o In-depth knowledge of MOSFET physics & MOSFET scaling theories
o Expertise in SOI MOSFET device physics and good knowledge of process flow
o Expertise in double-gate (DG) MOSFETs
o Good knowledge of circuit theory and analysis
* Compact modeling
o Expertise in BSIM-family compact spice models (BSIMPD, BSIMSOI) with good understanding of other compact spice models (PSP)
o Expertise in interconnect distribution theory and via blockage model
* Semiconductor processing technology & metrology
o Hands-on experience with Agilent VNA (E8364B) and Cascade WinCal package
o Expertise in polycrystalline silicon reactive ion etching (RIE) process development
o Hands-on experience with semiconductor parametric analyzer (HP4145) and probe station
o Hands-on experience with scanning electron microscope (SEM)
o Experience in photolithography
o In-depth knowledge and expertise in exciton theory in applications to photo-reflectance and photo-transmittance spectroscopy
o In-depth knowledge and hands-on experience in deep level transient spectroscopy (DLTS)
* TCAD
o Proficiency in 2D device simulator (Medici) to assist compact model development
* Programming languages
o Linux/unix shell scripting, Perl scripting
o C/C++, Fortran, Pascal, Visual Basic
*
Microelectronics and IC software packages
o Spice
model extraction: BSIMPro+, IC-CAP
o Circuit
simulator: Hspice, Spectre, Spice3
o Layout
editing and viewing: Virtuoso Layout, IC Workbench
o TCAD:
Medici
*
Technical programming: MatLab, Mathematica,
Maple
EDUCATION
Georgia Institute of Technology,
Ph.D. Electrical and Computer Engineering May 2003
Thesis Advisor: Prof. James D. Meindl
Thesis Title: Scaling Limits and Opportunities of
Double-Gate MOSFETs
Georgia
Institute of Technology,
M.S. Electrical and Computer Engineering
Dec. 2000
M.S. Engineering Feb. 1996
Thesis Advisors: Dr. Vladimir N. Bliznetsov and Prof. Yurii M.
Tairov
Thesis Title: Polysilicon Reactive Ion Etching for CMOS
VLSI (in Russian)
B.S. Engineering July 1994
Preparatory Department Nov.
1989 – Aug. 1990
University
of Science & Technology of China, Hefei, Anhui, China
Department of Radio & Electronics Aug. 1989 – Nov. 1989
PUBLICATIONS & PATENTS
30+ journal and refereed conference papers
6 US patents (pending)