Cupertino, CA

PUBLICATION LIST

JOURNAL PAPERS

1.          Q. Chen, L. Wang, and J. D. Meindl, “Fringe-induced barrier lowering (FIBL) included threshold voltage model for double-gate MOSFETs,” Solid-State Electronics, vol. 49, no. 2, pp.271-274, Feb. 2005.

2.          Q. Chen and J. D. Meindl, “Nanoscale MOSFETs: scaling limits and opportunities,” Nanotechnology, vol. 15, pp. S549–S555, 2004.

3.          Q. Chen, E. M. Harrell, and J. D. Meindl, "A physical short-channel threshold voltage model for undoped symmetric double-gate MOSFETs," IEEE Transactions on Electron Devices, vol. 50, no. 7, pp. 1631-1637, July 2003.

4.          Q. Chen, K. A. Bowman, E. M. Harrell, and J. D. Meindl, “Double jeopardy in the nanoscale court? – Modeling the scaling limits of double-gate MOSFETs with physics-based compact short-channel models of threshold voltage and subthreshold swing,” IEEE Circuits and Devices Magazine, vol. 19, no. 1, pp. 28-34, Jan. 2003.

5.          Q. Chen, B. Agrawal, and J. D. Meindl, “A comprehensive analytical subthreshold swing (S) model for double-gate MOSFETs,” IEEE Transactions on Electron Devices, vol. 49. no. 6, pp. 1086-1090, June 2002.

6.          J. D. Meindl, Q. Chen, and J. A. Davis, “Limits on silicon nanoelectronics for terascale integration,” Science, vol. 293, no. 5537, pp. 2044-2049, Sep. 14, 2001.

7.          Q. Chen, J. A. Davis, P. Zarkesh-Ha, and J. D. Meindl, “A compact physical via blockage model,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 8, no. 6, pp. 689-692, Dec. 2000.

8.          G. F. Glinskii and Q. Chen, “Electro-optical phenomena in direct-band semiconductors near the intrinsic absorption edge,” Izvestiya of Saint-Petersburg State Electrotechnical University (GETU), vol. 488, pp. 46-50, Dec. 1995.

INVITED PAPERS

9.          Q. Chen, Z.-Y. Wu, T. Ly, M. Gupta, V. Wason, J.-S. Goo, C. Thuruthiyil, M. Radwin, N. Subba, P. Chiney, S. Suryagandh, and A. B. Icel, “Extraction of speculative SOI MOSFET models using self-heating-free targets,” Proc. IEEE International Conference on Solid-State and Integrated-Circuit Technology (ICSICT), Beijing, China, Oct. 2008.

10.      J.-S. Goo, R. Q. Williams, G. O. Workman, Q. Chen, S. Lee, and E. J. Nowak, “Compact modeling and simulation of PD-SOI MOSFETs: current status and challenges,” Proc. IEEE Custom Integrated Circuits Conference (CICC), San Jose, CA, Sep. 2008.

11.      Q. Chen, L. Wang, and J. D. Meindl, “Physics-based device models for nanoscale double-gate MOSFETs,” Proc. IEEE International Conference on IC Design and Technology, Austin, TX, May 2004, pp. 73-79.

12.      Q. Chen, L. Wang, R. Murali, and J. D. Meindl, “Compact, physics-based modeling of nanoscale limits of double-gate MOSFETs,” Proc. the 7th International Conference on Modeling and Simulation of Microsystems (WCM-MSM2004), Boston, MA, Mar. 2004, pp. 114-119.

13.      Q. Chen and J. D. Meindl, “Nanoscale MOSFETs: scaling limits and opportunities,” Proc. IEEE Conference on Nanoscale Devices and System Integration (NDSI), Miami, FL, Feb. 2004, p. 105.

REFEREED CONFERENCE PAPERS

14.      Q. Chen, S. Balasubramanian, C. Thuruthiyil, M. Gupta, V. Wason, N. Subba, J.-S. Goo, P. Chiney, S. Krishnan, and A. B. Ali, “Critical current (ICRIT) based SPICE model extraction for SRAM cell,” Proc. IEEE International Conference on Solid-State and Integrated-Circuit Technology (ICSICT), Beijing, China, Oct. 2008.

15.      Q. Chen, J.-S. Goo, T. Ly, K. Chandrasekaran, Z.-Y. Wu, C. Thuruthiyil, and A. B. Icel, “Off-State leakage current modeling in low-power/high-performance partially-depleted (PD) floating-body (FB) SOI MOSFETs,” Proc. IEEE International Conference on Solid-State and Integrated-Circuit Technology (ICSICT), Beijing, China, Oct. 2008.

16.      J.-S. Goo, Q. Chen, A. Pandey, Y. Apanovich, T. Ly, V. Wason, N. Subba, C. Thuruthiyil, and A. B. Icel, “SPICE parameter extraction and RO validation of a 65nm SOI technology,” Proc. IEEE International Silicon on Insulator (SOI) Conference, Hudson River Valley, NY, Oct. 2008.

17.      S. Suryagandh, N. Subba, V. Wason, P. Chiney, Z.-Y. Wu, B. Q. Chen, S. Krishnan, M. Rathor, and A. Icel, “Model implementation for accurate variation estimation of analog parameters in advanced SOI technologies,” Proc. the 11th International Conference on Modeling and Simulation of Microsystems (WCM-MSM2008), Boston, MA, June 2008, pp. 822-824.

18.      S. Suryagandh, M. Gupta, Z.-Y. Wu, S. Krishnan, M. Pelella, J.-S. Goo, C. Thuruthiyil, J.X. An, B. Q. Chen, N. Subba, L. Zamudio, J. Yonemura, and A.B. Icel, “Impact of stress on various circuit characteristics in 65nm PDSOI technology,” Proc. the 37th European Solid-State Device Research Conference (ESSDERC2007), Munich, Germany, Sep. 2007, pp. 119-122.

19.      Y. Ma, Q. Chen, and H. Levinson, “Line edge roughness impact on critical dimension uniformity and device performance for sub-32nm technology,” Proc. the 51st Int. Conf. Electron, Ion, and Photon Beam Technology Nanofabrication (EIPBN), Denver CO, May 2007, PJ-4.

20.      Q. Chen, S. Suryagandh, J.-S. Goo, J. X. An, C. Thuruthiyil, and A. B. Icel, “Impact of gate induced drain leakage and impact ionization currents on hysteresis modeling of PD SOI circuits,” Proc. the 10th International Conference on Modeling and Simulation of Microsystems (WCM-MSM2007), Santa Clara, CA, May 2007, pp. 570-573.

21.      Q. Chen, Z.-Y. Wu, R. Y .K. Su, J.-S. Goo, C. Thuruthiyil, M. Radwin, N. Subba, S. Suryagandh, T. Ly, V. Wason, J. X. An, and A. B. Icel, “Extraction of self-heating free I-V curves including the substrate current of PD SOI MOSFETs,” Proc. IEEE International Conference on Microelectronic Test Structures, Tokyo, Japan, Mar. 2007, pp. 272-275.

22.      V. Wason, J. X. An, J.-S. Goo, Z.-Y. Wu, Q. Chen, C. Thuruthiyil, R. Topaloglu, P. Chiney, and A. Icel, “Statistical compact modeling and Si verification methodology,” Proc. IEEE  International Conference on Solid-State and Integrated-Circuit Technology (ICSICT), Shanghai, China, Oct. 2006, pp. 1198-1201.

23.      Q. Chen, Z.-Y. Wu, A. B. Icel，J.-S. Goo, S. Krishnan, C. Thuruthiyil, N. Subba, S. Suryagandh, J. X. An, T. Ly, M. Radwin, J. Yonemura, and F. Assad, “On Idlow with emphasis on speculative SPICE modeling,” Proc. the 9th International Conference on Modeling and Simulation of Microsystems (WCM-MSM2006), Boston, MA, May 2006, vol. 3, pp. 831-834.

24.      Q. Chen, J.-S. Goo, N. Subba, X. Cai, J. X. An, T. Ly, Z.-Y. Wu, S. Suryagandh, C. Thuruthiyil, M. Radwin, L. Zamudio, J. Yonemura, F. Assad, M.M. Pelella, and A. B. Icel, “An a priori hysteresis modeling methodology for improved efficiency and model accuracy in advanced PD SOI technologies,” Proc. the 8th International Conference on Modeling and Simulation of Microsystems (WCM-MSM2005), Anaheim, CA, May 2005, vol. 4, pp. 159-162.

25.      X. Wu, Q. Chen, P.C.H. Chan, and M. Chan (Best Student Paper Award), “A physical short-channel threshold voltage model for FinFET’s with non-rectangular cross-section,” Proc. International Meeting for Future of Electron Devices, Kansai, Japan,, Apr. 2005, pp. 29-30.

26.      C. Thuruthiyil, J. An, J. S. Goo, N. Subba, Q. Chen, S. Suryagandh, and A. Icel, “SOI compact modeling strategies and challenges for high performance logic applications,” Proc. Asia Pacific Microwave Conference (APMC), New Delhi, India, Dec. 2004, p. 657.

27.      J. X. An, Q. Chen, and Q. Xiang, “Advanced compact modeling of logic devices toward CMOS scaling limits,” Proc. IEEE International Conference on Solid-State and Integrated-Circuit Technology (ICSICT), Beijing, China, Oct. 2004, pp. 1184-1187.

28.      X. Wu, Q. Chen, P. C. H. Chan, and M. Chan, “Three dimensional analytical subthreshold model for non-rectangular cross-section FinFETs,” Proc. IEEE International Conference on Solid-State and Integrated-Circuit Technology (ICSICT), Beijing, China, Oct. 2004, pp. 1200-1203.

29.      J. S. Goo, J. X. An, C. Thuruthiyil, T. Ly, Q. Chen, M. Radwin, Z. Y. Wu, M. S. L. Lee, L. Zamudio, J. Yonemura, F. Assad, M. M. Pelella, and A. B. Icel, “History-effect-conscious SPICE model extraction for PD-SOI technology,” ,” Proc. IEEE International Silicon on Insulator (SOI) Conference, Charleston, SC, Oct. 2004, pp. 156-158.

30.      Q. Chen, L. Wang, and J. D. Meindl, “Quantum mechanical effects on double-gate MOSFET scaling,” Proc. IEEE International Silicon on Insulator (SOI) Conference, Newport Beach, CA, Sep. 2003, pp. 183-184.

31.      L. Wang, Q. Chen, R. Murali, and J. D. Meindl, “Quantum mechanical effects on CMOS SOC performance,” Proc. IEEE International System-on-Chip (SOC) Conference, Portland, OR, Sep. 2003, pp. 17-20.

32.      Q. Chen, L. Wang, and J. D. Meindl, “Impact of high-k dielectrics on undoped double-gate MOSFET scaling,” Proc. IEEE International Silicon on Insulator (SOI) Conference, Williamsburg, VA, Oct. 2002, pp. 115-116.

33.      Q. Chen and J. D. Meindl, “A comparative study of threshold variations in symmetric and asymmetric undoped double-gate MOSFETs,” Proc. IEEE International Silicon on Insulator (SOI) Conference, Williamsburg, VA, Oct. 2002, pp. 30-31.

34.      Q. Chen, J. A. Davis, P. Zarkesh-Ha, and J. D. Meindl, “A novel via blockage model and its implications,” Proc. IEEE International Interconnect Technology Conference, San Francisco, CA, June 2000, pp. 15-17.

35.      S. I. Babkin, V. N. Bliznetsov, and Q. Chen, “Polysilicon reactive ion etching for CMOS VLSI,” Proc. Third All-Russian and International Conference on Actual Problems of Solid State Electronics and Microelectronics, Sep. 1996, Divnomorskoye, Russia, p. 39.

PRESENTATIONS

36.      Q. Chen and J. D. Meindl, “Compact modeling of double-gate MOSFETs: scaling limits and opportunities,” SIGDA Ph.D. Forum at Design Automation Conference (DAC), Anaheim, CA, June 2003.

37.      Q. Chen and J. D. Meindl, “Scaling limits and opportunities of double-gate MOSFETs,” Yamacraw Industrial Advisory Board Conference, Atlanta, GA, Oct. 2002.