Resume
Tuesday October 22, 2002 12:53
History added
Technical evaluation. Tuesday December 25, 2001 11:44
Resume. Tuesday December 25, 2001 11:44
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Mr. Bill Payne
TECHNICAL SUMMARY
EDUCATION/TRAINING PhD Purdue University
EXPERIENCE HIGHLIGHTS Computer Systems Documentation Consultant: Consulting services for hardware and software design interfacing between real-time hardware DOS, Windows 3.11, 95, 98 and 2000 operating systems. 2001 - 2000 pci/cardbus drivers. 1998 - 2000 Performed replacement of VxD with a Windows 98/2000/ Win32 driver model [WDM] mini-driver. Reason for replacement was a WDM driver transfers data between rings 0 and 3 much faster than a VxD. A WDM driver interrupt latency is quite fast. Also a WDM diver is binary compatible between Windows 2000 and 98. Visual C++ 6.0 is the primary language used with some inline assembler. Visual C++ 6.0 is used both at ring 0 and 3. In ring 3 Visual C++ 6.0 interface code is built into a DLL. The DLL acts an intermediary between a Visual Basic 6.0 app and a ring 0 WDM. Numega DriverWorks was used for the skeleton WDM code. As well, of course, both Microsoft 98 and 2000 DDKs. Numega Softlce is used mostly to debug problems in NTKERN and VMM. Can implement NT 3.51 and 4.0 kernel mode drivers. However, the WDM initiative, because of improved performance and simplicity, will likely cause NT kernel mode drivers to be replaced. Internet web design and operation is required for software maintenance and enhancements. Currently operate four websites. 1997 - 1998 A win32 VxD running at ring 0 replaced a DLL running at ring 3 to improve interrupt latency for Windows 98 and 95. The 6.10 MASM-coded DLL mostly used 32 bit instructions. However, it used a 16 bit segmented linkage since it was required to interface to Visual Basic 3.0. Vireo VtoolsD was used to provide skeleton VxD code. Wrote both the ring 0 and 3 codes in a combination of MASM 6.13 and C. 1994 - 1997 An 8052 microcontroller was removed from planer mill hardware and the interface went directly from analog hardware bus boards in a PC. Wrote the real-time [less than I ms response time] code as a MASM 6.10 assembler interrupt handler and port i/o DLL operating at ring 3 interfacing to a Visual Basic 3.0 application running on windows 3.11. The 16 bit 3.11 DLL worked with no changes under Windows 95. 1992 - 1994 Designed and developed, an 8052 microcontroller real-time hardware with a FORTH operating system , which interfaced to analog lumber planer mill hardware. The 8052 microcontroller interfaced to a PC through a serial port. Interface languages were Microsoft assembler and FORTH assembler between external hardware and PC through serial port, parallel port and ISA bus. Designed and built with a physicist-consulting partner a low-noise a/d hardware system for magnetic detection of oil pipeline leaks. The hardware interfaced to a laptop PC. Sandia National Laboratories Sr. Member Technical Staff: Designed, built and programmed the Deployable Seismic Verification System data authenticator for the US/USSR Comprehensive Test Ban Treaty. The design was based on an 80C32. The real-time device algorithm was implemented in hardware. The interface between the algorithm and external hardware was an 80032 running a FORTH operating system. The data authenticator costs approximately $1500; it processes about 20K bytes per second, draws approximately 200 milliamperes, and occupies about 5-3/8 inches diameter by 10-1/2 inches of space. Interfaced Cylink CY-1024 public key crypto chips to an 80032. Designed and built tamper proof containers for CTBT verification devices. Designed and built TEMPEST mechanical and electrical devices. Acted as project leader for the Missile Secure
Cryptographic Unit [MSCU] for the US small missile. The MSCU used an 8085
processor. It was programmed with partially in FORTH and FORTH assembler. The
MSCU interfaced to a PC through two serial ports. Control Data Network Operating System consultant. Washington State University 1966 - 1979 Computer Science and Psychology professor at Washington State University, Pullman, WA. 1972 - 1973 Visiting Research Associate Professor of Computer Science, Department of Computer Science, University of Illinois at Urbana-Champaign, Urbana, IL. ADDITIONAL ASSETS
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PhD students Tuesday December 25, 2001 11:58
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PhD Students T. G. Lewis Computer Science. Currently employed as CEO of DaimlerChrysler Research & Technology, North America. Lewis was department chairman, Navy Postgraduate School, Monterey, CA, two term Editor-in-Chief of IEEE Software, Editor-in-Chief IEEE Computer. J. S. Sobolewski Computer Science. Currently employed as Associate Vice President of Computer Information and Resource Technology and Professor of Electrical Engineering, University of New Mexico. Sobolewski is one of the Maui supercomputer center directors. D. E. Anderson Experimental Psychology. Currently employed as a Psychology professor at Allegheny College. L. E. Banderet Experimental Psychology. Currently employed by the Army Institute of Environmental Medicine. |
Project success is, in large part, knowing as much about what not to do as what to do.
In 1972-3 bill was a visiting research professor at the University of Illinois at Urbana-Champaign.
Bill's job assignment was to help [software] make the Illiac III work.
Bill's supervisor was Jim Robertson, designer of the successful Illiac II.
Faiman’s visit led to the offer of an assistantship, working full time designing ILLIAC II. He recalled the good times spent with Jim Robertson, Don Gillies, Dick Shively, John Penhollow, and Kazuhiro Fuchi at DCL. "We built ILLIAC II, and it actually worked!"
We all soon discovered that there was no way we were going to get Illiac III working. Either hardware or software or the debug system ... a pdp 8e.
Robertson said "It's no fun working on someone else's failing projects."
So we all did other things!
Robertson gave Bill a copy of his student Bruce DeLuglish's Ph.D. thesis.
DeLugish:1970:CAA [DeL70] Bruce Gene DeLugish. A class of algorithms for automatic evaluation of certain elementary functions in a binary computer. Technical Report 399, Department of Computer Science, University of Illinois at Urbana-Champaign,Urbana, Illinois, 1970. 191 pp.
This tells how to compute elementary functions bit-by-bit on a digital computer.
Bill and his students did similar work. But applied their work to Monte Carlo computations.
Payne also worked on partial sorting. Finding the k-th largest element of n without storing all n elements.
The following year Payne taught a graduate course in computer science at Washington State University partially base on the algorithms in DeLuglish's thesis.
Susannah, the girl friend of one of the guys working on
8051 projects, was a
Stanford graduate.
Susannah got fired from a very prestigious
job.
Her boyfriend said, "Stanford University teaches people how to succeed. But not how to fail."
Goal of this site is project success in high tech ventures. Mostly software.
Project success is enhanced by not trying to do too much yourself. And using to your advantage what others have done.
NIH, not invented here, is perhaps one of the more certain ways to lead to project failure. Use other peoples' good stuff.
In 1960 Bill worked on the ElectroData 205
computer at Purdue University.
What he's doing today is more fun because of the operating sytems
like BASIC and FORTH which host interactive incremental compilation and
assembly.
So let's succeed with our Embedded Controller Forth 1 2 3 4 on the Cypress CY3671 EZ-USB-FX Development board Rev D project. And make some money too!
And, most important, have some fun!
But if you see project failure, then do something else which will eventually succeed.
If at first you don't succeed, try again. Then quit. There's no use being a damn fool about it.
W C Fields
(Quoted in The Executive's Book of Quotations compiled by Julia Vitullo-Martin and Robert J. Moskin, page 111, as found in "Movie Talk".)
80C52 SOCs are looking good Monday September 9, 2002 07:30
| 40 years
ago
November 22, 1961 Cover Feature: MW-Tube Power Supplies Have All-Electronic Control Iliac II Computer Shaping Up For Tests Iliac II, the University of Illinois’ scientific computer, is expected to be ready for its first system tests next spring. At that time, the arithmetic units, some of the control units, core storage, and some of the tape units should be completed. At present, the repetitive parts of the arithmetic units have been run error-free, the first 4000 words of core storage are being debugged, and the computer’s special buffer memory—or flow gate—is nearing completion. Illinois project engineers expect the computer to be doing useful work by the end of 1962. The Illiac II is said to be the most asynchronous
These figures are for floating-point operations on 52-bit words, of which 7 bits form an exponent representing a power of 4 and 45 bits the fractional part. Because the university will be the only user of Illiac II, the computer is being built with only 8192 words of core storage, divided into two units. These will be backed up by 65,536 words of storage on magnetic drums having an access time of 7 µsec once in synchronism. Illiac’s designers say that computing time will be slowed only 10% or 15% by the lack of all- core storage, and that the savings in cost of hardware more than compensates for this. One of the basic considerations affecting design of the computer was the inequality in speeds of arithmetic and storage operations. Because of the relative slowness of storage, Illiac II was organized so its programs require as few references to core memory as possible. Also, the core memories are designed to be Fast in themselves and to be used in multiplex. To enhance the effects of these steps, fast controls were designed and the arithmetic unit and input-output devices were linked to the core memories. The design objective was to make the operating time For all devices roughly equal, and to run them concurrently To minimize access to core storage, Illiac is provided with a compact order code, fast storage of short loops, storage of intermediate results through the use of a fast buffer, and an organization that permits concurrent operation of core and arithmetic units, initial decoding of addresses, decoding of instructions, and transfers of memory blocks. Also, to reduce the necessity for access to instructions, word length was increased and instructions were designed to be more powerful than usual for a given number of bits. The number of bits per instruction was reduced. Another design feature allows a number of instructions held in fast transistor registers to be obeyed repeatedly without further reference to the core memory for instruction. To reduce the number of bits per instruction, variable-length instructions are used in the Illinois computer. Long 26-bit instructions are used only where needed. The rest of the time, 13-bit instructions are used. Because the computer is designed to be asynchronous to an unusual degree (which designers call speed-independence), control is critical and achieved in a novel fashion. In addition to interplay control and an arithmetic control that corresponds to the usual delayed control (DC), Illiac includes an advanced control. This circuitry processes every instruction; it’s said to correspond to the memory bus, instruction unit, and look-ahead of the Stretch scientific computer, made by International Business Machines Corp. (ELECTRONIC DESIGN, Nov. 22, 1961, p. 26) Electronic Design November 19, 2001 |
Real world
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