
| Release date | [A]June 10th, 2002; [B]August 21st, 2002 |
| Core name | Thoroughbred B, Barton |
| Number of transistors | [T-bred B]~37.6 Million, [Barton]~54.3 Million |
| Manufacturing Process | .13� |
| Location of L2 cache | On-die |
| Amount of L2 cache | [Tbred-B]256kb, [Barton]512kb |
| Package | microPGA, Socket A/462 |
| Official clock speeds | 1236-2083 MHz |
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