Code Unleash

VHDL

• Some simple VHDL entities & testbenches: This zip file contains some elementary entities(and their testbenches) that we studied in DCS-I. It includes- AND, OR, XOR, JKFF, DFF, DECODER3x8, MUX4x1, FULL_ADDER, BINARY_ADDER(4 bit), BCD_ADDER(4 bit, not working:(), 3-bit COUNTER. All these were compiled and simulated successfully using VHDLSimilie from Sonata.
  
  
• VHDL Experiments: This zip file contains-
  • An 8-bit ALU that instantiates 8 X 1-bit ALU elements and its testbench.
  • A behavioral bcd counter and a structural bcd counter using 4 T-Flip-Flops and their testbenches.
  • A behavioral hex counter and a structural hex counter that uses 4 JK-Flip-Flops and their testbenches.
  • A binary to gray code convertor (that uses a look up table mechanism by converting the input binary code into an index) and its testbench.
  • A data demultiplexer to time-demultiplex 4 bit data to 3X4-bit output lines and its testbench.
  • A simple 2x4 decoder and a 4X2 encoder and their testbenches
  • A generic 6-in-1 D-Flip-Flop (that can either have synchronous or asynchronous reset, it can either be level-triggered (like in a latch) or +ve or -ve edge triggered) and its testbench.
  • A N-bit latch (that instantiates the generic DFF above with synchronous reset and level trigger) and its testbench.
  • A N-bit register (that instantiates the generic DFF above with synchronous reset and -ve edge trigger) and its testbench.
  • A Serial-In-Parallel-Out (SIPO) register (behavioral) and its testbench.
  • A Traffic Light Controller with generic time period that instantiates 2 traffic light record types for a X-junction and its test bench. The traffic light contains 4 signals, Go, Stop, Left and right. For a X-junction it was observed that only 2 instances were sufficient instead of 4 since the lights that were back to back are in identical states at all times.
  • A state-machine to check if the input binary number is divisible by 5 and its testbench.
  • A package called pkg_types that contains some utility types like nibble, nibble_vector, byte, traffic_light, some functions like nibble2natural, a look-up-table for gray2binary conversion, an operator srl for shift right logical of a byte type and procedures for changing the state of the traffic light.
  • Finally, the above library called assign depends on a satellite library called lib which is a renamed version of the dcs1 library above with the testbenches and the bcd adder stripped and a new T-Flip-FLop added.
  All these were compiled and simulated successfully using VHDLSimilie from Sonata.

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