On simple logic the stick diagram often time takes more time then just drawing the layout. However, for more complicated logic gates, layout is almost impossible without a stick diagram.

          ____
     A --|    \ ________
         |     )\       \
     B --|____/  \       \
          ____    )       O-- E
     C --|    \  /       /
         |     )/_______/
     D --|____/

       _________________
   E = (A * B) + (C * D)

         _______
            |
           ---
         _|   |_
    A_o||       ||o_B
       ||_     _||
          |___|
            |
           ---
         _|   |_
    C_o||       ||o_D
       ||_     _||
          |___|
            |
          ___________ E
         |     |
        _|     |_
    A_||         ||_C
      ||_       _||
         |     |
        _|     |_
    B_||         ||_D
      ||_       _||
         |     |
         |_____|
            |
           ---
           \ /
            v

For this logic gate, there are 4 inputs, and 8 transistors.

       |     |     |     |
       |     |     |     |
 P ---------------------------
       |     |     |     |
       |     |     |     |
       |     |     |     |
 N ---------------------------
       |     |     |     |
       |     |     |     |

For complicated gates, such as this, it is often times best to consider all gates at once. VSS is on one side of B, through A, then to the output E. VSS is also on one side of D, through C, then also to the output E. To keep capacitance down, E should be in the middle, and the two parallel paths to the left and right.

       |     |     |     |
       |     |     |     |
 P ---------------------------
       |     |     |     |
       |     |   _/|\___/|\__ E
       |     |  |  |     |
 N -x-----------x-----------x-
    |  |     |     |     |  |
    |  |     |     |     |  |

   VSS B     A     C     D VSS

The P-FETs can be tricky. Looking at the transistor level schematic, notice that output E goes to both transistor C and D. Again, to keep capacitance down, E should be between them.

       |     |     |     |
       |     |     |     |
 P -------------------x-------
       |     |     |  |  |
       |     |   _/|\_|_/|\__ E
       |     |  |  |     |
 N -x-----------x-----------x-
    |  |     |     |     |  |
    |  |     |     |     |  |

   VSS B     A     C     D VSS

The other sides of both C and D should be connected together, and then go into both A and B. VCC is on the other side of A and B. C and A are already next to each other, so connecting the far side of D and B to that same area will give the correct connection. VCC should go between A and B.

                 __________
         VCC    |          |
       |  |  |  |  |     | |
       |  |  |  |  |     | |
 P -x-----x-----x-----x----x--
    |_/|\___/|\_|  |  |  |
       |     |   _/|\_|_/|\__ E
       |     |  |  |     |
 N -x-----------x-----------x-
    |  |     |     |     |  |
    |  |     |     |     |  |

   VSS B     A     C     D VSS

This is the stick diagram for the above complex logic gate. Without a stick diagram, laying this out would be very difficult.