Knowing how to do basic transistor level schematics for NAND, NOR, and INVERTER gates, addressing something harder is now possible.

          ____
     A --|    \ ________
         |     )\       \
     B --|____/  \       \
          ____    )       O-- E
     C --|    \  /       /
         |     )/_______/
     D --|____/

       _________________
   E = (A * B) + (C * D)

For E to meet the condition (remember, when that happens, E will become logical 0), either A AND B must be true, OR C AND D. In other words, one choice is to have A AND B, the other choice is to have C AND D. Either choice will work, but the choice must be met exactly. The N-FET transistors for this gate will look like...

          ___________ E
         |     |
        _|     |_
    A_||         ||_C
      ||_       _||
         |     |
        _|     |_
    B_||         ||_D
      ||_       _||
         |     |
         |_____|
            |
           ---
           \ /
            v

Notice that there are two paths that E can take to get to ground. The first path is A AND B, the second is C AND D. In the equation, there is a set of parentheses around A*B and another around C*D. They indicate that A*B is a path, and C*D is another. The entire transistor level schematic (including the P-FETs) is...

         _______
            |
           ---
         _|   |_
    A_o||       ||o_B
       ||_     _||
          |___|
            |
           ---
         _|   |_
    C_o||       ||o_D
       ||_     _||
          |___|
            |
          ___________ E
         |     |
        _|     |_
    A_||         ||_C
      ||_       _||
         |     |
        _|     |_
    B_||         ||_D
      ||_       _||
         |     |
         |_____|
            |
           ---
           \ /
            v

For the N-FETs, path AB and path CD were parallel, so In the P-FETs they are in series. In the AB path the gates were in series, so in the P-FETs they are in parallel (same with the CD path).

Other "complex logic" gate configurations can also be solved.

          ____
     F --\    \  _______
          )    )|       \
     G --/____/ |        \
          ____  |         O-- J
     H --\    \ |        /
          )    )|_______/
     I --/____/

       _________________
   J = (F + G) * (H + I)

This gate looks similar, and is just as difficult. Paying close attention to the equation, such as what is in the parentheses, will uncover the N-FET transistor schematic.

             _______ J
            |
           ---
         _|   |_
     F_||       ||_G
       ||_     _||
          |___|
            |
           ---
         _|   |_
     H_||       ||_I
       ||_     _||
          |___|
            |
           ---
           \ /
            v

Notice that the formula indicated a series circuit (the central AND function). However, what is in series are two parallel circuits (the OR functions located in the parentheses). These two groups (F+G an H+I), while parallel within the group, are in series with each other. The full circuit (including P-FETs) is...

         _______
            |
          _____
         |     |
        _|     |_
   F_o||         ||o_H
      ||_       _||
         |     |
        _|     |_
   G_o||         ||o_I
      ||_       _||
         |     |
         |_____|
            |
           ______________ J
         _|   |_
     F_||       ||_G
       ||_     _||
          |___|
            |
           ---
         _|   |_
     H_||       ||_I
       ||_     _||
          |___|
            |
           ---
           \ /
            v

F and G were in parallel for the N-FETs, for the P-FETs they are in series (same with H and I). These two paths (FG and HI) were in series in the N-FETs, so for the P-FETs they are in parallel.